lib/main/STM32F1/Drivers/CMSIS/Include/core_cm0.h

   1 /**************************************************************************//**
   2  * @file     core_cm0.h
   3  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
   4  * @version  V4.30
   5  * @date     20. October 2015
   6  ******************************************************************************/
   7 /* Copyright (c) 2009 - 2015 ARM LIMITED
   8
   9    All rights reserved.
  10    Redistribution and use in source and binary forms, with or without
  11    modification, are permitted provided that the following conditions are met:
  12    - Redistributions of source code must retain the above copyright
  13      notice, this list of conditions and the following disclaimer.
  14    - Redistributions in binary form must reproduce the above copyright
  15      notice, this list of conditions and the following disclaimer in the
  16      documentation and/or other materials provided with the distribution.
  17    - Neither the name of ARM nor the names of its contributors may be used
  18      to endorse or promote products derived from this software without
  19      specific prior written permission.
  20    *
  21    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  25    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31    POSSIBILITY OF SUCH DAMAGE.
  32    ---------------------------------------------------------------------------*/
  33
  34
  35 #if   defined ( __ICCARM__ )
  36  #pragma system_include         /* treat file as system include file for MISRA check */
  37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  38   #pragma clang system_header   /* treat file as system include file */
  39 #endif
  40
  41 #ifndef __CORE_CM0_H_GENERIC
  42 #define __CORE_CM0_H_GENERIC
  43
  44 #include <stdint.h>
  45
  46 #ifdef __cplusplus
  47  extern "C" {
  48 #endif
  49
  50 /**
  51   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  52   CMSIS violates the following MISRA-C:2004 rules:
  53
  54    \li Required Rule 8.5, object/function definition in header file.<br>
  55      Function definitions in header files are used to allow 'inlining'.
  56
  57    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  58      Unions are used for effective representation of core registers.
  59
  60    \li Advisory Rule 19.7, Function-like macro defined.<br>
  61      Function-like macros are used to allow more efficient code.
  62  */
  63
  64
  65 /*******************************************************************************
  66  *                 CMSIS definitions
  67  ******************************************************************************/
  68 /**
  69   \ingroup Cortex_M0
  70   @{
  71  */
  72
  73 /*  CMSIS CM0 definitions */
  74 #define __CM0_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
  75 #define __CM0_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
  76 #define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
  77                                     __CM0_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
  78
  79 #define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */
  80
  81
  82 #if   defined ( __CC_ARM )
  83   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
  84   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
  85   #define __STATIC_INLINE  static __inline
  86
  87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  88   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
  89   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
  90   #define __STATIC_INLINE  static __inline
  91
  92 #elif defined ( __GNUC__ )
  93   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
  94   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
  95   #define __STATIC_INLINE  static inline
  96
  97 #elif defined ( __ICCARM__ )
  98   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
  99   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
 100   #define __STATIC_INLINE  static inline
 101
 102 #elif defined ( __TMS470__ )
 103   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
 104   #define __STATIC_INLINE  static inline
 105
 106 #elif defined ( __TASKING__ )
 107   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
 108   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
 109   #define __STATIC_INLINE  static inline
 110
 111 #elif defined ( __CSMC__ )
 112   #define __packed
 113   #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
 114   #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
 115   #define __STATIC_INLINE  static inline
 116
 117 #else
 118   #error Unknown compiler
 119 #endif
 120
 121 /** __FPU_USED indicates whether an FPU is used or not.
 122     This core does not support an FPU at all
 123 */
 124 #define __FPU_USED       0U
 125
 126 #if defined ( __CC_ARM )
 127   #if defined __TARGET_FPU_VFP
 128     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 129   #endif
 130
 131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
 132   #if defined __ARM_PCS_VFP
 133     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 134   #endif
 135
 136 #elif defined ( __GNUC__ )
 137   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
 138     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 139   #endif
 140
 141 #elif defined ( __ICCARM__ )
 142   #if defined __ARMVFP__
 143     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 144   #endif
 145
 146 #elif defined ( __TMS470__ )
 147   #if defined __TI_VFP_SUPPORT__
 148     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 149   #endif
 150
 151 #elif defined ( __TASKING__ )
 152   #if defined __FPU_VFP__
 153     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 154   #endif
 155
 156 #elif defined ( __CSMC__ )
 157   #if ( __CSMC__ & 0x400U)
 158     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 159   #endif
 160
 161 #endif
 162
 163 #include "core_cmInstr.h"                /* Core Instruction Access */
 164 #include "core_cmFunc.h"                 /* Core Function Access */
 165
 166 #ifdef __cplusplus
 167 }
 168 #endif
 169
 170 #endif /* __CORE_CM0_H_GENERIC */
 171
 172 #ifndef __CMSIS_GENERIC
 173
 174 #ifndef __CORE_CM0_H_DEPENDANT
 175 #define __CORE_CM0_H_DEPENDANT
 176
 177 #ifdef __cplusplus
 178  extern "C" {
 179 #endif
 180
 181 /* check device defines and use defaults */
 182 #if defined __CHECK_DEVICE_DEFINES
 183   #ifndef __CM0_REV
 184     #define __CM0_REV               0x0000U
 185     #warning "__CM0_REV not defined in device header file; using default!"
 186   #endif
 187
 188   #ifndef __NVIC_PRIO_BITS
 189     #define __NVIC_PRIO_BITS          2U
 190     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
 191   #endif
 192
 193   #ifndef __Vendor_SysTickConfig
 194     #define __Vendor_SysTickConfig    0U
 195     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
 196   #endif
 197 #endif
 198
 199 /* IO definitions (access restrictions to peripheral registers) */
 200 /**
 201     \defgroup CMSIS_glob_defs CMSIS Global Defines
 202
 203     <strong>IO Type Qualifiers</strong> are used
 204     \li to specify the access to peripheral variables.
 205     \li for automatic generation of peripheral register debug information.
 206 */
 207 #ifdef __cplusplus
 208   #define   __I     volatile             /*!< Defines 'read only' permissions */
 209 #else
 210   #define   __I     volatile const       /*!< Defines 'read only' permissions */
 211 #endif
 212 #define     __O     volatile             /*!< Defines 'write only' permissions */
 213 #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 214
 215 /* following defines should be used for structure members */
 216 #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 217 #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 218 #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 219
 220 /*@} end of group Cortex_M0 */
 221
 222
 223
 224 /*******************************************************************************
 225  *                 Register Abstraction
 226   Core Register contain:
 227   - Core Register
 228   - Core NVIC Register
 229   - Core SCB Register
 230   - Core SysTick Register
 231  ******************************************************************************/
 232 /**
 233   \defgroup CMSIS_core_register Defines and Type Definitions
 234   \brief Type definitions and defines for Cortex-M processor based devices.
 235 */
 236
 237 /**
 238   \ingroup    CMSIS_core_register
 239   \defgroup   CMSIS_CORE  Status and Control Registers
 240   \brief      Core Register type definitions.
 241   @{
 242  */
 243
 244 /**
 245   \brief  Union type to access the Application Program Status Register (APSR).
 246  */
 247 typedef union
 248 {
 249   struct
 250   {
 251     uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
 252     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 253     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 254     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 255     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 256   } b;                                   /*!< Structure used for bit  access */
 257   uint32_t w;                            /*!< Type      used for word access */
 258 } APSR_Type;
 259
 260 /* APSR Register Definitions */
 261 #define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
 262 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 263
 264 #define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
 265 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 266
 267 #define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
 268 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 269
 270 #define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
 271 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 272
 273
 274 /**
 275   \brief  Union type to access the Interrupt Program Status Register (IPSR).
 276  */
 277 typedef union
 278 {
 279   struct
 280   {
 281     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 282     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
 283   } b;                                   /*!< Structure used for bit  access */
 284   uint32_t w;                            /*!< Type      used for word access */
 285 } IPSR_Type;
 286
 287 /* IPSR Register Definitions */
 288 #define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
 289 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 290
 291
 292 /**
 293   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 294  */
 295 typedef union
 296 {
 297   struct
 298   {
 299     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 300     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
 301     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
 302     uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
 303     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 304     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 305     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 306     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 307   } b;                                   /*!< Structure used for bit  access */
 308   uint32_t w;                            /*!< Type      used for word access */
 309 } xPSR_Type;
 310
 311 /* xPSR Register Definitions */
 312 #define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
 313 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 314
 315 #define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
 316 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 317
 318 #define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
 319 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 320
 321 #define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
 322 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 323
 324 #define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 325 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 326
 327 #define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 328 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 329
 330
 331 /**
 332   \brief  Union type to access the Control Registers (CONTROL).
 333  */
 334 typedef union
 335 {
 336   struct
 337   {
 338     uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
 339     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
 340     uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
 341   } b;                                   /*!< Structure used for bit  access */
 342   uint32_t w;                            /*!< Type      used for word access */
 343 } CONTROL_Type;
 344
 345 /* CONTROL Register Definitions */
 346 #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
 347 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 348
 349 /*@} end of group CMSIS_CORE */
 350
 351
 352 /**
 353   \ingroup    CMSIS_core_register
 354   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
 355   \brief      Type definitions for the NVIC Registers
 356   @{
 357  */
 358
 359 /**
 360   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 361  */
 362 typedef struct
 363 {
 364   __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
 365         uint32_t RESERVED0[31U];
 366   __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
 367         uint32_t RSERVED1[31U];
 368   __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
 369         uint32_t RESERVED2[31U];
 370   __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
 371         uint32_t RESERVED3[31U];
 372         uint32_t RESERVED4[64U];
 373   __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 374 }  NVIC_Type;
 375
 376 /*@} end of group CMSIS_NVIC */
 377
 378
 379 /**
 380   \ingroup  CMSIS_core_register
 381   \defgroup CMSIS_SCB     System Control Block (SCB)
 382   \brief    Type definitions for the System Control Block Registers
 383   @{
 384  */
 385
 386 /**
 387   \brief  Structure type to access the System Control Block (SCB).
 388  */
 389 typedef struct
 390 {
 391   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
 392   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
 393         uint32_t RESERVED0;
 394   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
 395   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
 396   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
 397         uint32_t RESERVED1;
 398   __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
 399   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
 400 } SCB_Type;
 401
 402 /* SCB CPUID Register Definitions */
 403 #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
 404 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 405
 406 #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
 407 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 408
 409 #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
 410 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 411
 412 #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
 413 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 414
 415 #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
 416 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 417
 418 /* SCB Interrupt Control State Register Definitions */
 419 #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
 420 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 421
 422 #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
 423 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 424
 425 #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
 426 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 427
 428 #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
 429 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 430
 431 #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
 432 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 433
 434 #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
 435 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 436
 437 #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
 438 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 439
 440 #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
 441 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 442
 443 #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
 444 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 445
 446 /* SCB Application Interrupt and Reset Control Register Definitions */
 447 #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
 448 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 449
 450 #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
 451 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 452
 453 #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
 454 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 455
 456 #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
 457 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 458
 459 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
 460 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 461
 462 /* SCB System Control Register Definitions */
 463 #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
 464 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 465
 466 #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
 467 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 468
 469 #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
 470 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 471
 472 /* SCB Configuration Control Register Definitions */
 473 #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
 474 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 475
 476 #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
 477 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 478
 479 /* SCB System Handler Control and State Register Definitions */
 480 #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
 481 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 482
 483 /*@} end of group CMSIS_SCB */
 484
 485
 486 /**
 487   \ingroup  CMSIS_core_register
 488   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
 489   \brief    Type definitions for the System Timer Registers.
 490   @{
 491  */
 492
 493 /**
 494   \brief  Structure type to access the System Timer (SysTick).
 495  */
 496 typedef struct
 497 {
 498   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
 499   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
 500   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
 501   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 502 } SysTick_Type;
 503
 504 /* SysTick Control / Status Register Definitions */
 505 #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
 506 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 507
 508 #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
 509 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 510
 511 #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
 512 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 513
 514 #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
 515 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 516
 517 /* SysTick Reload Register Definitions */
 518 #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
 519 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 520
 521 /* SysTick Current Register Definitions */
 522 #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
 523 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 524
 525 /* SysTick Calibration Register Definitions */
 526 #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
 527 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 528
 529 #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
 530 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 531
 532 #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
 533 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 534
 535 /*@} end of group CMSIS_SysTick */
 536
 537
 538 /**
 539   \ingroup  CMSIS_core_register
 540   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
 541   \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
 542             Therefore they are not covered by the Cortex-M0 header file.
 543   @{
 544  */
 545 /*@} end of group CMSIS_CoreDebug */
 546
 547
 548 /**
 549   \ingroup    CMSIS_core_register
 550   \defgroup   CMSIS_core_bitfield     Core register bit field macros
 551   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
 552   @{
 553  */
 554
 555 /**
 556   \brief   Mask and shift a bit field value for use in a register bit range.
 557   \param[in] field  Name of the register bit field.
 558   \param[in] value  Value of the bit field.
 559   \return           Masked and shifted value.
 560 */
 561 #define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
 562
 563 /**
 564   \brief     Mask and shift a register value to extract a bit filed value.
 565   \param[in] field  Name of the register bit field.
 566   \param[in] value  Value of register.
 567   \return           Masked and shifted bit field value.
 568 */
 569 #define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
 570
 571 /*@} end of group CMSIS_core_bitfield */
 572
 573
 574 /**
 575   \ingroup    CMSIS_core_register
 576   \defgroup   CMSIS_core_base     Core Definitions
 577   \brief      Definitions for base addresses, unions, and structures.
 578   @{
 579  */
 580
 581 /* Memory mapping of Cortex-M0 Hardware */
 582 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 583 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
 584 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
 585 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 586
 587 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
 588 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
 589 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
 590
 591
 592 /*@} */
 593
 594
 595
 596 /*******************************************************************************
 597  *                Hardware Abstraction Layer
 598   Core Function Interface contains:
 599   - Core NVIC Functions
 600   - Core SysTick Functions
 601   - Core Register Access Functions
 602  ******************************************************************************/
 603 /**
 604   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 605 */
 606
 607
 608
 609 /* ##########################   NVIC functions  #################################### */
 610 /**
 611   \ingroup  CMSIS_Core_FunctionInterface
 612   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
 613   \brief    Functions that manage interrupts and exceptions via the NVIC.
 614   @{
 615  */
 616
 617 /* Interrupt Priorities are WORD accessible only under ARMv6M                   */
 618 /* The following MACROS handle generation of the register offset and byte masks */
 619 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 620 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 621 #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 622
 623
 624 /**
 625   \brief   Enable External Interrupt
 626   \details Enables a device-specific interrupt in the NVIC interrupt controller.
 627   \param [in]      IRQn  External interrupt number. Value cannot be negative.
 628  */
 629 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 630 {
 631   NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 632 }
 633
 634
 635 /**
 636   \brief   Disable External Interrupt
 637   \details Disables a device-specific interrupt in the NVIC interrupt controller.
 638   \param [in]      IRQn  External interrupt number. Value cannot be negative.
 639  */
 640 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 641 {
 642   NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 643 }
 644
 645
 646 /**
 647   \brief   Get Pending Interrupt
 648   \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
 649   \param [in]      IRQn  Interrupt number.
 650   \return             0  Interrupt status is not pending.
 651   \return             1  Interrupt status is pending.
 652  */
 653 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 654 {
 655   return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 656 }
 657
 658
 659 /**
 660   \brief   Set Pending Interrupt
 661   \details Sets the pending bit of an external interrupt.
 662   \param [in]      IRQn  Interrupt number. Value cannot be negative.
 663  */
 664 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 665 {
 666   NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 667 }
 668
 669
 670 /**
 671   \brief   Clear Pending Interrupt
 672   \details Clears the pending bit of an external interrupt.
 673   \param [in]      IRQn  External interrupt number. Value cannot be negative.
 674  */
 675 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 676 {
 677   NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 678 }
 679
 680
 681 /**
 682   \brief   Set Interrupt Priority
 683   \details Sets the priority of an interrupt.
 684   \note    The priority cannot be set for every core interrupt.
 685   \param [in]      IRQn  Interrupt number.
 686   \param [in]  priority  Priority to set.
 687  */
 688 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 689 {
 690   if ((int32_t)(IRQn) < 0)
 691   {
 692     SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 693        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 694   }
 695   else
 696   {
 697     NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 698        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 699   }
 700 }
 701
 702
 703 /**
 704   \brief   Get Interrupt Priority
 705   \details Reads the priority of an interrupt.
 706            The interrupt number can be positive to specify an external (device specific) interrupt,
 707            or negative to specify an internal (core) interrupt.
 708   \param [in]   IRQn  Interrupt number.
 709   \return             Interrupt Priority.
 710                       Value is aligned automatically to the implemented priority bits of the microcontroller.
 711  */
 712 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 713 {
 714
 715   if ((int32_t)(IRQn) < 0)
 716   {
 717     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
 718   }
 719   else
 720   {
 721     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
 722   }
 723 }
 724
 725
 726 /**
 727   \brief   System Reset
 728   \details Initiates a system reset request to reset the MCU.
 729  */
 730 __STATIC_INLINE void NVIC_SystemReset(void)
 731 {
 732   __DSB();                                                          /* Ensure all outstanding memory accesses included
 733                                                                        buffered write are completed before reset */
 734   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 735                  SCB_AIRCR_SYSRESETREQ_Msk);
 736   __DSB();                                                          /* Ensure completion of memory access */
 737
 738   for(;;)                                                           /* wait until reset */
 739   {
 740     __NOP();
 741   }
 742 }
 743
 744 /*@} end of CMSIS_Core_NVICFunctions */
 745
 746
 747
 748 /* ##################################    SysTick function  ############################################ */
 749 /**
 750   \ingroup  CMSIS_Core_FunctionInterface
 751   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
 752   \brief    Functions that configure the System.
 753   @{
 754  */
 755
 756 #if (__Vendor_SysTickConfig == 0U)
 757
 758 /**
 759   \brief   System Tick Configuration
 760   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
 761            Counter is in free running mode to generate periodic interrupts.
 762   \param [in]  ticks  Number of ticks between two interrupts.
 763   \return          0  Function succeeded.
 764   \return          1  Function failed.
 765   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
 766            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
 767            must contain a vendor-specific implementation of this function.
 768  */
 769 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 770 {
 771   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 772   {
 773     return (1UL);                                                   /* Reload value impossible */
 774   }
 775
 776   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 777   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 778   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 779   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 780                    SysTick_CTRL_TICKINT_Msk   |
 781                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
 782   return (0UL);                                                     /* Function successful */
 783 }
 784
 785 #endif
 786
 787 /*@} end of CMSIS_Core_SysTickFunctions */
 788
 789
 790
 791
 792 #ifdef __cplusplus
 793 }
 794 #endif
 795
 796 #endif /* __CORE_CM0_H_DEPENDANT */
 797
 798 #endif /* __CMSIS_GENERIC */