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F1 and F3 HAL / LL libraries
[betaflight.git] / lib / main / STM32F1 / Drivers / CMSIS / Device / ST / STM32F1xx / Include / stm32f101xb.h
blob937307cca45ad055d959824d6533a6b39654fda7
1 /**
2 ******************************************************************************
3 * @file stm32f101xb.h
4 * @author MCD Application Team
5 * @version V4.2.0
6 * @date 31-March-2017
7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
8 * This file contains all the peripheral register's definitions, bits
9 * definitions and memory mapping for STM32F1xx devices.
10 *
11 * This file contains:
12 * - Data structures and the address mapping for all peripherals
13 * - Peripheral's registers declarations and bits definition
14 * - Macros to access peripheral’s registers hardware
15 *
16 ******************************************************************************
17 * @attention
18 *
19 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
20 *
21 * Redistribution and use in source and binary forms, with or without modification,
22 * are permitted provided that the following conditions are met:
23 * 1. Redistributions of source code must retain the above copyright notice,
24 * this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright notice,
26 * this list of conditions and the following disclaimer in the documentation
27 * and/or other materials provided with the distribution.
28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ******************************************************************************
44 */
45
46
47 /** @addtogroup CMSIS
48 * @{
49 */
50
51 /** @addtogroup stm32f101xb
52 * @{
53 */
54
55 #ifndef __STM32F101xB_H
56 #define __STM32F101xB_H
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 /** @addtogroup Configuration_section_for_CMSIS
63 * @{
64 */
65 /**
66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
67 */
68 #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
69 #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
70 #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
71 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
72
73 /**
74 * @}
75 */
76
77 /** @addtogroup Peripheral_interrupt_number_definition
78 * @{
79 */
80
81 /**
82 * @brief STM32F10x Interrupt Number Definition, according to the selected device
83 * in @ref Library_configuration_section
84 */
85
86 /*!< Interrupt Number Definition */
87 typedef enum
88 {
89 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
91 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
92 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
93 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
94 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
95 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
96 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
97 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
98 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
99
100 /****** STM32 specific Interrupt Numbers *********************************************************/
101 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
102 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
103 TAMPER_IRQn = 2, /*!< Tamper Interrupt */
104 RTC_IRQn = 3, /*!< RTC global Interrupt */
105 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
106 RCC_IRQn = 5, /*!< RCC global Interrupt */
107 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
108 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
109 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
110 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
111 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
112 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
113 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
114 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
115 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
116 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
117 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
118 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
119 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
121 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
122 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
123 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
124 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
125 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
126 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
127 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
129 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
130 USART1_IRQn = 37, /*!< USART1 global Interrupt */
131 USART2_IRQn = 38, /*!< USART2 global Interrupt */
132 USART3_IRQn = 39, /*!< USART3 global Interrupt */
133 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
134 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
135 } IRQn_Type;
136
137 /**
138 * @}
139 */
140
141 #include "core_cm3.h"
142 #include "system_stm32f1xx.h"
143 #include <stdint.h>
144
145 /** @addtogroup Peripheral_registers_structures
146 * @{
147 */
148
149 /**
150 * @brief Analog to Digital Converter
151 */
152
153 typedef struct
154 {
155 __IO uint32_t SR;
156 __IO uint32_t CR1;
157 __IO uint32_t CR2;
158 __IO uint32_t SMPR1;
159 __IO uint32_t SMPR2;
160 __IO uint32_t JOFR1;
161 __IO uint32_t JOFR2;
162 __IO uint32_t JOFR3;
163 __IO uint32_t JOFR4;
164 __IO uint32_t HTR;
165 __IO uint32_t LTR;
166 __IO uint32_t SQR1;
167 __IO uint32_t SQR2;
168 __IO uint32_t SQR3;
169 __IO uint32_t JSQR;
170 __IO uint32_t JDR1;
171 __IO uint32_t JDR2;
172 __IO uint32_t JDR3;
173 __IO uint32_t JDR4;
174 __IO uint32_t DR;
175 } ADC_TypeDef;
176
177 typedef struct
178 {
179 __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
180 __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
181 __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
182 uint32_t RESERVED[16];
183 __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
184 } ADC_Common_TypeDef;
185
186 /**
187 * @brief Backup Registers
188 */
189
190 typedef struct
191 {
192 uint32_t RESERVED0;
193 __IO uint32_t DR1;
194 __IO uint32_t DR2;
195 __IO uint32_t DR3;
196 __IO uint32_t DR4;
197 __IO uint32_t DR5;
198 __IO uint32_t DR6;
199 __IO uint32_t DR7;
200 __IO uint32_t DR8;
201 __IO uint32_t DR9;
202 __IO uint32_t DR10;
203 __IO uint32_t RTCCR;
204 __IO uint32_t CR;
205 __IO uint32_t CSR;
206 } BKP_TypeDef;
207
208
209 /**
210 * @brief CRC calculation unit
211 */
212
213 typedef struct
214 {
215 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
216 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
217 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
218 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
219 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
220 } CRC_TypeDef;
221
222
223 /**
224 * @brief Debug MCU
225 */
226
227 typedef struct
228 {
229 __IO uint32_t IDCODE;
230 __IO uint32_t CR;
231 }DBGMCU_TypeDef;
232
233 /**
234 * @brief DMA Controller
235 */
236
237 typedef struct
238 {
239 __IO uint32_t CCR;
240 __IO uint32_t CNDTR;
241 __IO uint32_t CPAR;
242 __IO uint32_t CMAR;
243 } DMA_Channel_TypeDef;
244
245 typedef struct
246 {
247 __IO uint32_t ISR;
248 __IO uint32_t IFCR;
249 } DMA_TypeDef;
250
251
252
253 /**
254 * @brief External Interrupt/Event Controller
255 */
256
257 typedef struct
258 {
259 __IO uint32_t IMR;
260 __IO uint32_t EMR;
261 __IO uint32_t RTSR;
262 __IO uint32_t FTSR;
263 __IO uint32_t SWIER;
264 __IO uint32_t PR;
265 } EXTI_TypeDef;
266
267 /**
268 * @brief FLASH Registers
269 */
270
271 typedef struct
272 {
273 __IO uint32_t ACR;
274 __IO uint32_t KEYR;
275 __IO uint32_t OPTKEYR;
276 __IO uint32_t SR;
277 __IO uint32_t CR;
278 __IO uint32_t AR;
279 __IO uint32_t RESERVED;
280 __IO uint32_t OBR;
281 __IO uint32_t WRPR;
282 } FLASH_TypeDef;
283
284 /**
285 * @brief Option Bytes Registers
286 */
287
288 typedef struct
289 {
290 __IO uint16_t RDP;
291 __IO uint16_t USER;
292 __IO uint16_t Data0;
293 __IO uint16_t Data1;
294 __IO uint16_t WRP0;
295 __IO uint16_t WRP1;
296 __IO uint16_t WRP2;
297 __IO uint16_t WRP3;
298 } OB_TypeDef;
299
300 /**
301 * @brief General Purpose I/O
302 */
303
304 typedef struct
305 {
306 __IO uint32_t CRL;
307 __IO uint32_t CRH;
308 __IO uint32_t IDR;
309 __IO uint32_t ODR;
310 __IO uint32_t BSRR;
311 __IO uint32_t BRR;
312 __IO uint32_t LCKR;
313 } GPIO_TypeDef;
314
315 /**
316 * @brief Alternate Function I/O
317 */
318
319 typedef struct
320 {
321 __IO uint32_t EVCR;
322 __IO uint32_t MAPR;
323 __IO uint32_t EXTICR[4];
324 uint32_t RESERVED0;
325 __IO uint32_t MAPR2;
326 } AFIO_TypeDef;
327 /**
328 * @brief Inter Integrated Circuit Interface
329 */
330
331 typedef struct
332 {
333 __IO uint32_t CR1;
334 __IO uint32_t CR2;
335 __IO uint32_t OAR1;
336 __IO uint32_t OAR2;
337 __IO uint32_t DR;
338 __IO uint32_t SR1;
339 __IO uint32_t SR2;
340 __IO uint32_t CCR;
341 __IO uint32_t TRISE;
342 } I2C_TypeDef;
343
344 /**
345 * @brief Independent WATCHDOG
346 */
347
348 typedef struct
349 {
350 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
351 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
352 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
353 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
354 } IWDG_TypeDef;
355
356 /**
357 * @brief Power Control
358 */
359
360 typedef struct
361 {
362 __IO uint32_t CR;
363 __IO uint32_t CSR;
364 } PWR_TypeDef;
365
366 /**
367 * @brief Reset and Clock Control
368 */
369
370 typedef struct
371 {
372 __IO uint32_t CR;
373 __IO uint32_t CFGR;
374 __IO uint32_t CIR;
375 __IO uint32_t APB2RSTR;
376 __IO uint32_t APB1RSTR;
377 __IO uint32_t AHBENR;
378 __IO uint32_t APB2ENR;
379 __IO uint32_t APB1ENR;
380 __IO uint32_t BDCR;
381 __IO uint32_t CSR;
382
383
384 } RCC_TypeDef;
385
386 /**
387 * @brief Real-Time Clock
388 */
389
390 typedef struct
391 {
392 __IO uint32_t CRH;
393 __IO uint32_t CRL;
394 __IO uint32_t PRLH;
395 __IO uint32_t PRLL;
396 __IO uint32_t DIVH;
397 __IO uint32_t DIVL;
398 __IO uint32_t CNTH;
399 __IO uint32_t CNTL;
400 __IO uint32_t ALRH;
401 __IO uint32_t ALRL;
402 } RTC_TypeDef;
403
404 /**
405 * @brief SD host Interface
406 */
407
408 typedef struct
409 {
410 __IO uint32_t POWER;
411 __IO uint32_t CLKCR;
412 __IO uint32_t ARG;
413 __IO uint32_t CMD;
414 __I uint32_t RESPCMD;
415 __I uint32_t RESP1;
416 __I uint32_t RESP2;
417 __I uint32_t RESP3;
418 __I uint32_t RESP4;
419 __IO uint32_t DTIMER;
420 __IO uint32_t DLEN;
421 __IO uint32_t DCTRL;
422 __I uint32_t DCOUNT;
423 __I uint32_t STA;
424 __IO uint32_t ICR;
425 __IO uint32_t MASK;
426 uint32_t RESERVED0[2];
427 __I uint32_t FIFOCNT;
428 uint32_t RESERVED1[13];
429 __IO uint32_t FIFO;
430 } SDIO_TypeDef;
431
432 /**
433 * @brief Serial Peripheral Interface
434 */
435
436 typedef struct
437 {
438 __IO uint32_t CR1;
439 __IO uint32_t CR2;
440 __IO uint32_t SR;
441 __IO uint32_t DR;
442 __IO uint32_t CRCPR;
443 __IO uint32_t RXCRCR;
444 __IO uint32_t TXCRCR;
445 __IO uint32_t I2SCFGR;
446 } SPI_TypeDef;
447
448 /**
449 * @brief TIM Timers
450 */
451 typedef struct
452 {
453 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
454 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
455 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
456 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
457 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
458 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
459 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
460 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
461 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
462 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
463 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
464 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
465 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
466 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
467 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
468 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
469 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
470 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
471 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
472 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
473 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
474 }TIM_TypeDef;
475
476
477 /**
478 * @brief Universal Synchronous Asynchronous Receiver Transmitter
479 */
480
481 typedef struct
482 {
483 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
484 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
485 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
486 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
487 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
488 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
489 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
490 } USART_TypeDef;
491
492
493
494 /**
495 * @brief Window WATCHDOG
496 */
497
498 typedef struct
499 {
500 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
501 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
502 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
503 } WWDG_TypeDef;
504
505 /**
506 * @}
507 */
508
509 /** @addtogroup Peripheral_memory_map
510 * @{
511 */
512
513
514 #define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
515 #define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
516 #define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
517 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
518
519 #define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
520 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
521
522
523 /*!< Peripheral memory map */
524 #define APB1PERIPH_BASE PERIPH_BASE
525 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
526 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
527
528 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
529 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
530 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
531 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
532 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
533 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
534 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
535 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
536 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
537 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
538 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
539 #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
540 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
541 #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
542 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
543 #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
544 #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
545 #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
546 #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
547 #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
548 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
549 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
550 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
551
552 #define SDIO_BASE (PERIPH_BASE + 0x00018000U)
553
554 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
555 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
556 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
557 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
558 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
559 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
560 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
561 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
562 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
563 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
564
565 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
566 #define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
567 #define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
568 #define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
569
570
571
572 #define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
573
574
575
576 /**
577 * @}
578 */
579
580 /** @addtogroup Peripheral_declaration
581 * @{
582 */
583
584 #define TIM2 ((TIM_TypeDef *)TIM2_BASE)
585 #define TIM3 ((TIM_TypeDef *)TIM3_BASE)
586 #define TIM4 ((TIM_TypeDef *)TIM4_BASE)
587 #define RTC ((RTC_TypeDef *)RTC_BASE)
588 #define WWDG ((WWDG_TypeDef *)WWDG_BASE)
589 #define IWDG ((IWDG_TypeDef *)IWDG_BASE)
590 #define SPI2 ((SPI_TypeDef *)SPI2_BASE)
591 #define USART2 ((USART_TypeDef *)USART2_BASE)
592 #define USART3 ((USART_TypeDef *)USART3_BASE)
593 #define I2C1 ((I2C_TypeDef *)I2C1_BASE)
594 #define I2C2 ((I2C_TypeDef *)I2C2_BASE)
595 #define BKP ((BKP_TypeDef *)BKP_BASE)
596 #define PWR ((PWR_TypeDef *)PWR_BASE)
597 #define AFIO ((AFIO_TypeDef *)AFIO_BASE)
598 #define EXTI ((EXTI_TypeDef *)EXTI_BASE)
599 #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
600 #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
601 #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
602 #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
603 #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
604 #define ADC1 ((ADC_TypeDef *)ADC1_BASE)
605 #define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
606 #define SPI1 ((SPI_TypeDef *)SPI1_BASE)
607 #define USART1 ((USART_TypeDef *)USART1_BASE)
608 #define SDIO ((SDIO_TypeDef *)SDIO_BASE)
609 #define DMA1 ((DMA_TypeDef *)DMA1_BASE)
610 #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
611 #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
612 #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
613 #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
614 #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
615 #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
616 #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
617 #define RCC ((RCC_TypeDef *)RCC_BASE)
618 #define CRC ((CRC_TypeDef *)CRC_BASE)
619 #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
620 #define OB ((OB_TypeDef *)OB_BASE)
621 #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
622
623
624 /**
625 * @}
626 */
627
628 /** @addtogroup Exported_constants
629 * @{
630 */
631
632 /** @addtogroup Peripheral_Registers_Bits_Definition
633 * @{
634 */
635
636 /******************************************************************************/
637 /* Peripheral Registers_Bits_Definition */
638 /******************************************************************************/
639
640 /******************************************************************************/
641 /* */
642 /* CRC calculation unit (CRC) */
643 /* */
644 /******************************************************************************/
645
646 /******************* Bit definition for CRC_DR register *********************/
647 #define CRC_DR_DR_Pos (0U)
648 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
649 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
650
651 /******************* Bit definition for CRC_IDR register ********************/
652 #define CRC_IDR_IDR_Pos (0U)
653 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
654 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
655
656 /******************** Bit definition for CRC_CR register ********************/
657 #define CRC_CR_RESET_Pos (0U)
658 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
659 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
660
661 /******************************************************************************/
662 /* */
663 /* Power Control */
664 /* */
665 /******************************************************************************/
666
667 /******************** Bit definition for PWR_CR register ********************/
668 #define PWR_CR_LPDS_Pos (0U)
669 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
670 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
671 #define PWR_CR_PDDS_Pos (1U)
672 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
673 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
674 #define PWR_CR_CWUF_Pos (2U)
675 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
676 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
677 #define PWR_CR_CSBF_Pos (3U)
678 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
679 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
680 #define PWR_CR_PVDE_Pos (4U)
681 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
682 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
683
684 #define PWR_CR_PLS_Pos (5U)
685 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
686 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
687 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
688 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
689 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
690
691 /*!< PVD level configuration */
692 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
693 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
694 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
695 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
696 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
697 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
698 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
699 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
700
701 /* Legacy defines */
702 #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
703 #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
704 #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
705 #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
706 #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
707 #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
708 #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
709 #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
710
711 #define PWR_CR_DBP_Pos (8U)
712 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
713 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
714
715
716 /******************* Bit definition for PWR_CSR register ********************/
717 #define PWR_CSR_WUF_Pos (0U)
718 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
719 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
720 #define PWR_CSR_SBF_Pos (1U)
721 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
722 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
723 #define PWR_CSR_PVDO_Pos (2U)
724 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
725 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
726 #define PWR_CSR_EWUP_Pos (8U)
727 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
728 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
729
730 /******************************************************************************/
731 /* */
732 /* Backup registers */
733 /* */
734 /******************************************************************************/
735
736 /******************* Bit definition for BKP_DR1 register ********************/
737 #define BKP_DR1_D_Pos (0U)
738 #define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
739 #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
740
741 /******************* Bit definition for BKP_DR2 register ********************/
742 #define BKP_DR2_D_Pos (0U)
743 #define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
744 #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
745
746 /******************* Bit definition for BKP_DR3 register ********************/
747 #define BKP_DR3_D_Pos (0U)
748 #define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
749 #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
750
751 /******************* Bit definition for BKP_DR4 register ********************/
752 #define BKP_DR4_D_Pos (0U)
753 #define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
754 #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
755
756 /******************* Bit definition for BKP_DR5 register ********************/
757 #define BKP_DR5_D_Pos (0U)
758 #define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
759 #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
760
761 /******************* Bit definition for BKP_DR6 register ********************/
762 #define BKP_DR6_D_Pos (0U)
763 #define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
764 #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
765
766 /******************* Bit definition for BKP_DR7 register ********************/
767 #define BKP_DR7_D_Pos (0U)
768 #define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
769 #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
770
771 /******************* Bit definition for BKP_DR8 register ********************/
772 #define BKP_DR8_D_Pos (0U)
773 #define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
774 #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
775
776 /******************* Bit definition for BKP_DR9 register ********************/
777 #define BKP_DR9_D_Pos (0U)
778 #define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
779 #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
780
781 /******************* Bit definition for BKP_DR10 register *******************/
782 #define BKP_DR10_D_Pos (0U)
783 #define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
784 #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
785
786 #define RTC_BKP_NUMBER 10
787
788 /****************** Bit definition for BKP_RTCCR register *******************/
789 #define BKP_RTCCR_CAL_Pos (0U)
790 #define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
791 #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
792 #define BKP_RTCCR_CCO_Pos (7U)
793 #define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
794 #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
795 #define BKP_RTCCR_ASOE_Pos (8U)
796 #define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
797 #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
798 #define BKP_RTCCR_ASOS_Pos (9U)
799 #define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
800 #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
801
802 /******************** Bit definition for BKP_CR register ********************/
803 #define BKP_CR_TPE_Pos (0U)
804 #define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
805 #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
806 #define BKP_CR_TPAL_Pos (1U)
807 #define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
808 #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
809
810 /******************* Bit definition for BKP_CSR register ********************/
811 #define BKP_CSR_CTE_Pos (0U)
812 #define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
813 #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
814 #define BKP_CSR_CTI_Pos (1U)
815 #define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
816 #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
817 #define BKP_CSR_TPIE_Pos (2U)
818 #define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
819 #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
820 #define BKP_CSR_TEF_Pos (8U)
821 #define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
822 #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
823 #define BKP_CSR_TIF_Pos (9U)
824 #define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
825 #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
826
827 /******************************************************************************/
828 /* */
829 /* Reset and Clock Control */
830 /* */
831 /******************************************************************************/
832
833 /******************** Bit definition for RCC_CR register ********************/
834 #define RCC_CR_HSION_Pos (0U)
835 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
836 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
837 #define RCC_CR_HSIRDY_Pos (1U)
838 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
839 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
840 #define RCC_CR_HSITRIM_Pos (3U)
841 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
842 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
843 #define RCC_CR_HSICAL_Pos (8U)
844 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
845 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
846 #define RCC_CR_HSEON_Pos (16U)
847 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
848 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
849 #define RCC_CR_HSERDY_Pos (17U)
850 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
851 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
852 #define RCC_CR_HSEBYP_Pos (18U)
853 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
854 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
855 #define RCC_CR_CSSON_Pos (19U)
856 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
857 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
858 #define RCC_CR_PLLON_Pos (24U)
859 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
860 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
861 #define RCC_CR_PLLRDY_Pos (25U)
862 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
863 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
864
865
866 /******************* Bit definition for RCC_CFGR register *******************/
867 /*!< SW configuration */
868 #define RCC_CFGR_SW_Pos (0U)
869 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
870 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
871 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
872 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
873
874 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
875 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
876 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
877
878 /*!< SWS configuration */
879 #define RCC_CFGR_SWS_Pos (2U)
880 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
881 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
882 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
883 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
884
885 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
886 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
887 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
888
889 /*!< HPRE configuration */
890 #define RCC_CFGR_HPRE_Pos (4U)
891 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
892 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
893 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
894 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
895 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
896 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
897
898 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
899 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
900 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
901 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
902 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
903 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
904 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
905 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
906 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
907
908 /*!< PPRE1 configuration */
909 #define RCC_CFGR_PPRE1_Pos (8U)
910 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
911 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
912 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
913 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
914 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
915
916 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
917 #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
918 #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
919 #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
920 #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
921
922 /*!< PPRE2 configuration */
923 #define RCC_CFGR_PPRE2_Pos (11U)
924 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
925 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
926 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
927 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
928 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
929
930 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
931 #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
932 #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
933 #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
934 #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
935
936 /*!< ADCPPRE configuration */
937 #define RCC_CFGR_ADCPRE_Pos (14U)
938 #define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
939 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
940 #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
941 #define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
942
943 #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
944 #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
945 #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
946 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
947
948 #define RCC_CFGR_PLLSRC_Pos (16U)
949 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
950 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
951
952 #define RCC_CFGR_PLLXTPRE_Pos (17U)
953 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
954 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
955
956 /*!< PLLMUL configuration */
957 #define RCC_CFGR_PLLMULL_Pos (18U)
958 #define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
959 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
960 #define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
961 #define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
962 #define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
963 #define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
964
965 #define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
966 #define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
967
968 #define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
969 #define RCC_CFGR_PLLMULL3_Pos (18U)
970 #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
971 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
972 #define RCC_CFGR_PLLMULL4_Pos (19U)
973 #define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
974 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
975 #define RCC_CFGR_PLLMULL5_Pos (18U)
976 #define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
977 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
978 #define RCC_CFGR_PLLMULL6_Pos (20U)
979 #define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
980 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
981 #define RCC_CFGR_PLLMULL7_Pos (18U)
982 #define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
983 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
984 #define RCC_CFGR_PLLMULL8_Pos (19U)
985 #define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
986 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
987 #define RCC_CFGR_PLLMULL9_Pos (18U)
988 #define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
989 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
990 #define RCC_CFGR_PLLMULL10_Pos (21U)
991 #define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
992 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
993 #define RCC_CFGR_PLLMULL11_Pos (18U)
994 #define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
995 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
996 #define RCC_CFGR_PLLMULL12_Pos (19U)
997 #define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
998 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
999 #define RCC_CFGR_PLLMULL13_Pos (18U)
1000 #define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
1001 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
1002 #define RCC_CFGR_PLLMULL14_Pos (20U)
1003 #define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
1004 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
1005 #define RCC_CFGR_PLLMULL15_Pos (18U)
1006 #define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
1007 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
1008 #define RCC_CFGR_PLLMULL16_Pos (19U)
1009 #define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
1010 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
1011
1012 /*!< MCO configuration */
1013 #define RCC_CFGR_MCO_Pos (24U)
1014 #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
1015 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
1016 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
1017 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
1018 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
1019
1020 #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
1021 #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
1022 #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
1023 #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
1024 #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
1025
1026 /* Reference defines */
1027 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
1028 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
1029 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
1030 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
1031 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
1032 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
1033 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
1034 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
1035 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
1036
1037 /*!<****************** Bit definition for RCC_CIR register ********************/
1038 #define RCC_CIR_LSIRDYF_Pos (0U)
1039 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
1040 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
1041 #define RCC_CIR_LSERDYF_Pos (1U)
1042 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
1043 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
1044 #define RCC_CIR_HSIRDYF_Pos (2U)
1045 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
1046 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
1047 #define RCC_CIR_HSERDYF_Pos (3U)
1048 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
1049 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
1050 #define RCC_CIR_PLLRDYF_Pos (4U)
1051 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
1052 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
1053 #define RCC_CIR_CSSF_Pos (7U)
1054 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
1055 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
1056 #define RCC_CIR_LSIRDYIE_Pos (8U)
1057 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
1058 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
1059 #define RCC_CIR_LSERDYIE_Pos (9U)
1060 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
1061 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
1062 #define RCC_CIR_HSIRDYIE_Pos (10U)
1063 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
1064 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
1065 #define RCC_CIR_HSERDYIE_Pos (11U)
1066 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
1067 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
1068 #define RCC_CIR_PLLRDYIE_Pos (12U)
1069 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
1070 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
1071 #define RCC_CIR_LSIRDYC_Pos (16U)
1072 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
1073 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
1074 #define RCC_CIR_LSERDYC_Pos (17U)
1075 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
1076 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
1077 #define RCC_CIR_HSIRDYC_Pos (18U)
1078 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
1079 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
1080 #define RCC_CIR_HSERDYC_Pos (19U)
1081 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
1082 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
1083 #define RCC_CIR_PLLRDYC_Pos (20U)
1084 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
1085 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
1086 #define RCC_CIR_CSSC_Pos (23U)
1087 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
1088 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
1089
1090
1091 /***************** Bit definition for RCC_APB2RSTR register *****************/
1092 #define RCC_APB2RSTR_AFIORST_Pos (0U)
1093 #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
1094 #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
1095 #define RCC_APB2RSTR_IOPARST_Pos (2U)
1096 #define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
1097 #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
1098 #define RCC_APB2RSTR_IOPBRST_Pos (3U)
1099 #define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
1100 #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
1101 #define RCC_APB2RSTR_IOPCRST_Pos (4U)
1102 #define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
1103 #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
1104 #define RCC_APB2RSTR_IOPDRST_Pos (5U)
1105 #define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
1106 #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
1107 #define RCC_APB2RSTR_ADC1RST_Pos (9U)
1108 #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
1109 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
1110
1111
1112 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
1113 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
1114 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
1115 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
1116 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
1117 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
1118 #define RCC_APB2RSTR_USART1RST_Pos (14U)
1119 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
1120 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
1121
1122
1123 #define RCC_APB2RSTR_IOPERST_Pos (6U)
1124 #define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
1125 #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
1126
1127
1128
1129
1130 /***************** Bit definition for RCC_APB1RSTR register *****************/
1131 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
1132 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
1133 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
1134 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
1135 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
1136 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
1137 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
1138 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
1139 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
1140 #define RCC_APB1RSTR_USART2RST_Pos (17U)
1141 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
1142 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
1143 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
1144 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
1145 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
1146
1147
1148 #define RCC_APB1RSTR_BKPRST_Pos (27U)
1149 #define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
1150 #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
1151 #define RCC_APB1RSTR_PWRRST_Pos (28U)
1152 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
1153 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
1154
1155 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
1156 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
1157 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
1158 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
1159 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
1160 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
1161 #define RCC_APB1RSTR_USART3RST_Pos (18U)
1162 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
1163 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
1164 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
1165 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
1166 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
1167
1168
1169
1170
1171
1172
1173
1174 /****************** Bit definition for RCC_AHBENR register ******************/
1175 #define RCC_AHBENR_DMA1EN_Pos (0U)
1176 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
1177 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
1178 #define RCC_AHBENR_SRAMEN_Pos (2U)
1179 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
1180 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
1181 #define RCC_AHBENR_FLITFEN_Pos (4U)
1182 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
1183 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
1184 #define RCC_AHBENR_CRCEN_Pos (6U)
1185 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
1186 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
1187
1188
1189
1190
1191 /****************** Bit definition for RCC_APB2ENR register *****************/
1192 #define RCC_APB2ENR_AFIOEN_Pos (0U)
1193 #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
1194 #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
1195 #define RCC_APB2ENR_IOPAEN_Pos (2U)
1196 #define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
1197 #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
1198 #define RCC_APB2ENR_IOPBEN_Pos (3U)
1199 #define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
1200 #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
1201 #define RCC_APB2ENR_IOPCEN_Pos (4U)
1202 #define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
1203 #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
1204 #define RCC_APB2ENR_IOPDEN_Pos (5U)
1205 #define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
1206 #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
1207 #define RCC_APB2ENR_ADC1EN_Pos (9U)
1208 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
1209 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
1210
1211
1212 #define RCC_APB2ENR_TIM1EN_Pos (11U)
1213 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
1214 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
1215 #define RCC_APB2ENR_SPI1EN_Pos (12U)
1216 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
1217 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
1218 #define RCC_APB2ENR_USART1EN_Pos (14U)
1219 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
1220 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
1221
1222
1223 #define RCC_APB2ENR_IOPEEN_Pos (6U)
1224 #define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
1225 #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
1226
1227
1228
1229
1230 /***************** Bit definition for RCC_APB1ENR register ******************/
1231 #define RCC_APB1ENR_TIM2EN_Pos (0U)
1232 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
1233 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
1234 #define RCC_APB1ENR_TIM3EN_Pos (1U)
1235 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
1236 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
1237 #define RCC_APB1ENR_WWDGEN_Pos (11U)
1238 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
1239 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
1240 #define RCC_APB1ENR_USART2EN_Pos (17U)
1241 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
1242 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
1243 #define RCC_APB1ENR_I2C1EN_Pos (21U)
1244 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
1245 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
1246
1247
1248 #define RCC_APB1ENR_BKPEN_Pos (27U)
1249 #define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
1250 #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
1251 #define RCC_APB1ENR_PWREN_Pos (28U)
1252 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
1253 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
1254
1255 #define RCC_APB1ENR_TIM4EN_Pos (2U)
1256 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
1257 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
1258 #define RCC_APB1ENR_SPI2EN_Pos (14U)
1259 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
1260 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
1261 #define RCC_APB1ENR_USART3EN_Pos (18U)
1262 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
1263 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
1264 #define RCC_APB1ENR_I2C2EN_Pos (22U)
1265 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
1266 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
1267
1268
1269
1270
1271
1272
1273
1274 /******************* Bit definition for RCC_BDCR register *******************/
1275 #define RCC_BDCR_LSEON_Pos (0U)
1276 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
1277 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
1278 #define RCC_BDCR_LSERDY_Pos (1U)
1279 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
1280 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
1281 #define RCC_BDCR_LSEBYP_Pos (2U)
1282 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
1283 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
1284
1285 #define RCC_BDCR_RTCSEL_Pos (8U)
1286 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
1287 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
1288 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
1289 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
1290
1291 /*!< RTC congiguration */
1292 #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
1293 #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
1294 #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
1295 #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
1296
1297 #define RCC_BDCR_RTCEN_Pos (15U)
1298 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
1299 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
1300 #define RCC_BDCR_BDRST_Pos (16U)
1301 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
1302 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
1303
1304 /******************* Bit definition for RCC_CSR register ********************/
1305 #define RCC_CSR_LSION_Pos (0U)
1306 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
1307 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
1308 #define RCC_CSR_LSIRDY_Pos (1U)
1309 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
1310 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
1311 #define RCC_CSR_RMVF_Pos (24U)
1312 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
1313 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
1314 #define RCC_CSR_PINRSTF_Pos (26U)
1315 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
1316 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
1317 #define RCC_CSR_PORRSTF_Pos (27U)
1318 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
1319 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
1320 #define RCC_CSR_SFTRSTF_Pos (28U)
1321 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
1322 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
1323 #define RCC_CSR_IWDGRSTF_Pos (29U)
1324 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
1325 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
1326 #define RCC_CSR_WWDGRSTF_Pos (30U)
1327 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
1328 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
1329 #define RCC_CSR_LPWRRSTF_Pos (31U)
1330 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
1331 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
1332
1333
1334
1335 /******************************************************************************/
1336 /* */
1337 /* General Purpose and Alternate Function I/O */
1338 /* */
1339 /******************************************************************************/
1340
1341 /******************* Bit definition for GPIO_CRL register *******************/
1342 #define GPIO_CRL_MODE_Pos (0U)
1343 #define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
1344 #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
1345
1346 #define GPIO_CRL_MODE0_Pos (0U)
1347 #define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
1348 #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
1349 #define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
1350 #define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
1351
1352 #define GPIO_CRL_MODE1_Pos (4U)
1353 #define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
1354 #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
1355 #define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
1356 #define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
1357
1358 #define GPIO_CRL_MODE2_Pos (8U)
1359 #define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
1360 #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
1361 #define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
1362 #define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
1363
1364 #define GPIO_CRL_MODE3_Pos (12U)
1365 #define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
1366 #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
1367 #define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
1368 #define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
1369
1370 #define GPIO_CRL_MODE4_Pos (16U)
1371 #define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
1372 #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
1373 #define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
1374 #define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
1375
1376 #define GPIO_CRL_MODE5_Pos (20U)
1377 #define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
1378 #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
1379 #define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
1380 #define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
1381
1382 #define GPIO_CRL_MODE6_Pos (24U)
1383 #define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
1384 #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
1385 #define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
1386 #define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
1387
1388 #define GPIO_CRL_MODE7_Pos (28U)
1389 #define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
1390 #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
1391 #define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
1392 #define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
1393
1394 #define GPIO_CRL_CNF_Pos (2U)
1395 #define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
1396 #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
1397
1398 #define GPIO_CRL_CNF0_Pos (2U)
1399 #define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
1400 #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
1401 #define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
1402 #define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
1403
1404 #define GPIO_CRL_CNF1_Pos (6U)
1405 #define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
1406 #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
1407 #define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
1408 #define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
1409
1410 #define GPIO_CRL_CNF2_Pos (10U)
1411 #define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
1412 #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
1413 #define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
1414 #define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
1415
1416 #define GPIO_CRL_CNF3_Pos (14U)
1417 #define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
1418 #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
1419 #define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
1420 #define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
1421
1422 #define GPIO_CRL_CNF4_Pos (18U)
1423 #define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
1424 #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
1425 #define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
1426 #define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
1427
1428 #define GPIO_CRL_CNF5_Pos (22U)
1429 #define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
1430 #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
1431 #define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
1432 #define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
1433
1434 #define GPIO_CRL_CNF6_Pos (26U)
1435 #define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
1436 #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
1437 #define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
1438 #define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
1439
1440 #define GPIO_CRL_CNF7_Pos (30U)
1441 #define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
1442 #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
1443 #define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
1444 #define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
1445
1446 /******************* Bit definition for GPIO_CRH register *******************/
1447 #define GPIO_CRH_MODE_Pos (0U)
1448 #define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
1449 #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
1450
1451 #define GPIO_CRH_MODE8_Pos (0U)
1452 #define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
1453 #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
1454 #define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
1455 #define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
1456
1457 #define GPIO_CRH_MODE9_Pos (4U)
1458 #define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
1459 #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
1460 #define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
1461 #define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
1462
1463 #define GPIO_CRH_MODE10_Pos (8U)
1464 #define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
1465 #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
1466 #define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
1467 #define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
1468
1469 #define GPIO_CRH_MODE11_Pos (12U)
1470 #define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
1471 #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
1472 #define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
1473 #define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
1474
1475 #define GPIO_CRH_MODE12_Pos (16U)
1476 #define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
1477 #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
1478 #define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
1479 #define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
1480
1481 #define GPIO_CRH_MODE13_Pos (20U)
1482 #define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
1483 #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
1484 #define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
1485 #define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
1486
1487 #define GPIO_CRH_MODE14_Pos (24U)
1488 #define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
1489 #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
1490 #define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
1491 #define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
1492
1493 #define GPIO_CRH_MODE15_Pos (28U)
1494 #define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
1495 #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
1496 #define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
1497 #define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
1498
1499 #define GPIO_CRH_CNF_Pos (2U)
1500 #define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
1501 #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
1502
1503 #define GPIO_CRH_CNF8_Pos (2U)
1504 #define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
1505 #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
1506 #define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
1507 #define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
1508
1509 #define GPIO_CRH_CNF9_Pos (6U)
1510 #define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
1511 #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
1512 #define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
1513 #define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
1514
1515 #define GPIO_CRH_CNF10_Pos (10U)
1516 #define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
1517 #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
1518 #define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
1519 #define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
1520
1521 #define GPIO_CRH_CNF11_Pos (14U)
1522 #define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
1523 #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
1524 #define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
1525 #define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
1526
1527 #define GPIO_CRH_CNF12_Pos (18U)
1528 #define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
1529 #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
1530 #define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
1531 #define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
1532
1533 #define GPIO_CRH_CNF13_Pos (22U)
1534 #define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
1535 #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
1536 #define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
1537 #define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
1538
1539 #define GPIO_CRH_CNF14_Pos (26U)
1540 #define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
1541 #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
1542 #define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
1543 #define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
1544
1545 #define GPIO_CRH_CNF15_Pos (30U)
1546 #define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
1547 #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
1548 #define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
1549 #define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
1550
1551 /*!<****************** Bit definition for GPIO_IDR register *******************/
1552 #define GPIO_IDR_IDR0_Pos (0U)
1553 #define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
1554 #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
1555 #define GPIO_IDR_IDR1_Pos (1U)
1556 #define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
1557 #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
1558 #define GPIO_IDR_IDR2_Pos (2U)
1559 #define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
1560 #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
1561 #define GPIO_IDR_IDR3_Pos (3U)
1562 #define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
1563 #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
1564 #define GPIO_IDR_IDR4_Pos (4U)
1565 #define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
1566 #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
1567 #define GPIO_IDR_IDR5_Pos (5U)
1568 #define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
1569 #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
1570 #define GPIO_IDR_IDR6_Pos (6U)
1571 #define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
1572 #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
1573 #define GPIO_IDR_IDR7_Pos (7U)
1574 #define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
1575 #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
1576 #define GPIO_IDR_IDR8_Pos (8U)
1577 #define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
1578 #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
1579 #define GPIO_IDR_IDR9_Pos (9U)
1580 #define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
1581 #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
1582 #define GPIO_IDR_IDR10_Pos (10U)
1583 #define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
1584 #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
1585 #define GPIO_IDR_IDR11_Pos (11U)
1586 #define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
1587 #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
1588 #define GPIO_IDR_IDR12_Pos (12U)
1589 #define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
1590 #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
1591 #define GPIO_IDR_IDR13_Pos (13U)
1592 #define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
1593 #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
1594 #define GPIO_IDR_IDR14_Pos (14U)
1595 #define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
1596 #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
1597 #define GPIO_IDR_IDR15_Pos (15U)
1598 #define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
1599 #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
1600
1601 /******************* Bit definition for GPIO_ODR register *******************/
1602 #define GPIO_ODR_ODR0_Pos (0U)
1603 #define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
1604 #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
1605 #define GPIO_ODR_ODR1_Pos (1U)
1606 #define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
1607 #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
1608 #define GPIO_ODR_ODR2_Pos (2U)
1609 #define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
1610 #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
1611 #define GPIO_ODR_ODR3_Pos (3U)
1612 #define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
1613 #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
1614 #define GPIO_ODR_ODR4_Pos (4U)
1615 #define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
1616 #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
1617 #define GPIO_ODR_ODR5_Pos (5U)
1618 #define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
1619 #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
1620 #define GPIO_ODR_ODR6_Pos (6U)
1621 #define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
1622 #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
1623 #define GPIO_ODR_ODR7_Pos (7U)
1624 #define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
1625 #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
1626 #define GPIO_ODR_ODR8_Pos (8U)
1627 #define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
1628 #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
1629 #define GPIO_ODR_ODR9_Pos (9U)
1630 #define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
1631 #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
1632 #define GPIO_ODR_ODR10_Pos (10U)
1633 #define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
1634 #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
1635 #define GPIO_ODR_ODR11_Pos (11U)
1636 #define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
1637 #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
1638 #define GPIO_ODR_ODR12_Pos (12U)
1639 #define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
1640 #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
1641 #define GPIO_ODR_ODR13_Pos (13U)
1642 #define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
1643 #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
1644 #define GPIO_ODR_ODR14_Pos (14U)
1645 #define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
1646 #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
1647 #define GPIO_ODR_ODR15_Pos (15U)
1648 #define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
1649 #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
1650
1651 /****************** Bit definition for GPIO_BSRR register *******************/
1652 #define GPIO_BSRR_BS0_Pos (0U)
1653 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
1654 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
1655 #define GPIO_BSRR_BS1_Pos (1U)
1656 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
1657 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
1658 #define GPIO_BSRR_BS2_Pos (2U)
1659 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
1660 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
1661 #define GPIO_BSRR_BS3_Pos (3U)
1662 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
1663 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
1664 #define GPIO_BSRR_BS4_Pos (4U)
1665 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
1666 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
1667 #define GPIO_BSRR_BS5_Pos (5U)
1668 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
1669 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
1670 #define GPIO_BSRR_BS6_Pos (6U)
1671 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
1672 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
1673 #define GPIO_BSRR_BS7_Pos (7U)
1674 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
1675 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
1676 #define GPIO_BSRR_BS8_Pos (8U)
1677 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
1678 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
1679 #define GPIO_BSRR_BS9_Pos (9U)
1680 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
1681 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
1682 #define GPIO_BSRR_BS10_Pos (10U)
1683 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
1684 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
1685 #define GPIO_BSRR_BS11_Pos (11U)
1686 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
1687 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
1688 #define GPIO_BSRR_BS12_Pos (12U)
1689 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
1690 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
1691 #define GPIO_BSRR_BS13_Pos (13U)
1692 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
1693 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
1694 #define GPIO_BSRR_BS14_Pos (14U)
1695 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
1696 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
1697 #define GPIO_BSRR_BS15_Pos (15U)
1698 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
1699 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
1700
1701 #define GPIO_BSRR_BR0_Pos (16U)
1702 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
1703 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
1704 #define GPIO_BSRR_BR1_Pos (17U)
1705 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
1706 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
1707 #define GPIO_BSRR_BR2_Pos (18U)
1708 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
1709 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
1710 #define GPIO_BSRR_BR3_Pos (19U)
1711 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
1712 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
1713 #define GPIO_BSRR_BR4_Pos (20U)
1714 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
1715 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
1716 #define GPIO_BSRR_BR5_Pos (21U)
1717 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
1718 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
1719 #define GPIO_BSRR_BR6_Pos (22U)
1720 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
1721 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
1722 #define GPIO_BSRR_BR7_Pos (23U)
1723 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
1724 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
1725 #define GPIO_BSRR_BR8_Pos (24U)
1726 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
1727 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
1728 #define GPIO_BSRR_BR9_Pos (25U)
1729 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
1730 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
1731 #define GPIO_BSRR_BR10_Pos (26U)
1732 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
1733 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
1734 #define GPIO_BSRR_BR11_Pos (27U)
1735 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
1736 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
1737 #define GPIO_BSRR_BR12_Pos (28U)
1738 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
1739 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
1740 #define GPIO_BSRR_BR13_Pos (29U)
1741 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
1742 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
1743 #define GPIO_BSRR_BR14_Pos (30U)
1744 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
1745 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
1746 #define GPIO_BSRR_BR15_Pos (31U)
1747 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
1748 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
1749
1750 /******************* Bit definition for GPIO_BRR register *******************/
1751 #define GPIO_BRR_BR0_Pos (0U)
1752 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
1753 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
1754 #define GPIO_BRR_BR1_Pos (1U)
1755 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
1756 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
1757 #define GPIO_BRR_BR2_Pos (2U)
1758 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
1759 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
1760 #define GPIO_BRR_BR3_Pos (3U)
1761 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
1762 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
1763 #define GPIO_BRR_BR4_Pos (4U)
1764 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
1765 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
1766 #define GPIO_BRR_BR5_Pos (5U)
1767 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
1768 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
1769 #define GPIO_BRR_BR6_Pos (6U)
1770 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
1771 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
1772 #define GPIO_BRR_BR7_Pos (7U)
1773 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
1774 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
1775 #define GPIO_BRR_BR8_Pos (8U)
1776 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
1777 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
1778 #define GPIO_BRR_BR9_Pos (9U)
1779 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
1780 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
1781 #define GPIO_BRR_BR10_Pos (10U)
1782 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
1783 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
1784 #define GPIO_BRR_BR11_Pos (11U)
1785 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
1786 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
1787 #define GPIO_BRR_BR12_Pos (12U)
1788 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
1789 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
1790 #define GPIO_BRR_BR13_Pos (13U)
1791 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
1792 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
1793 #define GPIO_BRR_BR14_Pos (14U)
1794 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
1795 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
1796 #define GPIO_BRR_BR15_Pos (15U)
1797 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
1798 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
1799
1800 /****************** Bit definition for GPIO_LCKR register *******************/
1801 #define GPIO_LCKR_LCK0_Pos (0U)
1802 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
1803 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
1804 #define GPIO_LCKR_LCK1_Pos (1U)
1805 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
1806 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
1807 #define GPIO_LCKR_LCK2_Pos (2U)
1808 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
1809 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
1810 #define GPIO_LCKR_LCK3_Pos (3U)
1811 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
1812 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
1813 #define GPIO_LCKR_LCK4_Pos (4U)
1814 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
1815 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
1816 #define GPIO_LCKR_LCK5_Pos (5U)
1817 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
1818 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
1819 #define GPIO_LCKR_LCK6_Pos (6U)
1820 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
1821 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
1822 #define GPIO_LCKR_LCK7_Pos (7U)
1823 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
1824 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
1825 #define GPIO_LCKR_LCK8_Pos (8U)
1826 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
1827 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
1828 #define GPIO_LCKR_LCK9_Pos (9U)
1829 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
1830 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
1831 #define GPIO_LCKR_LCK10_Pos (10U)
1832 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
1833 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
1834 #define GPIO_LCKR_LCK11_Pos (11U)
1835 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
1836 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
1837 #define GPIO_LCKR_LCK12_Pos (12U)
1838 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
1839 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
1840 #define GPIO_LCKR_LCK13_Pos (13U)
1841 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
1842 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
1843 #define GPIO_LCKR_LCK14_Pos (14U)
1844 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
1845 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
1846 #define GPIO_LCKR_LCK15_Pos (15U)
1847 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
1848 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
1849 #define GPIO_LCKR_LCKK_Pos (16U)
1850 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
1851 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
1852
1853 /*----------------------------------------------------------------------------*/
1854
1855 /****************** Bit definition for AFIO_EVCR register *******************/
1856 #define AFIO_EVCR_PIN_Pos (0U)
1857 #define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
1858 #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
1859 #define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
1860 #define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
1861 #define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
1862 #define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
1863
1864 /*!< PIN configuration */
1865 #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
1866 #define AFIO_EVCR_PIN_PX1_Pos (0U)
1867 #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
1868 #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
1869 #define AFIO_EVCR_PIN_PX2_Pos (1U)
1870 #define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
1871 #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
1872 #define AFIO_EVCR_PIN_PX3_Pos (0U)
1873 #define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
1874 #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
1875 #define AFIO_EVCR_PIN_PX4_Pos (2U)
1876 #define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
1877 #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
1878 #define AFIO_EVCR_PIN_PX5_Pos (0U)
1879 #define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
1880 #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
1881 #define AFIO_EVCR_PIN_PX6_Pos (1U)
1882 #define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
1883 #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
1884 #define AFIO_EVCR_PIN_PX7_Pos (0U)
1885 #define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
1886 #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
1887 #define AFIO_EVCR_PIN_PX8_Pos (3U)
1888 #define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
1889 #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
1890 #define AFIO_EVCR_PIN_PX9_Pos (0U)
1891 #define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
1892 #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
1893 #define AFIO_EVCR_PIN_PX10_Pos (1U)
1894 #define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
1895 #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
1896 #define AFIO_EVCR_PIN_PX11_Pos (0U)
1897 #define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
1898 #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
1899 #define AFIO_EVCR_PIN_PX12_Pos (2U)
1900 #define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
1901 #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
1902 #define AFIO_EVCR_PIN_PX13_Pos (0U)
1903 #define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
1904 #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
1905 #define AFIO_EVCR_PIN_PX14_Pos (1U)
1906 #define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
1907 #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
1908 #define AFIO_EVCR_PIN_PX15_Pos (0U)
1909 #define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
1910 #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
1911
1912 #define AFIO_EVCR_PORT_Pos (4U)
1913 #define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
1914 #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
1915 #define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
1916 #define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
1917 #define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
1918
1919 /*!< PORT configuration */
1920 #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
1921 #define AFIO_EVCR_PORT_PB_Pos (4U)
1922 #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
1923 #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
1924 #define AFIO_EVCR_PORT_PC_Pos (5U)
1925 #define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
1926 #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
1927 #define AFIO_EVCR_PORT_PD_Pos (4U)
1928 #define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
1929 #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
1930 #define AFIO_EVCR_PORT_PE_Pos (6U)
1931 #define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
1932 #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
1933
1934 #define AFIO_EVCR_EVOE_Pos (7U)
1935 #define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
1936 #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
1937
1938 /****************** Bit definition for AFIO_MAPR register *******************/
1939 #define AFIO_MAPR_SPI1_REMAP_Pos (0U)
1940 #define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
1941 #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
1942 #define AFIO_MAPR_I2C1_REMAP_Pos (1U)
1943 #define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
1944 #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
1945 #define AFIO_MAPR_USART1_REMAP_Pos (2U)
1946 #define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
1947 #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
1948 #define AFIO_MAPR_USART2_REMAP_Pos (3U)
1949 #define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
1950 #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
1951
1952 #define AFIO_MAPR_USART3_REMAP_Pos (4U)
1953 #define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
1954 #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
1955 #define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
1956 #define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
1957
1958 /* USART3_REMAP configuration */
1959 #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
1960 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
1961 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
1962 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
1963 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
1964 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
1965 #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
1966
1967 #define AFIO_MAPR_TIM1_REMAP_Pos (6U)
1968 #define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
1969 #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
1970 #define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
1971 #define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
1972
1973 /*!< TIM1_REMAP configuration */
1974 #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
1975 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
1976 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
1977 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
1978 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
1979 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
1980 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
1981
1982 #define AFIO_MAPR_TIM2_REMAP_Pos (8U)
1983 #define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
1984 #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
1985 #define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
1986 #define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
1987
1988 /*!< TIM2_REMAP configuration */
1989 #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
1990 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
1991 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
1992 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
1993 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
1994 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
1995 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
1996 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
1997 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
1998 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
1999
2000 #define AFIO_MAPR_TIM3_REMAP_Pos (10U)
2001 #define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
2002 #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
2003 #define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
2004 #define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
2005
2006 /*!< TIM3_REMAP configuration */
2007 #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
2008 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
2009 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
2010 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
2011 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
2012 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
2013 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
2014
2015 #define AFIO_MAPR_TIM4_REMAP_Pos (12U)
2016 #define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
2017 #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
2018
2019
2020 #define AFIO_MAPR_PD01_REMAP_Pos (15U)
2021 #define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
2022 #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
2023
2024 /*!< SWJ_CFG configuration */
2025 #define AFIO_MAPR_SWJ_CFG_Pos (24U)
2026 #define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
2027 #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
2028 #define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
2029 #define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
2030 #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
2031
2032 #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
2033 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
2034 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
2035 #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
2036 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
2037 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
2038 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
2039 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
2040 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
2041 #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
2042
2043
2044 /***************** Bit definition for AFIO_EXTICR1 register *****************/
2045 #define AFIO_EXTICR1_EXTI0_Pos (0U)
2046 #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
2047 #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
2048 #define AFIO_EXTICR1_EXTI1_Pos (4U)
2049 #define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
2050 #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
2051 #define AFIO_EXTICR1_EXTI2_Pos (8U)
2052 #define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
2053 #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
2054 #define AFIO_EXTICR1_EXTI3_Pos (12U)
2055 #define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
2056 #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
2057
2058 /*!< EXTI0 configuration */
2059 #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
2060 #define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
2061 #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
2062 #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
2063 #define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
2064 #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
2065 #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
2066 #define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
2067 #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
2068 #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
2069 #define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
2070 #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
2071 #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
2072 #define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
2073 #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
2074 #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
2075 #define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
2076 #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
2077 #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
2078
2079 /*!< EXTI1 configuration */
2080 #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
2081 #define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
2082 #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
2083 #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
2084 #define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
2085 #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
2086 #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
2087 #define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
2088 #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
2089 #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
2090 #define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
2091 #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
2092 #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
2093 #define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
2094 #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
2095 #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
2096 #define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
2097 #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
2098 #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
2099
2100 /*!< EXTI2 configuration */
2101 #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
2102 #define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
2103 #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
2104 #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
2105 #define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
2106 #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
2107 #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
2108 #define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
2109 #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
2110 #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
2111 #define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
2112 #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
2113 #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
2114 #define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
2115 #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
2116 #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
2117 #define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
2118 #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
2119 #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
2120
2121 /*!< EXTI3 configuration */
2122 #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
2123 #define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
2124 #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
2125 #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
2126 #define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
2127 #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
2128 #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
2129 #define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
2130 #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
2131 #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
2132 #define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
2133 #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
2134 #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
2135 #define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
2136 #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
2137 #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
2138 #define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
2139 #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
2140 #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
2141
2142 /***************** Bit definition for AFIO_EXTICR2 register *****************/
2143 #define AFIO_EXTICR2_EXTI4_Pos (0U)
2144 #define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
2145 #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
2146 #define AFIO_EXTICR2_EXTI5_Pos (4U)
2147 #define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
2148 #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
2149 #define AFIO_EXTICR2_EXTI6_Pos (8U)
2150 #define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
2151 #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
2152 #define AFIO_EXTICR2_EXTI7_Pos (12U)
2153 #define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
2154 #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
2155
2156 /*!< EXTI4 configuration */
2157 #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
2158 #define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
2159 #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
2160 #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
2161 #define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
2162 #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
2163 #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
2164 #define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
2165 #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
2166 #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
2167 #define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
2168 #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
2169 #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
2170 #define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
2171 #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
2172 #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
2173 #define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
2174 #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
2175 #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
2176
2177 /* EXTI5 configuration */
2178 #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
2179 #define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
2180 #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
2181 #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
2182 #define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
2183 #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
2184 #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
2185 #define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
2186 #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
2187 #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
2188 #define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
2189 #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
2190 #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
2191 #define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
2192 #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
2193 #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
2194 #define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
2195 #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
2196 #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
2197
2198 /*!< EXTI6 configuration */
2199 #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
2200 #define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
2201 #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
2202 #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
2203 #define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
2204 #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
2205 #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
2206 #define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
2207 #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
2208 #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
2209 #define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
2210 #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
2211 #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
2212 #define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
2213 #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
2214 #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
2215 #define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
2216 #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
2217 #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
2218
2219 /*!< EXTI7 configuration */
2220 #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
2221 #define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
2222 #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
2223 #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
2224 #define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
2225 #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
2226 #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
2227 #define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
2228 #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
2229 #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
2230 #define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
2231 #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
2232 #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
2233 #define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
2234 #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
2235 #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
2236 #define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
2237 #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
2238 #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
2239
2240 /***************** Bit definition for AFIO_EXTICR3 register *****************/
2241 #define AFIO_EXTICR3_EXTI8_Pos (0U)
2242 #define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
2243 #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
2244 #define AFIO_EXTICR3_EXTI9_Pos (4U)
2245 #define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
2246 #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
2247 #define AFIO_EXTICR3_EXTI10_Pos (8U)
2248 #define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
2249 #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
2250 #define AFIO_EXTICR3_EXTI11_Pos (12U)
2251 #define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
2252 #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
2253
2254 /*!< EXTI8 configuration */
2255 #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
2256 #define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
2257 #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
2258 #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
2259 #define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
2260 #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
2261 #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
2262 #define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
2263 #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
2264 #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
2265 #define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
2266 #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
2267 #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
2268 #define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
2269 #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
2270 #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
2271 #define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
2272 #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
2273 #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
2274
2275 /*!< EXTI9 configuration */
2276 #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
2277 #define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
2278 #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
2279 #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
2280 #define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
2281 #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
2282 #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
2283 #define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
2284 #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
2285 #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
2286 #define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
2287 #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
2288 #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
2289 #define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
2290 #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
2291 #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
2292 #define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
2293 #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
2294 #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
2295
2296 /*!< EXTI10 configuration */
2297 #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
2298 #define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
2299 #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
2300 #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
2301 #define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
2302 #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
2303 #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
2304 #define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
2305 #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
2306 #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
2307 #define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
2308 #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
2309 #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
2310 #define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
2311 #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
2312 #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
2313 #define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
2314 #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
2315 #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
2316
2317 /*!< EXTI11 configuration */
2318 #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
2319 #define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
2320 #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
2321 #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
2322 #define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
2323 #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
2324 #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
2325 #define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
2326 #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
2327 #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
2328 #define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
2329 #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
2330 #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
2331 #define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
2332 #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
2333 #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
2334 #define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
2335 #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
2336 #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
2337
2338 /***************** Bit definition for AFIO_EXTICR4 register *****************/
2339 #define AFIO_EXTICR4_EXTI12_Pos (0U)
2340 #define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
2341 #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
2342 #define AFIO_EXTICR4_EXTI13_Pos (4U)
2343 #define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
2344 #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
2345 #define AFIO_EXTICR4_EXTI14_Pos (8U)
2346 #define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
2347 #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
2348 #define AFIO_EXTICR4_EXTI15_Pos (12U)
2349 #define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
2350 #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
2351
2352 /* EXTI12 configuration */
2353 #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
2354 #define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
2355 #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
2356 #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
2357 #define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
2358 #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
2359 #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
2360 #define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
2361 #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
2362 #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
2363 #define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
2364 #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
2365 #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
2366 #define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
2367 #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
2368 #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
2369 #define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
2370 #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
2371 #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
2372
2373 /* EXTI13 configuration */
2374 #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
2375 #define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
2376 #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
2377 #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
2378 #define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
2379 #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
2380 #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
2381 #define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
2382 #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
2383 #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
2384 #define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
2385 #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
2386 #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
2387 #define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
2388 #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
2389 #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
2390 #define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
2391 #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
2392 #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
2393
2394 /*!< EXTI14 configuration */
2395 #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
2396 #define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
2397 #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
2398 #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
2399 #define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
2400 #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
2401 #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
2402 #define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
2403 #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
2404 #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
2405 #define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
2406 #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
2407 #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
2408 #define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
2409 #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
2410 #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
2411 #define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
2412 #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
2413 #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
2414
2415 /*!< EXTI15 configuration */
2416 #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
2417 #define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
2418 #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
2419 #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
2420 #define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
2421 #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
2422 #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
2423 #define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
2424 #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
2425 #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
2426 #define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
2427 #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
2428 #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
2429 #define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
2430 #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
2431 #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
2432 #define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
2433 #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
2434 #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
2435
2436 /****************** Bit definition for AFIO_MAPR2 register ******************/
2437
2438
2439
2440 /******************************************************************************/
2441 /* */
2442 /* External Interrupt/Event Controller */
2443 /* */
2444 /******************************************************************************/
2445
2446 /******************* Bit definition for EXTI_IMR register *******************/
2447 #define EXTI_IMR_MR0_Pos (0U)
2448 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
2449 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
2450 #define EXTI_IMR_MR1_Pos (1U)
2451 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
2452 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
2453 #define EXTI_IMR_MR2_Pos (2U)
2454 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
2455 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
2456 #define EXTI_IMR_MR3_Pos (3U)
2457 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
2458 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
2459 #define EXTI_IMR_MR4_Pos (4U)
2460 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
2461 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
2462 #define EXTI_IMR_MR5_Pos (5U)
2463 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
2464 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
2465 #define EXTI_IMR_MR6_Pos (6U)
2466 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
2467 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
2468 #define EXTI_IMR_MR7_Pos (7U)
2469 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
2470 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
2471 #define EXTI_IMR_MR8_Pos (8U)
2472 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
2473 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
2474 #define EXTI_IMR_MR9_Pos (9U)
2475 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
2476 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
2477 #define EXTI_IMR_MR10_Pos (10U)
2478 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
2479 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
2480 #define EXTI_IMR_MR11_Pos (11U)
2481 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
2482 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
2483 #define EXTI_IMR_MR12_Pos (12U)
2484 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
2485 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
2486 #define EXTI_IMR_MR13_Pos (13U)
2487 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
2488 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
2489 #define EXTI_IMR_MR14_Pos (14U)
2490 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
2491 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
2492 #define EXTI_IMR_MR15_Pos (15U)
2493 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
2494 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
2495 #define EXTI_IMR_MR16_Pos (16U)
2496 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
2497 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
2498 #define EXTI_IMR_MR17_Pos (17U)
2499 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
2500 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
2501 #define EXTI_IMR_MR18_Pos (18U)
2502 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
2503 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
2504
2505 /* References Defines */
2506 #define EXTI_IMR_IM0 EXTI_IMR_MR0
2507 #define EXTI_IMR_IM1 EXTI_IMR_MR1
2508 #define EXTI_IMR_IM2 EXTI_IMR_MR2
2509 #define EXTI_IMR_IM3 EXTI_IMR_MR3
2510 #define EXTI_IMR_IM4 EXTI_IMR_MR4
2511 #define EXTI_IMR_IM5 EXTI_IMR_MR5
2512 #define EXTI_IMR_IM6 EXTI_IMR_MR6
2513 #define EXTI_IMR_IM7 EXTI_IMR_MR7
2514 #define EXTI_IMR_IM8 EXTI_IMR_MR8
2515 #define EXTI_IMR_IM9 EXTI_IMR_MR9
2516 #define EXTI_IMR_IM10 EXTI_IMR_MR10
2517 #define EXTI_IMR_IM11 EXTI_IMR_MR11
2518 #define EXTI_IMR_IM12 EXTI_IMR_MR12
2519 #define EXTI_IMR_IM13 EXTI_IMR_MR13
2520 #define EXTI_IMR_IM14 EXTI_IMR_MR14
2521 #define EXTI_IMR_IM15 EXTI_IMR_MR15
2522 #define EXTI_IMR_IM16 EXTI_IMR_MR16
2523 #define EXTI_IMR_IM17 EXTI_IMR_MR17
2524 #define EXTI_IMR_IM18 EXTI_IMR_MR18
2525 #define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
2526
2527 /******************* Bit definition for EXTI_EMR register *******************/
2528 #define EXTI_EMR_MR0_Pos (0U)
2529 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
2530 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
2531 #define EXTI_EMR_MR1_Pos (1U)
2532 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
2533 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
2534 #define EXTI_EMR_MR2_Pos (2U)
2535 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
2536 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
2537 #define EXTI_EMR_MR3_Pos (3U)
2538 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
2539 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
2540 #define EXTI_EMR_MR4_Pos (4U)
2541 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
2542 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
2543 #define EXTI_EMR_MR5_Pos (5U)
2544 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
2545 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
2546 #define EXTI_EMR_MR6_Pos (6U)
2547 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
2548 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
2549 #define EXTI_EMR_MR7_Pos (7U)
2550 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
2551 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
2552 #define EXTI_EMR_MR8_Pos (8U)
2553 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
2554 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
2555 #define EXTI_EMR_MR9_Pos (9U)
2556 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
2557 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
2558 #define EXTI_EMR_MR10_Pos (10U)
2559 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
2560 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
2561 #define EXTI_EMR_MR11_Pos (11U)
2562 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
2563 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
2564 #define EXTI_EMR_MR12_Pos (12U)
2565 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
2566 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
2567 #define EXTI_EMR_MR13_Pos (13U)
2568 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
2569 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
2570 #define EXTI_EMR_MR14_Pos (14U)
2571 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
2572 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
2573 #define EXTI_EMR_MR15_Pos (15U)
2574 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
2575 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
2576 #define EXTI_EMR_MR16_Pos (16U)
2577 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
2578 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
2579 #define EXTI_EMR_MR17_Pos (17U)
2580 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
2581 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
2582 #define EXTI_EMR_MR18_Pos (18U)
2583 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
2584 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
2585
2586 /* References Defines */
2587 #define EXTI_EMR_EM0 EXTI_EMR_MR0
2588 #define EXTI_EMR_EM1 EXTI_EMR_MR1
2589 #define EXTI_EMR_EM2 EXTI_EMR_MR2
2590 #define EXTI_EMR_EM3 EXTI_EMR_MR3
2591 #define EXTI_EMR_EM4 EXTI_EMR_MR4
2592 #define EXTI_EMR_EM5 EXTI_EMR_MR5
2593 #define EXTI_EMR_EM6 EXTI_EMR_MR6
2594 #define EXTI_EMR_EM7 EXTI_EMR_MR7
2595 #define EXTI_EMR_EM8 EXTI_EMR_MR8
2596 #define EXTI_EMR_EM9 EXTI_EMR_MR9
2597 #define EXTI_EMR_EM10 EXTI_EMR_MR10
2598 #define EXTI_EMR_EM11 EXTI_EMR_MR11
2599 #define EXTI_EMR_EM12 EXTI_EMR_MR12
2600 #define EXTI_EMR_EM13 EXTI_EMR_MR13
2601 #define EXTI_EMR_EM14 EXTI_EMR_MR14
2602 #define EXTI_EMR_EM15 EXTI_EMR_MR15
2603 #define EXTI_EMR_EM16 EXTI_EMR_MR16
2604 #define EXTI_EMR_EM17 EXTI_EMR_MR17
2605 #define EXTI_EMR_EM18 EXTI_EMR_MR18
2606
2607 /****************** Bit definition for EXTI_RTSR register *******************/
2608 #define EXTI_RTSR_TR0_Pos (0U)
2609 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
2610 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
2611 #define EXTI_RTSR_TR1_Pos (1U)
2612 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
2613 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
2614 #define EXTI_RTSR_TR2_Pos (2U)
2615 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
2616 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
2617 #define EXTI_RTSR_TR3_Pos (3U)
2618 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
2619 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
2620 #define EXTI_RTSR_TR4_Pos (4U)
2621 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
2622 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
2623 #define EXTI_RTSR_TR5_Pos (5U)
2624 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
2625 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
2626 #define EXTI_RTSR_TR6_Pos (6U)
2627 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
2628 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
2629 #define EXTI_RTSR_TR7_Pos (7U)
2630 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
2631 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
2632 #define EXTI_RTSR_TR8_Pos (8U)
2633 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
2634 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
2635 #define EXTI_RTSR_TR9_Pos (9U)
2636 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
2637 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
2638 #define EXTI_RTSR_TR10_Pos (10U)
2639 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
2640 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
2641 #define EXTI_RTSR_TR11_Pos (11U)
2642 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
2643 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
2644 #define EXTI_RTSR_TR12_Pos (12U)
2645 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
2646 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
2647 #define EXTI_RTSR_TR13_Pos (13U)
2648 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
2649 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
2650 #define EXTI_RTSR_TR14_Pos (14U)
2651 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
2652 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
2653 #define EXTI_RTSR_TR15_Pos (15U)
2654 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
2655 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
2656 #define EXTI_RTSR_TR16_Pos (16U)
2657 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
2658 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
2659 #define EXTI_RTSR_TR17_Pos (17U)
2660 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
2661 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
2662 #define EXTI_RTSR_TR18_Pos (18U)
2663 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
2664 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
2665
2666 /* References Defines */
2667 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
2668 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
2669 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
2670 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
2671 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
2672 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
2673 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
2674 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
2675 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
2676 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
2677 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
2678 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
2679 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
2680 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
2681 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
2682 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
2683 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
2684 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
2685 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
2686
2687 /****************** Bit definition for EXTI_FTSR register *******************/
2688 #define EXTI_FTSR_TR0_Pos (0U)
2689 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
2690 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
2691 #define EXTI_FTSR_TR1_Pos (1U)
2692 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
2693 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
2694 #define EXTI_FTSR_TR2_Pos (2U)
2695 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
2696 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
2697 #define EXTI_FTSR_TR3_Pos (3U)
2698 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
2699 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
2700 #define EXTI_FTSR_TR4_Pos (4U)
2701 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
2702 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
2703 #define EXTI_FTSR_TR5_Pos (5U)
2704 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
2705 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
2706 #define EXTI_FTSR_TR6_Pos (6U)
2707 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
2708 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
2709 #define EXTI_FTSR_TR7_Pos (7U)
2710 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
2711 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
2712 #define EXTI_FTSR_TR8_Pos (8U)
2713 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
2714 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
2715 #define EXTI_FTSR_TR9_Pos (9U)
2716 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
2717 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
2718 #define EXTI_FTSR_TR10_Pos (10U)
2719 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
2720 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
2721 #define EXTI_FTSR_TR11_Pos (11U)
2722 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
2723 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
2724 #define EXTI_FTSR_TR12_Pos (12U)
2725 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
2726 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
2727 #define EXTI_FTSR_TR13_Pos (13U)
2728 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
2729 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
2730 #define EXTI_FTSR_TR14_Pos (14U)
2731 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
2732 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
2733 #define EXTI_FTSR_TR15_Pos (15U)
2734 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
2735 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
2736 #define EXTI_FTSR_TR16_Pos (16U)
2737 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
2738 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
2739 #define EXTI_FTSR_TR17_Pos (17U)
2740 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
2741 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
2742 #define EXTI_FTSR_TR18_Pos (18U)
2743 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
2744 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
2745
2746 /* References Defines */
2747 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
2748 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
2749 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
2750 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
2751 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
2752 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
2753 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
2754 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
2755 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
2756 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
2757 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
2758 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
2759 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
2760 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
2761 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
2762 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
2763 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
2764 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
2765 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
2766
2767 /****************** Bit definition for EXTI_SWIER register ******************/
2768 #define EXTI_SWIER_SWIER0_Pos (0U)
2769 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
2770 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
2771 #define EXTI_SWIER_SWIER1_Pos (1U)
2772 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
2773 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
2774 #define EXTI_SWIER_SWIER2_Pos (2U)
2775 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
2776 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
2777 #define EXTI_SWIER_SWIER3_Pos (3U)
2778 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
2779 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
2780 #define EXTI_SWIER_SWIER4_Pos (4U)
2781 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
2782 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
2783 #define EXTI_SWIER_SWIER5_Pos (5U)
2784 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
2785 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
2786 #define EXTI_SWIER_SWIER6_Pos (6U)
2787 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
2788 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
2789 #define EXTI_SWIER_SWIER7_Pos (7U)
2790 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
2791 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
2792 #define EXTI_SWIER_SWIER8_Pos (8U)
2793 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
2794 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
2795 #define EXTI_SWIER_SWIER9_Pos (9U)
2796 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
2797 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
2798 #define EXTI_SWIER_SWIER10_Pos (10U)
2799 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
2800 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
2801 #define EXTI_SWIER_SWIER11_Pos (11U)
2802 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
2803 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
2804 #define EXTI_SWIER_SWIER12_Pos (12U)
2805 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
2806 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
2807 #define EXTI_SWIER_SWIER13_Pos (13U)
2808 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
2809 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
2810 #define EXTI_SWIER_SWIER14_Pos (14U)
2811 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
2812 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
2813 #define EXTI_SWIER_SWIER15_Pos (15U)
2814 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
2815 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
2816 #define EXTI_SWIER_SWIER16_Pos (16U)
2817 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
2818 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
2819 #define EXTI_SWIER_SWIER17_Pos (17U)
2820 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
2821 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
2822 #define EXTI_SWIER_SWIER18_Pos (18U)
2823 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
2824 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
2825
2826 /* References Defines */
2827 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
2828 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
2829 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
2830 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
2831 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
2832 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
2833 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
2834 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
2835 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
2836 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
2837 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
2838 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
2839 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
2840 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
2841 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
2842 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
2843 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
2844 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
2845 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
2846
2847 /******************* Bit definition for EXTI_PR register ********************/
2848 #define EXTI_PR_PR0_Pos (0U)
2849 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
2850 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
2851 #define EXTI_PR_PR1_Pos (1U)
2852 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
2853 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
2854 #define EXTI_PR_PR2_Pos (2U)
2855 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
2856 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
2857 #define EXTI_PR_PR3_Pos (3U)
2858 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
2859 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
2860 #define EXTI_PR_PR4_Pos (4U)
2861 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
2862 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
2863 #define EXTI_PR_PR5_Pos (5U)
2864 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
2865 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
2866 #define EXTI_PR_PR6_Pos (6U)
2867 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
2868 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
2869 #define EXTI_PR_PR7_Pos (7U)
2870 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
2871 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
2872 #define EXTI_PR_PR8_Pos (8U)
2873 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
2874 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
2875 #define EXTI_PR_PR9_Pos (9U)
2876 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
2877 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
2878 #define EXTI_PR_PR10_Pos (10U)
2879 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
2880 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
2881 #define EXTI_PR_PR11_Pos (11U)
2882 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
2883 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
2884 #define EXTI_PR_PR12_Pos (12U)
2885 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
2886 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
2887 #define EXTI_PR_PR13_Pos (13U)
2888 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
2889 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
2890 #define EXTI_PR_PR14_Pos (14U)
2891 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
2892 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
2893 #define EXTI_PR_PR15_Pos (15U)
2894 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
2895 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
2896 #define EXTI_PR_PR16_Pos (16U)
2897 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
2898 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
2899 #define EXTI_PR_PR17_Pos (17U)
2900 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
2901 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
2902 #define EXTI_PR_PR18_Pos (18U)
2903 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
2904 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
2905
2906 /* References Defines */
2907 #define EXTI_PR_PIF0 EXTI_PR_PR0
2908 #define EXTI_PR_PIF1 EXTI_PR_PR1
2909 #define EXTI_PR_PIF2 EXTI_PR_PR2
2910 #define EXTI_PR_PIF3 EXTI_PR_PR3
2911 #define EXTI_PR_PIF4 EXTI_PR_PR4
2912 #define EXTI_PR_PIF5 EXTI_PR_PR5
2913 #define EXTI_PR_PIF6 EXTI_PR_PR6
2914 #define EXTI_PR_PIF7 EXTI_PR_PR7
2915 #define EXTI_PR_PIF8 EXTI_PR_PR8
2916 #define EXTI_PR_PIF9 EXTI_PR_PR9
2917 #define EXTI_PR_PIF10 EXTI_PR_PR10
2918 #define EXTI_PR_PIF11 EXTI_PR_PR11
2919 #define EXTI_PR_PIF12 EXTI_PR_PR12
2920 #define EXTI_PR_PIF13 EXTI_PR_PR13
2921 #define EXTI_PR_PIF14 EXTI_PR_PR14
2922 #define EXTI_PR_PIF15 EXTI_PR_PR15
2923 #define EXTI_PR_PIF16 EXTI_PR_PR16
2924 #define EXTI_PR_PIF17 EXTI_PR_PR17
2925 #define EXTI_PR_PIF18 EXTI_PR_PR18
2926
2927 /******************************************************************************/
2928 /* */
2929 /* DMA Controller */
2930 /* */
2931 /******************************************************************************/
2932
2933 /******************* Bit definition for DMA_ISR register ********************/
2934 #define DMA_ISR_GIF1_Pos (0U)
2935 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
2936 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
2937 #define DMA_ISR_TCIF1_Pos (1U)
2938 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
2939 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
2940 #define DMA_ISR_HTIF1_Pos (2U)
2941 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
2942 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
2943 #define DMA_ISR_TEIF1_Pos (3U)
2944 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
2945 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
2946 #define DMA_ISR_GIF2_Pos (4U)
2947 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
2948 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
2949 #define DMA_ISR_TCIF2_Pos (5U)
2950 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
2951 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
2952 #define DMA_ISR_HTIF2_Pos (6U)
2953 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
2954 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
2955 #define DMA_ISR_TEIF2_Pos (7U)
2956 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
2957 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
2958 #define DMA_ISR_GIF3_Pos (8U)
2959 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
2960 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
2961 #define DMA_ISR_TCIF3_Pos (9U)
2962 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
2963 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
2964 #define DMA_ISR_HTIF3_Pos (10U)
2965 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
2966 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
2967 #define DMA_ISR_TEIF3_Pos (11U)
2968 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
2969 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
2970 #define DMA_ISR_GIF4_Pos (12U)
2971 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
2972 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
2973 #define DMA_ISR_TCIF4_Pos (13U)
2974 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
2975 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
2976 #define DMA_ISR_HTIF4_Pos (14U)
2977 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
2978 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
2979 #define DMA_ISR_TEIF4_Pos (15U)
2980 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
2981 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
2982 #define DMA_ISR_GIF5_Pos (16U)
2983 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
2984 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
2985 #define DMA_ISR_TCIF5_Pos (17U)
2986 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
2987 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
2988 #define DMA_ISR_HTIF5_Pos (18U)
2989 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
2990 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
2991 #define DMA_ISR_TEIF5_Pos (19U)
2992 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
2993 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
2994 #define DMA_ISR_GIF6_Pos (20U)
2995 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
2996 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
2997 #define DMA_ISR_TCIF6_Pos (21U)
2998 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
2999 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
3000 #define DMA_ISR_HTIF6_Pos (22U)
3001 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
3002 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
3003 #define DMA_ISR_TEIF6_Pos (23U)
3004 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
3005 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
3006 #define DMA_ISR_GIF7_Pos (24U)
3007 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
3008 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
3009 #define DMA_ISR_TCIF7_Pos (25U)
3010 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
3011 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
3012 #define DMA_ISR_HTIF7_Pos (26U)
3013 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
3014 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
3015 #define DMA_ISR_TEIF7_Pos (27U)
3016 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
3017 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
3018
3019 /******************* Bit definition for DMA_IFCR register *******************/
3020 #define DMA_IFCR_CGIF1_Pos (0U)
3021 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
3022 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
3023 #define DMA_IFCR_CTCIF1_Pos (1U)
3024 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
3025 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
3026 #define DMA_IFCR_CHTIF1_Pos (2U)
3027 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
3028 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
3029 #define DMA_IFCR_CTEIF1_Pos (3U)
3030 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
3031 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
3032 #define DMA_IFCR_CGIF2_Pos (4U)
3033 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
3034 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
3035 #define DMA_IFCR_CTCIF2_Pos (5U)
3036 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
3037 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
3038 #define DMA_IFCR_CHTIF2_Pos (6U)
3039 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
3040 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
3041 #define DMA_IFCR_CTEIF2_Pos (7U)
3042 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
3043 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
3044 #define DMA_IFCR_CGIF3_Pos (8U)
3045 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
3046 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
3047 #define DMA_IFCR_CTCIF3_Pos (9U)
3048 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
3049 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
3050 #define DMA_IFCR_CHTIF3_Pos (10U)
3051 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
3052 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
3053 #define DMA_IFCR_CTEIF3_Pos (11U)
3054 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
3055 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
3056 #define DMA_IFCR_CGIF4_Pos (12U)
3057 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
3058 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
3059 #define DMA_IFCR_CTCIF4_Pos (13U)
3060 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
3061 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
3062 #define DMA_IFCR_CHTIF4_Pos (14U)
3063 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
3064 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
3065 #define DMA_IFCR_CTEIF4_Pos (15U)
3066 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
3067 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
3068 #define DMA_IFCR_CGIF5_Pos (16U)
3069 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
3070 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
3071 #define DMA_IFCR_CTCIF5_Pos (17U)
3072 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
3073 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
3074 #define DMA_IFCR_CHTIF5_Pos (18U)
3075 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
3076 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
3077 #define DMA_IFCR_CTEIF5_Pos (19U)
3078 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
3079 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
3080 #define DMA_IFCR_CGIF6_Pos (20U)
3081 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
3082 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
3083 #define DMA_IFCR_CTCIF6_Pos (21U)
3084 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
3085 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
3086 #define DMA_IFCR_CHTIF6_Pos (22U)
3087 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
3088 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
3089 #define DMA_IFCR_CTEIF6_Pos (23U)
3090 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
3091 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
3092 #define DMA_IFCR_CGIF7_Pos (24U)
3093 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
3094 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
3095 #define DMA_IFCR_CTCIF7_Pos (25U)
3096 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
3097 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
3098 #define DMA_IFCR_CHTIF7_Pos (26U)
3099 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
3100 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
3101 #define DMA_IFCR_CTEIF7_Pos (27U)
3102 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
3103 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
3104
3105 /******************* Bit definition for DMA_CCR register *******************/
3106 #define DMA_CCR_EN_Pos (0U)
3107 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
3108 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
3109 #define DMA_CCR_TCIE_Pos (1U)
3110 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
3111 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
3112 #define DMA_CCR_HTIE_Pos (2U)
3113 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
3114 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
3115 #define DMA_CCR_TEIE_Pos (3U)
3116 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
3117 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
3118 #define DMA_CCR_DIR_Pos (4U)
3119 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
3120 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
3121 #define DMA_CCR_CIRC_Pos (5U)
3122 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
3123 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
3124 #define DMA_CCR_PINC_Pos (6U)
3125 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
3126 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
3127 #define DMA_CCR_MINC_Pos (7U)
3128 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3129 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
3130
3131 #define DMA_CCR_PSIZE_Pos (8U)
3132 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
3133 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
3134 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
3135 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
3136
3137 #define DMA_CCR_MSIZE_Pos (10U)
3138 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
3139 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
3140 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
3141 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
3142
3143 #define DMA_CCR_PL_Pos (12U)
3144 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
3145 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
3146 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
3147 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
3148
3149 #define DMA_CCR_MEM2MEM_Pos (14U)
3150 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
3151 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
3152
3153 /****************** Bit definition for DMA_CNDTR register ******************/
3154 #define DMA_CNDTR_NDT_Pos (0U)
3155 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
3156 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
3157
3158 /****************** Bit definition for DMA_CPAR register *******************/
3159 #define DMA_CPAR_PA_Pos (0U)
3160 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
3161 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
3162
3163 /****************** Bit definition for DMA_CMAR register *******************/
3164 #define DMA_CMAR_MA_Pos (0U)
3165 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
3166 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
3167
3168 /******************************************************************************/
3169 /* */
3170 /* Analog to Digital Converter (ADC) */
3171 /* */
3172 /******************************************************************************/
3173
3174 /*
3175 * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
3176 */
3177 /* Note: No specific macro feature on this device */
3178
3179 /******************** Bit definition for ADC_SR register ********************/
3180 #define ADC_SR_AWD_Pos (0U)
3181 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
3182 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
3183 #define ADC_SR_EOS_Pos (1U)
3184 #define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
3185 #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
3186 #define ADC_SR_JEOS_Pos (2U)
3187 #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
3188 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
3189 #define ADC_SR_JSTRT_Pos (3U)
3190 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
3191 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
3192 #define ADC_SR_STRT_Pos (4U)
3193 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
3194 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
3195
3196 /* Legacy defines */
3197 #define ADC_SR_EOC (ADC_SR_EOS)
3198 #define ADC_SR_JEOC (ADC_SR_JEOS)
3199
3200 /******************* Bit definition for ADC_CR1 register ********************/
3201 #define ADC_CR1_AWDCH_Pos (0U)
3202 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
3203 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
3204 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
3205 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
3206 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
3207 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
3208 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
3209
3210 #define ADC_CR1_EOSIE_Pos (5U)
3211 #define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
3212 #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
3213 #define ADC_CR1_AWDIE_Pos (6U)
3214 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
3215 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
3216 #define ADC_CR1_JEOSIE_Pos (7U)
3217 #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
3218 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
3219 #define ADC_CR1_SCAN_Pos (8U)
3220 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
3221 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
3222 #define ADC_CR1_AWDSGL_Pos (9U)
3223 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
3224 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
3225 #define ADC_CR1_JAUTO_Pos (10U)
3226 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
3227 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
3228 #define ADC_CR1_DISCEN_Pos (11U)
3229 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
3230 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
3231 #define ADC_CR1_JDISCEN_Pos (12U)
3232 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
3233 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
3234
3235 #define ADC_CR1_DISCNUM_Pos (13U)
3236 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
3237 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
3238 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
3239 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
3240 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
3241
3242 #define ADC_CR1_JAWDEN_Pos (22U)
3243 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
3244 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
3245 #define ADC_CR1_AWDEN_Pos (23U)
3246 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
3247 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
3248
3249 /* Legacy defines */
3250 #define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
3251 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
3252
3253 /******************* Bit definition for ADC_CR2 register ********************/
3254 #define ADC_CR2_ADON_Pos (0U)
3255 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
3256 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
3257 #define ADC_CR2_CONT_Pos (1U)
3258 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
3259 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
3260 #define ADC_CR2_CAL_Pos (2U)
3261 #define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
3262 #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
3263 #define ADC_CR2_RSTCAL_Pos (3U)
3264 #define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
3265 #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
3266 #define ADC_CR2_DMA_Pos (8U)
3267 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
3268 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
3269 #define ADC_CR2_ALIGN_Pos (11U)
3270 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
3271 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
3272
3273 #define ADC_CR2_JEXTSEL_Pos (12U)
3274 #define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
3275 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
3276 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
3277 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
3278 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
3279
3280 #define ADC_CR2_JEXTTRIG_Pos (15U)
3281 #define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
3282 #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
3283
3284 #define ADC_CR2_EXTSEL_Pos (17U)
3285 #define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
3286 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
3287 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
3288 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
3289 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
3290
3291 #define ADC_CR2_EXTTRIG_Pos (20U)
3292 #define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
3293 #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
3294 #define ADC_CR2_JSWSTART_Pos (21U)
3295 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
3296 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
3297 #define ADC_CR2_SWSTART_Pos (22U)
3298 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
3299 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
3300 #define ADC_CR2_TSVREFE_Pos (23U)
3301 #define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
3302 #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
3303
3304 /****************** Bit definition for ADC_SMPR1 register *******************/
3305 #define ADC_SMPR1_SMP10_Pos (0U)
3306 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
3307 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
3308 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
3309 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
3310 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
3311
3312 #define ADC_SMPR1_SMP11_Pos (3U)
3313 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
3314 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
3315 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
3316 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
3317 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
3318
3319 #define ADC_SMPR1_SMP12_Pos (6U)
3320 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
3321 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
3322 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
3323 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
3324 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
3325
3326 #define ADC_SMPR1_SMP13_Pos (9U)
3327 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
3328 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
3329 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
3330 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
3331 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
3332
3333 #define ADC_SMPR1_SMP14_Pos (12U)
3334 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
3335 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
3336 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
3337 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
3338 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
3339
3340 #define ADC_SMPR1_SMP15_Pos (15U)
3341 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
3342 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
3343 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
3344 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
3345 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
3346
3347 #define ADC_SMPR1_SMP16_Pos (18U)
3348 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
3349 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
3350 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
3351 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
3352 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
3353
3354 #define ADC_SMPR1_SMP17_Pos (21U)
3355 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
3356 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
3357 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
3358 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
3359 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
3360
3361 /****************** Bit definition for ADC_SMPR2 register *******************/
3362 #define ADC_SMPR2_SMP0_Pos (0U)
3363 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
3364 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
3365 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
3366 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
3367 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
3368
3369 #define ADC_SMPR2_SMP1_Pos (3U)
3370 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
3371 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
3372 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
3373 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
3374 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
3375
3376 #define ADC_SMPR2_SMP2_Pos (6U)
3377 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
3378 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
3379 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
3380 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
3381 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
3382
3383 #define ADC_SMPR2_SMP3_Pos (9U)
3384 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
3385 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
3386 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
3387 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
3388 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
3389
3390 #define ADC_SMPR2_SMP4_Pos (12U)
3391 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
3392 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
3393 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
3394 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
3395 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
3396
3397 #define ADC_SMPR2_SMP5_Pos (15U)
3398 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
3399 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
3400 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
3401 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
3402 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
3403
3404 #define ADC_SMPR2_SMP6_Pos (18U)
3405 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
3406 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
3407 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
3408 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
3409 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
3410
3411 #define ADC_SMPR2_SMP7_Pos (21U)
3412 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
3413 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
3414 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
3415 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
3416 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
3417
3418 #define ADC_SMPR2_SMP8_Pos (24U)
3419 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
3420 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
3421 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
3422 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
3423 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
3424
3425 #define ADC_SMPR2_SMP9_Pos (27U)
3426 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
3427 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
3428 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
3429 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
3430 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
3431
3432 /****************** Bit definition for ADC_JOFR1 register *******************/
3433 #define ADC_JOFR1_JOFFSET1_Pos (0U)
3434 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
3435 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
3436
3437 /****************** Bit definition for ADC_JOFR2 register *******************/
3438 #define ADC_JOFR2_JOFFSET2_Pos (0U)
3439 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
3440 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
3441
3442 /****************** Bit definition for ADC_JOFR3 register *******************/
3443 #define ADC_JOFR3_JOFFSET3_Pos (0U)
3444 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
3445 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
3446
3447 /****************** Bit definition for ADC_JOFR4 register *******************/
3448 #define ADC_JOFR4_JOFFSET4_Pos (0U)
3449 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
3450 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
3451
3452 /******************* Bit definition for ADC_HTR register ********************/
3453 #define ADC_HTR_HT_Pos (0U)
3454 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
3455 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
3456
3457 /******************* Bit definition for ADC_LTR register ********************/
3458 #define ADC_LTR_LT_Pos (0U)
3459 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
3460 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
3461
3462 /******************* Bit definition for ADC_SQR1 register *******************/
3463 #define ADC_SQR1_SQ13_Pos (0U)
3464 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
3465 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
3466 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
3467 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
3468 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
3469 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
3470 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
3471
3472 #define ADC_SQR1_SQ14_Pos (5U)
3473 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
3474 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
3475 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
3476 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
3477 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
3478 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
3479 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
3480
3481 #define ADC_SQR1_SQ15_Pos (10U)
3482 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
3483 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
3484 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
3485 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
3486 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
3487 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
3488 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
3489
3490 #define ADC_SQR1_SQ16_Pos (15U)
3491 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
3492 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
3493 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
3494 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
3495 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
3496 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
3497 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
3498
3499 #define ADC_SQR1_L_Pos (20U)
3500 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
3501 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
3502 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
3503 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
3504 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
3505 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
3506
3507 /******************* Bit definition for ADC_SQR2 register *******************/
3508 #define ADC_SQR2_SQ7_Pos (0U)
3509 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
3510 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
3511 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
3512 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
3513 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
3514 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
3515 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
3516
3517 #define ADC_SQR2_SQ8_Pos (5U)
3518 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
3519 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
3520 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
3521 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
3522 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
3523 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
3524 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
3525
3526 #define ADC_SQR2_SQ9_Pos (10U)
3527 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
3528 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
3529 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
3530 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
3531 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
3532 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
3533 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
3534
3535 #define ADC_SQR2_SQ10_Pos (15U)
3536 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
3537 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
3538 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
3539 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
3540 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
3541 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
3542 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
3543
3544 #define ADC_SQR2_SQ11_Pos (20U)
3545 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
3546 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
3547 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
3548 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
3549 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
3550 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
3551 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
3552
3553 #define ADC_SQR2_SQ12_Pos (25U)
3554 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
3555 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
3556 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
3557 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
3558 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
3559 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
3560 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
3561
3562 /******************* Bit definition for ADC_SQR3 register *******************/
3563 #define ADC_SQR3_SQ1_Pos (0U)
3564 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
3565 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
3566 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
3567 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
3568 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
3569 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
3570 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
3571
3572 #define ADC_SQR3_SQ2_Pos (5U)
3573 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
3574 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
3575 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
3576 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
3577 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
3578 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
3579 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
3580
3581 #define ADC_SQR3_SQ3_Pos (10U)
3582 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
3583 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
3584 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
3585 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
3586 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
3587 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
3588 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
3589
3590 #define ADC_SQR3_SQ4_Pos (15U)
3591 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
3592 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
3593 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
3594 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
3595 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
3596 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
3597 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
3598
3599 #define ADC_SQR3_SQ5_Pos (20U)
3600 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
3601 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
3602 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
3603 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
3604 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
3605 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
3606 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
3607
3608 #define ADC_SQR3_SQ6_Pos (25U)
3609 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
3610 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
3611 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
3612 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
3613 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
3614 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
3615 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
3616
3617 /******************* Bit definition for ADC_JSQR register *******************/
3618 #define ADC_JSQR_JSQ1_Pos (0U)
3619 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
3620 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
3621 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
3622 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
3623 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
3624 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
3625 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
3626
3627 #define ADC_JSQR_JSQ2_Pos (5U)
3628 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
3629 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
3630 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
3631 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
3632 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
3633 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
3634 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
3635
3636 #define ADC_JSQR_JSQ3_Pos (10U)
3637 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
3638 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
3639 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
3640 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
3641 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
3642 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
3643 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
3644
3645 #define ADC_JSQR_JSQ4_Pos (15U)
3646 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
3647 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
3648 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
3649 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
3650 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
3651 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
3652 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
3653
3654 #define ADC_JSQR_JL_Pos (20U)
3655 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
3656 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
3657 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
3658 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
3659
3660 /******************* Bit definition for ADC_JDR1 register *******************/
3661 #define ADC_JDR1_JDATA_Pos (0U)
3662 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
3663 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
3664
3665 /******************* Bit definition for ADC_JDR2 register *******************/
3666 #define ADC_JDR2_JDATA_Pos (0U)
3667 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
3668 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
3669
3670 /******************* Bit definition for ADC_JDR3 register *******************/
3671 #define ADC_JDR3_JDATA_Pos (0U)
3672 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
3673 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
3674
3675 /******************* Bit definition for ADC_JDR4 register *******************/
3676 #define ADC_JDR4_JDATA_Pos (0U)
3677 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
3678 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
3679
3680 /******************** Bit definition for ADC_DR register ********************/
3681 #define ADC_DR_DATA_Pos (0U)
3682 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
3683 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
3684
3685
3686 /*****************************************************************************/
3687 /* */
3688 /* Timers (TIM) */
3689 /* */
3690 /*****************************************************************************/
3691 /******************* Bit definition for TIM_CR1 register *******************/
3692 #define TIM_CR1_CEN_Pos (0U)
3693 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
3694 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
3695 #define TIM_CR1_UDIS_Pos (1U)
3696 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
3697 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
3698 #define TIM_CR1_URS_Pos (2U)
3699 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
3700 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
3701 #define TIM_CR1_OPM_Pos (3U)
3702 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
3703 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
3704 #define TIM_CR1_DIR_Pos (4U)
3705 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
3706 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
3707
3708 #define TIM_CR1_CMS_Pos (5U)
3709 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
3710 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
3711 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
3712 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
3713
3714 #define TIM_CR1_ARPE_Pos (7U)
3715 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
3716 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
3717
3718 #define TIM_CR1_CKD_Pos (8U)
3719 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
3720 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
3721 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
3722 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
3723
3724 /******************* Bit definition for TIM_CR2 register *******************/
3725 #define TIM_CR2_CCPC_Pos (0U)
3726 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
3727 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
3728 #define TIM_CR2_CCUS_Pos (2U)
3729 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
3730 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
3731 #define TIM_CR2_CCDS_Pos (3U)
3732 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
3733 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
3734
3735 #define TIM_CR2_MMS_Pos (4U)
3736 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
3737 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
3738 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
3739 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
3740 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
3741
3742 #define TIM_CR2_TI1S_Pos (7U)
3743 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
3744 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
3745 #define TIM_CR2_OIS1_Pos (8U)
3746 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
3747 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
3748 #define TIM_CR2_OIS1N_Pos (9U)
3749 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
3750 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
3751 #define TIM_CR2_OIS2_Pos (10U)
3752 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
3753 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
3754 #define TIM_CR2_OIS2N_Pos (11U)
3755 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
3756 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
3757 #define TIM_CR2_OIS3_Pos (12U)
3758 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
3759 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
3760 #define TIM_CR2_OIS3N_Pos (13U)
3761 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
3762 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
3763 #define TIM_CR2_OIS4_Pos (14U)
3764 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
3765 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
3766
3767 /******************* Bit definition for TIM_SMCR register ******************/
3768 #define TIM_SMCR_SMS_Pos (0U)
3769 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
3770 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
3771 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
3772 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
3773 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
3774
3775 #define TIM_SMCR_TS_Pos (4U)
3776 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
3777 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
3778 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
3779 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
3780 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
3781
3782 #define TIM_SMCR_MSM_Pos (7U)
3783 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
3784 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
3785
3786 #define TIM_SMCR_ETF_Pos (8U)
3787 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
3788 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
3789 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
3790 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
3791 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
3792 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
3793
3794 #define TIM_SMCR_ETPS_Pos (12U)
3795 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
3796 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
3797 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
3798 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
3799
3800 #define TIM_SMCR_ECE_Pos (14U)
3801 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
3802 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
3803 #define TIM_SMCR_ETP_Pos (15U)
3804 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
3805 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
3806
3807 /******************* Bit definition for TIM_DIER register ******************/
3808 #define TIM_DIER_UIE_Pos (0U)
3809 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
3810 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
3811 #define TIM_DIER_CC1IE_Pos (1U)
3812 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
3813 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
3814 #define TIM_DIER_CC2IE_Pos (2U)
3815 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
3816 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
3817 #define TIM_DIER_CC3IE_Pos (3U)
3818 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
3819 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
3820 #define TIM_DIER_CC4IE_Pos (4U)
3821 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
3822 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
3823 #define TIM_DIER_COMIE_Pos (5U)
3824 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
3825 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
3826 #define TIM_DIER_TIE_Pos (6U)
3827 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
3828 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
3829 #define TIM_DIER_BIE_Pos (7U)
3830 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
3831 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
3832 #define TIM_DIER_UDE_Pos (8U)
3833 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
3834 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
3835 #define TIM_DIER_CC1DE_Pos (9U)
3836 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
3837 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
3838 #define TIM_DIER_CC2DE_Pos (10U)
3839 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
3840 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
3841 #define TIM_DIER_CC3DE_Pos (11U)
3842 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
3843 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
3844 #define TIM_DIER_CC4DE_Pos (12U)
3845 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
3846 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
3847 #define TIM_DIER_COMDE_Pos (13U)
3848 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
3849 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
3850 #define TIM_DIER_TDE_Pos (14U)
3851 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
3852 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
3853
3854 /******************** Bit definition for TIM_SR register *******************/
3855 #define TIM_SR_UIF_Pos (0U)
3856 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
3857 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
3858 #define TIM_SR_CC1IF_Pos (1U)
3859 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
3860 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
3861 #define TIM_SR_CC2IF_Pos (2U)
3862 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
3863 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
3864 #define TIM_SR_CC3IF_Pos (3U)
3865 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
3866 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
3867 #define TIM_SR_CC4IF_Pos (4U)
3868 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
3869 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
3870 #define TIM_SR_COMIF_Pos (5U)
3871 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
3872 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
3873 #define TIM_SR_TIF_Pos (6U)
3874 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
3875 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
3876 #define TIM_SR_BIF_Pos (7U)
3877 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
3878 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
3879 #define TIM_SR_CC1OF_Pos (9U)
3880 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
3881 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
3882 #define TIM_SR_CC2OF_Pos (10U)
3883 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
3884 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
3885 #define TIM_SR_CC3OF_Pos (11U)
3886 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
3887 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
3888 #define TIM_SR_CC4OF_Pos (12U)
3889 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
3890 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
3891
3892 /******************* Bit definition for TIM_EGR register *******************/
3893 #define TIM_EGR_UG_Pos (0U)
3894 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
3895 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
3896 #define TIM_EGR_CC1G_Pos (1U)
3897 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
3898 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
3899 #define TIM_EGR_CC2G_Pos (2U)
3900 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
3901 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
3902 #define TIM_EGR_CC3G_Pos (3U)
3903 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
3904 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
3905 #define TIM_EGR_CC4G_Pos (4U)
3906 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
3907 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
3908 #define TIM_EGR_COMG_Pos (5U)
3909 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
3910 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
3911 #define TIM_EGR_TG_Pos (6U)
3912 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
3913 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
3914 #define TIM_EGR_BG_Pos (7U)
3915 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
3916 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
3917
3918 /****************** Bit definition for TIM_CCMR1 register ******************/
3919 #define TIM_CCMR1_CC1S_Pos (0U)
3920 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
3921 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
3922 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
3923 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
3924
3925 #define TIM_CCMR1_OC1FE_Pos (2U)
3926 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
3927 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
3928 #define TIM_CCMR1_OC1PE_Pos (3U)
3929 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
3930 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
3931
3932 #define TIM_CCMR1_OC1M_Pos (4U)
3933 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
3934 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
3935 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
3936 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
3937 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
3938
3939 #define TIM_CCMR1_OC1CE_Pos (7U)
3940 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
3941 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
3942
3943 #define TIM_CCMR1_CC2S_Pos (8U)
3944 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
3945 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
3946 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
3947 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
3948
3949 #define TIM_CCMR1_OC2FE_Pos (10U)
3950 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
3951 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
3952 #define TIM_CCMR1_OC2PE_Pos (11U)
3953 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
3954 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
3955
3956 #define TIM_CCMR1_OC2M_Pos (12U)
3957 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
3958 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
3959 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
3960 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
3961 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
3962
3963 #define TIM_CCMR1_OC2CE_Pos (15U)
3964 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
3965 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
3966
3967 /*---------------------------------------------------------------------------*/
3968
3969 #define TIM_CCMR1_IC1PSC_Pos (2U)
3970 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
3971 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
3972 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
3973 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
3974
3975 #define TIM_CCMR1_IC1F_Pos (4U)
3976 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
3977 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
3978 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
3979 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
3980 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
3981 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
3982
3983 #define TIM_CCMR1_IC2PSC_Pos (10U)
3984 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
3985 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
3986 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
3987 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
3988
3989 #define TIM_CCMR1_IC2F_Pos (12U)
3990 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
3991 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
3992 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
3993 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
3994 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
3995 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
3996
3997 /****************** Bit definition for TIM_CCMR2 register ******************/
3998 #define TIM_CCMR2_CC3S_Pos (0U)
3999 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
4000 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
4001 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
4002 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
4003
4004 #define TIM_CCMR2_OC3FE_Pos (2U)
4005 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
4006 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
4007 #define TIM_CCMR2_OC3PE_Pos (3U)
4008 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
4009 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
4010
4011 #define TIM_CCMR2_OC3M_Pos (4U)
4012 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
4013 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
4014 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
4015 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
4016 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
4017
4018 #define TIM_CCMR2_OC3CE_Pos (7U)
4019 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
4020 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
4021
4022 #define TIM_CCMR2_CC4S_Pos (8U)
4023 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
4024 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
4025 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
4026 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
4027
4028 #define TIM_CCMR2_OC4FE_Pos (10U)
4029 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
4030 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
4031 #define TIM_CCMR2_OC4PE_Pos (11U)
4032 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
4033 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
4034
4035 #define TIM_CCMR2_OC4M_Pos (12U)
4036 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
4037 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
4038 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
4039 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
4040 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
4041
4042 #define TIM_CCMR2_OC4CE_Pos (15U)
4043 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
4044 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
4045
4046 /*---------------------------------------------------------------------------*/
4047
4048 #define TIM_CCMR2_IC3PSC_Pos (2U)
4049 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
4050 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
4051 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
4052 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
4053
4054 #define TIM_CCMR2_IC3F_Pos (4U)
4055 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
4056 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
4057 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
4058 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
4059 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
4060 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
4061
4062 #define TIM_CCMR2_IC4PSC_Pos (10U)
4063 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
4064 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
4065 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
4066 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
4067
4068 #define TIM_CCMR2_IC4F_Pos (12U)
4069 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
4070 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
4071 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
4072 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
4073 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
4074 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
4075
4076 /******************* Bit definition for TIM_CCER register ******************/
4077 #define TIM_CCER_CC1E_Pos (0U)
4078 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
4079 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
4080 #define TIM_CCER_CC1P_Pos (1U)
4081 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
4082 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
4083 #define TIM_CCER_CC1NE_Pos (2U)
4084 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
4085 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
4086 #define TIM_CCER_CC1NP_Pos (3U)
4087 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
4088 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
4089 #define TIM_CCER_CC2E_Pos (4U)
4090 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
4091 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
4092 #define TIM_CCER_CC2P_Pos (5U)
4093 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
4094 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
4095 #define TIM_CCER_CC2NE_Pos (6U)
4096 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
4097 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
4098 #define TIM_CCER_CC2NP_Pos (7U)
4099 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
4100 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
4101 #define TIM_CCER_CC3E_Pos (8U)
4102 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
4103 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
4104 #define TIM_CCER_CC3P_Pos (9U)
4105 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
4106 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
4107 #define TIM_CCER_CC3NE_Pos (10U)
4108 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
4109 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
4110 #define TIM_CCER_CC3NP_Pos (11U)
4111 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
4112 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
4113 #define TIM_CCER_CC4E_Pos (12U)
4114 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
4115 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
4116 #define TIM_CCER_CC4P_Pos (13U)
4117 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
4118 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
4119
4120 /******************* Bit definition for TIM_CNT register *******************/
4121 #define TIM_CNT_CNT_Pos (0U)
4122 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
4123 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
4124
4125 /******************* Bit definition for TIM_PSC register *******************/
4126 #define TIM_PSC_PSC_Pos (0U)
4127 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
4128 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
4129
4130 /******************* Bit definition for TIM_ARR register *******************/
4131 #define TIM_ARR_ARR_Pos (0U)
4132 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
4133 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
4134
4135 /******************* Bit definition for TIM_RCR register *******************/
4136 #define TIM_RCR_REP_Pos (0U)
4137 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
4138 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
4139
4140 /******************* Bit definition for TIM_CCR1 register ******************/
4141 #define TIM_CCR1_CCR1_Pos (0U)
4142 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
4143 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
4144
4145 /******************* Bit definition for TIM_CCR2 register ******************/
4146 #define TIM_CCR2_CCR2_Pos (0U)
4147 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
4148 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
4149
4150 /******************* Bit definition for TIM_CCR3 register ******************/
4151 #define TIM_CCR3_CCR3_Pos (0U)
4152 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
4153 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
4154
4155 /******************* Bit definition for TIM_CCR4 register ******************/
4156 #define TIM_CCR4_CCR4_Pos (0U)
4157 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
4158 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
4159
4160 /******************* Bit definition for TIM_BDTR register ******************/
4161 #define TIM_BDTR_DTG_Pos (0U)
4162 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
4163 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
4164 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
4165 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
4166 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
4167 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
4168 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
4169 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
4170 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
4171 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
4172
4173 #define TIM_BDTR_LOCK_Pos (8U)
4174 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
4175 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
4176 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
4177 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
4178
4179 #define TIM_BDTR_OSSI_Pos (10U)
4180 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
4181 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
4182 #define TIM_BDTR_OSSR_Pos (11U)
4183 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
4184 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
4185 #define TIM_BDTR_BKE_Pos (12U)
4186 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
4187 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
4188 #define TIM_BDTR_BKP_Pos (13U)
4189 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
4190 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
4191 #define TIM_BDTR_AOE_Pos (14U)
4192 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
4193 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
4194 #define TIM_BDTR_MOE_Pos (15U)
4195 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
4196 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
4197
4198 /******************* Bit definition for TIM_DCR register *******************/
4199 #define TIM_DCR_DBA_Pos (0U)
4200 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
4201 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
4202 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
4203 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
4204 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
4205 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
4206 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
4207
4208 #define TIM_DCR_DBL_Pos (8U)
4209 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
4210 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
4211 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
4212 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
4213 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
4214 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
4215 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
4216
4217 /******************* Bit definition for TIM_DMAR register ******************/
4218 #define TIM_DMAR_DMAB_Pos (0U)
4219 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
4220 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
4221
4222 /******************************************************************************/
4223 /* */
4224 /* Real-Time Clock */
4225 /* */
4226 /******************************************************************************/
4227
4228 /******************* Bit definition for RTC_CRH register ********************/
4229 #define RTC_CRH_SECIE_Pos (0U)
4230 #define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
4231 #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
4232 #define RTC_CRH_ALRIE_Pos (1U)
4233 #define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
4234 #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
4235 #define RTC_CRH_OWIE_Pos (2U)
4236 #define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
4237 #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
4238
4239 /******************* Bit definition for RTC_CRL register ********************/
4240 #define RTC_CRL_SECF_Pos (0U)
4241 #define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
4242 #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
4243 #define RTC_CRL_ALRF_Pos (1U)
4244 #define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
4245 #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
4246 #define RTC_CRL_OWF_Pos (2U)
4247 #define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
4248 #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
4249 #define RTC_CRL_RSF_Pos (3U)
4250 #define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
4251 #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
4252 #define RTC_CRL_CNF_Pos (4U)
4253 #define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
4254 #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
4255 #define RTC_CRL_RTOFF_Pos (5U)
4256 #define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
4257 #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
4258
4259 /******************* Bit definition for RTC_PRLH register *******************/
4260 #define RTC_PRLH_PRL_Pos (0U)
4261 #define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
4262 #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
4263
4264 /******************* Bit definition for RTC_PRLL register *******************/
4265 #define RTC_PRLL_PRL_Pos (0U)
4266 #define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
4267 #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
4268
4269 /******************* Bit definition for RTC_DIVH register *******************/
4270 #define RTC_DIVH_RTC_DIV_Pos (0U)
4271 #define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
4272 #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
4273
4274 /******************* Bit definition for RTC_DIVL register *******************/
4275 #define RTC_DIVL_RTC_DIV_Pos (0U)
4276 #define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
4277 #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
4278
4279 /******************* Bit definition for RTC_CNTH register *******************/
4280 #define RTC_CNTH_RTC_CNT_Pos (0U)
4281 #define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
4282 #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
4283
4284 /******************* Bit definition for RTC_CNTL register *******************/
4285 #define RTC_CNTL_RTC_CNT_Pos (0U)
4286 #define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
4287 #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
4288
4289 /******************* Bit definition for RTC_ALRH register *******************/
4290 #define RTC_ALRH_RTC_ALR_Pos (0U)
4291 #define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
4292 #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
4293
4294 /******************* Bit definition for RTC_ALRL register *******************/
4295 #define RTC_ALRL_RTC_ALR_Pos (0U)
4296 #define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
4297 #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
4298
4299 /******************************************************************************/
4300 /* */
4301 /* Independent WATCHDOG (IWDG) */
4302 /* */
4303 /******************************************************************************/
4304
4305 /******************* Bit definition for IWDG_KR register ********************/
4306 #define IWDG_KR_KEY_Pos (0U)
4307 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
4308 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
4309
4310 /******************* Bit definition for IWDG_PR register ********************/
4311 #define IWDG_PR_PR_Pos (0U)
4312 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
4313 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
4314 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
4315 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
4316 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
4317
4318 /******************* Bit definition for IWDG_RLR register *******************/
4319 #define IWDG_RLR_RL_Pos (0U)
4320 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
4321 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
4322
4323 /******************* Bit definition for IWDG_SR register ********************/
4324 #define IWDG_SR_PVU_Pos (0U)
4325 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
4326 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
4327 #define IWDG_SR_RVU_Pos (1U)
4328 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
4329 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
4330
4331 /******************************************************************************/
4332 /* */
4333 /* Window WATCHDOG (WWDG) */
4334 /* */
4335 /******************************************************************************/
4336
4337 /******************* Bit definition for WWDG_CR register ********************/
4338 #define WWDG_CR_T_Pos (0U)
4339 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
4340 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
4341 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
4342 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
4343 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
4344 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
4345 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
4346 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
4347 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
4348
4349 /* Legacy defines */
4350 #define WWDG_CR_T0 WWDG_CR_T_0
4351 #define WWDG_CR_T1 WWDG_CR_T_1
4352 #define WWDG_CR_T2 WWDG_CR_T_2
4353 #define WWDG_CR_T3 WWDG_CR_T_3
4354 #define WWDG_CR_T4 WWDG_CR_T_4
4355 #define WWDG_CR_T5 WWDG_CR_T_5
4356 #define WWDG_CR_T6 WWDG_CR_T_6
4357
4358 #define WWDG_CR_WDGA_Pos (7U)
4359 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
4360 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
4361
4362 /******************* Bit definition for WWDG_CFR register *******************/
4363 #define WWDG_CFR_W_Pos (0U)
4364 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
4365 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
4366 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
4367 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
4368 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
4369 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
4370 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
4371 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
4372 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
4373
4374 /* Legacy defines */
4375 #define WWDG_CFR_W0 WWDG_CFR_W_0
4376 #define WWDG_CFR_W1 WWDG_CFR_W_1
4377 #define WWDG_CFR_W2 WWDG_CFR_W_2
4378 #define WWDG_CFR_W3 WWDG_CFR_W_3
4379 #define WWDG_CFR_W4 WWDG_CFR_W_4
4380 #define WWDG_CFR_W5 WWDG_CFR_W_5
4381 #define WWDG_CFR_W6 WWDG_CFR_W_6
4382
4383 #define WWDG_CFR_WDGTB_Pos (7U)
4384 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
4385 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
4386 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
4387 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
4388
4389 /* Legacy defines */
4390 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
4391 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
4392
4393 #define WWDG_CFR_EWI_Pos (9U)
4394 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
4395 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
4396
4397 /******************* Bit definition for WWDG_SR register ********************/
4398 #define WWDG_SR_EWIF_Pos (0U)
4399 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
4400 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
4401
4402
4403 /******************************************************************************/
4404 /* */
4405 /* SD host Interface */
4406 /* */
4407 /******************************************************************************/
4408
4409 /****************** Bit definition for SDIO_POWER register ******************/
4410 #define SDIO_POWER_PWRCTRL_Pos (0U)
4411 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
4412 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
4413 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
4414 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
4415
4416 /****************** Bit definition for SDIO_CLKCR register ******************/
4417 #define SDIO_CLKCR_CLKDIV_Pos (0U)
4418 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
4419 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
4420 #define SDIO_CLKCR_CLKEN_Pos (8U)
4421 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
4422 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
4423 #define SDIO_CLKCR_PWRSAV_Pos (9U)
4424 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
4425 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
4426 #define SDIO_CLKCR_BYPASS_Pos (10U)
4427 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
4428 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
4429
4430 #define SDIO_CLKCR_WIDBUS_Pos (11U)
4431 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
4432 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
4433 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
4434 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
4435
4436 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
4437 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
4438 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
4439 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
4440 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
4441 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
4442
4443 /******************* Bit definition for SDIO_ARG register *******************/
4444 #define SDIO_ARG_CMDARG_Pos (0U)
4445 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
4446 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
4447
4448 /******************* Bit definition for SDIO_CMD register *******************/
4449 #define SDIO_CMD_CMDINDEX_Pos (0U)
4450 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
4451 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
4452
4453 #define SDIO_CMD_WAITRESP_Pos (6U)
4454 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
4455 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
4456 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
4457 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
4458
4459 #define SDIO_CMD_WAITINT_Pos (8U)
4460 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
4461 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
4462 #define SDIO_CMD_WAITPEND_Pos (9U)
4463 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
4464 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
4465 #define SDIO_CMD_CPSMEN_Pos (10U)
4466 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
4467 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
4468 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
4469 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
4470 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
4471 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
4472 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
4473 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
4474 #define SDIO_CMD_NIEN_Pos (13U)
4475 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
4476 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
4477 #define SDIO_CMD_CEATACMD_Pos (14U)
4478 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
4479 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
4480
4481 /***************** Bit definition for SDIO_RESPCMD register *****************/
4482 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
4483 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
4484 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
4485
4486 /****************** Bit definition for SDIO_RESP0 register ******************/
4487 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
4488 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
4489 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
4490
4491 /****************** Bit definition for SDIO_RESP1 register ******************/
4492 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
4493 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
4494 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
4495
4496 /****************** Bit definition for SDIO_RESP2 register ******************/
4497 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
4498 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
4499 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
4500
4501 /****************** Bit definition for SDIO_RESP3 register ******************/
4502 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
4503 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
4504 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
4505
4506 /****************** Bit definition for SDIO_RESP4 register ******************/
4507 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
4508 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
4509 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
4510
4511 /****************** Bit definition for SDIO_DTIMER register *****************/
4512 #define SDIO_DTIMER_DATATIME_Pos (0U)
4513 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
4514 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
4515
4516 /****************** Bit definition for SDIO_DLEN register *******************/
4517 #define SDIO_DLEN_DATALENGTH_Pos (0U)
4518 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
4519 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
4520
4521 /****************** Bit definition for SDIO_DCTRL register ******************/
4522 #define SDIO_DCTRL_DTEN_Pos (0U)
4523 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
4524 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
4525 #define SDIO_DCTRL_DTDIR_Pos (1U)
4526 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
4527 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
4528 #define SDIO_DCTRL_DTMODE_Pos (2U)
4529 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
4530 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
4531 #define SDIO_DCTRL_DMAEN_Pos (3U)
4532 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
4533 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
4534
4535 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
4536 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
4537 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
4538 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
4539 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
4540 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
4541 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
4542
4543 #define SDIO_DCTRL_RWSTART_Pos (8U)
4544 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
4545 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
4546 #define SDIO_DCTRL_RWSTOP_Pos (9U)
4547 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
4548 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
4549 #define SDIO_DCTRL_RWMOD_Pos (10U)
4550 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
4551 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
4552 #define SDIO_DCTRL_SDIOEN_Pos (11U)
4553 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
4554 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
4555
4556 /****************** Bit definition for SDIO_DCOUNT register *****************/
4557 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
4558 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
4559 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
4560
4561 /****************** Bit definition for SDIO_STA register ********************/
4562 #define SDIO_STA_CCRCFAIL_Pos (0U)
4563 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
4564 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
4565 #define SDIO_STA_DCRCFAIL_Pos (1U)
4566 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
4567 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
4568 #define SDIO_STA_CTIMEOUT_Pos (2U)
4569 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
4570 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
4571 #define SDIO_STA_DTIMEOUT_Pos (3U)
4572 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
4573 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
4574 #define SDIO_STA_TXUNDERR_Pos (4U)
4575 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
4576 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
4577 #define SDIO_STA_RXOVERR_Pos (5U)
4578 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
4579 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
4580 #define SDIO_STA_CMDREND_Pos (6U)
4581 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
4582 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
4583 #define SDIO_STA_CMDSENT_Pos (7U)
4584 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
4585 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
4586 #define SDIO_STA_DATAEND_Pos (8U)
4587 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
4588 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
4589 #define SDIO_STA_STBITERR_Pos (9U)
4590 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
4591 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
4592 #define SDIO_STA_DBCKEND_Pos (10U)
4593 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
4594 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
4595 #define SDIO_STA_CMDACT_Pos (11U)
4596 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
4597 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
4598 #define SDIO_STA_TXACT_Pos (12U)
4599 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
4600 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
4601 #define SDIO_STA_RXACT_Pos (13U)
4602 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
4603 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
4604 #define SDIO_STA_TXFIFOHE_Pos (14U)
4605 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
4606 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
4607 #define SDIO_STA_RXFIFOHF_Pos (15U)
4608 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
4609 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
4610 #define SDIO_STA_TXFIFOF_Pos (16U)
4611 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
4612 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
4613 #define SDIO_STA_RXFIFOF_Pos (17U)
4614 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
4615 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
4616 #define SDIO_STA_TXFIFOE_Pos (18U)
4617 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
4618 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
4619 #define SDIO_STA_RXFIFOE_Pos (19U)
4620 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
4621 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
4622 #define SDIO_STA_TXDAVL_Pos (20U)
4623 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
4624 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
4625 #define SDIO_STA_RXDAVL_Pos (21U)
4626 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
4627 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
4628 #define SDIO_STA_SDIOIT_Pos (22U)
4629 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
4630 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
4631 #define SDIO_STA_CEATAEND_Pos (23U)
4632 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
4633 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
4634
4635 /******************* Bit definition for SDIO_ICR register *******************/
4636 #define SDIO_ICR_CCRCFAILC_Pos (0U)
4637 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
4638 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
4639 #define SDIO_ICR_DCRCFAILC_Pos (1U)
4640 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
4641 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
4642 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
4643 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
4644 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
4645 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
4646 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
4647 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
4648 #define SDIO_ICR_TXUNDERRC_Pos (4U)
4649 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
4650 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
4651 #define SDIO_ICR_RXOVERRC_Pos (5U)
4652 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
4653 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
4654 #define SDIO_ICR_CMDRENDC_Pos (6U)
4655 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
4656 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
4657 #define SDIO_ICR_CMDSENTC_Pos (7U)
4658 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
4659 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
4660 #define SDIO_ICR_DATAENDC_Pos (8U)
4661 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
4662 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
4663 #define SDIO_ICR_STBITERRC_Pos (9U)
4664 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
4665 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
4666 #define SDIO_ICR_DBCKENDC_Pos (10U)
4667 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
4668 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
4669 #define SDIO_ICR_SDIOITC_Pos (22U)
4670 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
4671 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
4672 #define SDIO_ICR_CEATAENDC_Pos (23U)
4673 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
4674 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
4675
4676 /****************** Bit definition for SDIO_MASK register *******************/
4677 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
4678 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
4679 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
4680 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
4681 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
4682 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
4683 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
4684 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
4685 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
4686 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
4687 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
4688 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
4689 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
4690 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
4691 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
4692 #define SDIO_MASK_RXOVERRIE_Pos (5U)
4693 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
4694 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
4695 #define SDIO_MASK_CMDRENDIE_Pos (6U)
4696 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
4697 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
4698 #define SDIO_MASK_CMDSENTIE_Pos (7U)
4699 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
4700 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
4701 #define SDIO_MASK_DATAENDIE_Pos (8U)
4702 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
4703 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
4704 #define SDIO_MASK_STBITERRIE_Pos (9U)
4705 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
4706 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
4707 #define SDIO_MASK_DBCKENDIE_Pos (10U)
4708 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
4709 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
4710 #define SDIO_MASK_CMDACTIE_Pos (11U)
4711 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
4712 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
4713 #define SDIO_MASK_TXACTIE_Pos (12U)
4714 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
4715 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
4716 #define SDIO_MASK_RXACTIE_Pos (13U)
4717 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
4718 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
4719 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
4720 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
4721 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
4722 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
4723 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
4724 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
4725 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
4726 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
4727 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
4728 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
4729 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
4730 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
4731 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
4732 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
4733 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
4734 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
4735 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
4736 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
4737 #define SDIO_MASK_TXDAVLIE_Pos (20U)
4738 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
4739 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
4740 #define SDIO_MASK_RXDAVLIE_Pos (21U)
4741 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
4742 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
4743 #define SDIO_MASK_SDIOITIE_Pos (22U)
4744 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
4745 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
4746 #define SDIO_MASK_CEATAENDIE_Pos (23U)
4747 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
4748 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
4749
4750 /***************** Bit definition for SDIO_FIFOCNT register *****************/
4751 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
4752 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
4753 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
4754
4755 /****************** Bit definition for SDIO_FIFO register *******************/
4756 #define SDIO_FIFO_FIFODATA_Pos (0U)
4757 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
4758 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
4759
4760
4761
4762 /******************************************************************************/
4763 /* */
4764 /* Serial Peripheral Interface */
4765 /* */
4766 /******************************************************************************/
4767
4768 /******************* Bit definition for SPI_CR1 register ********************/
4769 #define SPI_CR1_CPHA_Pos (0U)
4770 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
4771 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
4772 #define SPI_CR1_CPOL_Pos (1U)
4773 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
4774 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
4775 #define SPI_CR1_MSTR_Pos (2U)
4776 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
4777 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
4778
4779 #define SPI_CR1_BR_Pos (3U)
4780 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
4781 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
4782 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
4783 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
4784 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
4785
4786 #define SPI_CR1_SPE_Pos (6U)
4787 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
4788 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
4789 #define SPI_CR1_LSBFIRST_Pos (7U)
4790 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
4791 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
4792 #define SPI_CR1_SSI_Pos (8U)
4793 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
4794 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
4795 #define SPI_CR1_SSM_Pos (9U)
4796 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
4797 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
4798 #define SPI_CR1_RXONLY_Pos (10U)
4799 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
4800 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
4801 #define SPI_CR1_DFF_Pos (11U)
4802 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
4803 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
4804 #define SPI_CR1_CRCNEXT_Pos (12U)
4805 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
4806 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
4807 #define SPI_CR1_CRCEN_Pos (13U)
4808 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
4809 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
4810 #define SPI_CR1_BIDIOE_Pos (14U)
4811 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
4812 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
4813 #define SPI_CR1_BIDIMODE_Pos (15U)
4814 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
4815 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
4816
4817 /******************* Bit definition for SPI_CR2 register ********************/
4818 #define SPI_CR2_RXDMAEN_Pos (0U)
4819 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
4820 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
4821 #define SPI_CR2_TXDMAEN_Pos (1U)
4822 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
4823 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
4824 #define SPI_CR2_SSOE_Pos (2U)
4825 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
4826 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
4827 #define SPI_CR2_ERRIE_Pos (5U)
4828 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
4829 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
4830 #define SPI_CR2_RXNEIE_Pos (6U)
4831 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
4832 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
4833 #define SPI_CR2_TXEIE_Pos (7U)
4834 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
4835 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
4836
4837 /******************** Bit definition for SPI_SR register ********************/
4838 #define SPI_SR_RXNE_Pos (0U)
4839 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
4840 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
4841 #define SPI_SR_TXE_Pos (1U)
4842 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
4843 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
4844 #define SPI_SR_CHSIDE_Pos (2U)
4845 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
4846 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
4847 #define SPI_SR_UDR_Pos (3U)
4848 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
4849 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
4850 #define SPI_SR_CRCERR_Pos (4U)
4851 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
4852 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
4853 #define SPI_SR_MODF_Pos (5U)
4854 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
4855 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
4856 #define SPI_SR_OVR_Pos (6U)
4857 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
4858 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
4859 #define SPI_SR_BSY_Pos (7U)
4860 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
4861 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
4862
4863 /******************** Bit definition for SPI_DR register ********************/
4864 #define SPI_DR_DR_Pos (0U)
4865 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
4866 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
4867
4868 /******************* Bit definition for SPI_CRCPR register ******************/
4869 #define SPI_CRCPR_CRCPOLY_Pos (0U)
4870 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
4871 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
4872
4873 /****************** Bit definition for SPI_RXCRCR register ******************/
4874 #define SPI_RXCRCR_RXCRC_Pos (0U)
4875 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
4876 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
4877
4878 /****************** Bit definition for SPI_TXCRCR register ******************/
4879 #define SPI_TXCRCR_TXCRC_Pos (0U)
4880 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
4881 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
4882
4883 /****************** Bit definition for SPI_I2SCFGR register *****************/
4884 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
4885 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
4886 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
4887
4888
4889 /******************************************************************************/
4890 /* */
4891 /* Inter-integrated Circuit Interface */
4892 /* */
4893 /******************************************************************************/
4894
4895 /******************* Bit definition for I2C_CR1 register ********************/
4896 #define I2C_CR1_PE_Pos (0U)
4897 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
4898 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
4899 #define I2C_CR1_SMBUS_Pos (1U)
4900 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
4901 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
4902 #define I2C_CR1_SMBTYPE_Pos (3U)
4903 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
4904 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
4905 #define I2C_CR1_ENARP_Pos (4U)
4906 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
4907 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
4908 #define I2C_CR1_ENPEC_Pos (5U)
4909 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
4910 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
4911 #define I2C_CR1_ENGC_Pos (6U)
4912 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
4913 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
4914 #define I2C_CR1_NOSTRETCH_Pos (7U)
4915 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
4916 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
4917 #define I2C_CR1_START_Pos (8U)
4918 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
4919 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
4920 #define I2C_CR1_STOP_Pos (9U)
4921 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
4922 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
4923 #define I2C_CR1_ACK_Pos (10U)
4924 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
4925 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
4926 #define I2C_CR1_POS_Pos (11U)
4927 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
4928 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
4929 #define I2C_CR1_PEC_Pos (12U)
4930 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
4931 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
4932 #define I2C_CR1_ALERT_Pos (13U)
4933 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
4934 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
4935 #define I2C_CR1_SWRST_Pos (15U)
4936 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
4937 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
4938
4939 /******************* Bit definition for I2C_CR2 register ********************/
4940 #define I2C_CR2_FREQ_Pos (0U)
4941 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
4942 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
4943 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
4944 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
4945 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
4946 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
4947 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
4948 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
4949
4950 #define I2C_CR2_ITERREN_Pos (8U)
4951 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
4952 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
4953 #define I2C_CR2_ITEVTEN_Pos (9U)
4954 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
4955 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
4956 #define I2C_CR2_ITBUFEN_Pos (10U)
4957 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
4958 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
4959 #define I2C_CR2_DMAEN_Pos (11U)
4960 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
4961 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
4962 #define I2C_CR2_LAST_Pos (12U)
4963 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
4964 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
4965
4966 /******************* Bit definition for I2C_OAR1 register *******************/
4967 #define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
4968 #define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
4969
4970 #define I2C_OAR1_ADD0_Pos (0U)
4971 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
4972 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
4973 #define I2C_OAR1_ADD1_Pos (1U)
4974 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
4975 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
4976 #define I2C_OAR1_ADD2_Pos (2U)
4977 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
4978 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
4979 #define I2C_OAR1_ADD3_Pos (3U)
4980 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
4981 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
4982 #define I2C_OAR1_ADD4_Pos (4U)
4983 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
4984 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
4985 #define I2C_OAR1_ADD5_Pos (5U)
4986 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
4987 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
4988 #define I2C_OAR1_ADD6_Pos (6U)
4989 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
4990 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
4991 #define I2C_OAR1_ADD7_Pos (7U)
4992 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
4993 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
4994 #define I2C_OAR1_ADD8_Pos (8U)
4995 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
4996 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
4997 #define I2C_OAR1_ADD9_Pos (9U)
4998 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
4999 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
5000
5001 #define I2C_OAR1_ADDMODE_Pos (15U)
5002 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
5003 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
5004
5005 /******************* Bit definition for I2C_OAR2 register *******************/
5006 #define I2C_OAR2_ENDUAL_Pos (0U)
5007 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
5008 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
5009 #define I2C_OAR2_ADD2_Pos (1U)
5010 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
5011 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
5012
5013 /******************** Bit definition for I2C_DR register ********************/
5014 #define I2C_DR_DR_Pos (0U)
5015 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
5016 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
5017
5018 /******************* Bit definition for I2C_SR1 register ********************/
5019 #define I2C_SR1_SB_Pos (0U)
5020 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
5021 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
5022 #define I2C_SR1_ADDR_Pos (1U)
5023 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
5024 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
5025 #define I2C_SR1_BTF_Pos (2U)
5026 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
5027 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
5028 #define I2C_SR1_ADD10_Pos (3U)
5029 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
5030 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
5031 #define I2C_SR1_STOPF_Pos (4U)
5032 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
5033 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
5034 #define I2C_SR1_RXNE_Pos (6U)
5035 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
5036 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
5037 #define I2C_SR1_TXE_Pos (7U)
5038 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
5039 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
5040 #define I2C_SR1_BERR_Pos (8U)
5041 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
5042 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
5043 #define I2C_SR1_ARLO_Pos (9U)
5044 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
5045 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
5046 #define I2C_SR1_AF_Pos (10U)
5047 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
5048 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
5049 #define I2C_SR1_OVR_Pos (11U)
5050 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
5051 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
5052 #define I2C_SR1_PECERR_Pos (12U)
5053 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
5054 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
5055 #define I2C_SR1_TIMEOUT_Pos (14U)
5056 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
5057 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
5058 #define I2C_SR1_SMBALERT_Pos (15U)
5059 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
5060 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
5061
5062 /******************* Bit definition for I2C_SR2 register ********************/
5063 #define I2C_SR2_MSL_Pos (0U)
5064 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
5065 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
5066 #define I2C_SR2_BUSY_Pos (1U)
5067 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
5068 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
5069 #define I2C_SR2_TRA_Pos (2U)
5070 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
5071 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
5072 #define I2C_SR2_GENCALL_Pos (4U)
5073 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
5074 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
5075 #define I2C_SR2_SMBDEFAULT_Pos (5U)
5076 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
5077 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
5078 #define I2C_SR2_SMBHOST_Pos (6U)
5079 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
5080 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
5081 #define I2C_SR2_DUALF_Pos (7U)
5082 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
5083 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
5084 #define I2C_SR2_PEC_Pos (8U)
5085 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
5086 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
5087
5088 /******************* Bit definition for I2C_CCR register ********************/
5089 #define I2C_CCR_CCR_Pos (0U)
5090 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
5091 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
5092 #define I2C_CCR_DUTY_Pos (14U)
5093 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
5094 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
5095 #define I2C_CCR_FS_Pos (15U)
5096 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
5097 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
5098
5099 /****************** Bit definition for I2C_TRISE register *******************/
5100 #define I2C_TRISE_TRISE_Pos (0U)
5101 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
5102 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
5103
5104 /******************************************************************************/
5105 /* */
5106 /* Universal Synchronous Asynchronous Receiver Transmitter */
5107 /* */
5108 /******************************************************************************/
5109
5110 /******************* Bit definition for USART_SR register *******************/
5111 #define USART_SR_PE_Pos (0U)
5112 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
5113 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
5114 #define USART_SR_FE_Pos (1U)
5115 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
5116 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
5117 #define USART_SR_NE_Pos (2U)
5118 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
5119 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
5120 #define USART_SR_ORE_Pos (3U)
5121 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
5122 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
5123 #define USART_SR_IDLE_Pos (4U)
5124 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
5125 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
5126 #define USART_SR_RXNE_Pos (5U)
5127 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
5128 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
5129 #define USART_SR_TC_Pos (6U)
5130 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
5131 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
5132 #define USART_SR_TXE_Pos (7U)
5133 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
5134 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
5135 #define USART_SR_LBD_Pos (8U)
5136 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
5137 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
5138 #define USART_SR_CTS_Pos (9U)
5139 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
5140 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
5141
5142 /******************* Bit definition for USART_DR register *******************/
5143 #define USART_DR_DR_Pos (0U)
5144 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
5145 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
5146
5147 /****************** Bit definition for USART_BRR register *******************/
5148 #define USART_BRR_DIV_Fraction_Pos (0U)
5149 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
5150 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
5151 #define USART_BRR_DIV_Mantissa_Pos (4U)
5152 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
5153 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
5154
5155 /****************** Bit definition for USART_CR1 register *******************/
5156 #define USART_CR1_SBK_Pos (0U)
5157 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
5158 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
5159 #define USART_CR1_RWU_Pos (1U)
5160 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
5161 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
5162 #define USART_CR1_RE_Pos (2U)
5163 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
5164 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
5165 #define USART_CR1_TE_Pos (3U)
5166 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
5167 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
5168 #define USART_CR1_IDLEIE_Pos (4U)
5169 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
5170 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
5171 #define USART_CR1_RXNEIE_Pos (5U)
5172 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
5173 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
5174 #define USART_CR1_TCIE_Pos (6U)
5175 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
5176 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
5177 #define USART_CR1_TXEIE_Pos (7U)
5178 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
5179 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
5180 #define USART_CR1_PEIE_Pos (8U)
5181 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
5182 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
5183 #define USART_CR1_PS_Pos (9U)
5184 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
5185 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
5186 #define USART_CR1_PCE_Pos (10U)
5187 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
5188 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
5189 #define USART_CR1_WAKE_Pos (11U)
5190 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
5191 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
5192 #define USART_CR1_M_Pos (12U)
5193 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
5194 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
5195 #define USART_CR1_UE_Pos (13U)
5196 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
5197 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
5198
5199 /****************** Bit definition for USART_CR2 register *******************/
5200 #define USART_CR2_ADD_Pos (0U)
5201 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
5202 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
5203 #define USART_CR2_LBDL_Pos (5U)
5204 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
5205 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
5206 #define USART_CR2_LBDIE_Pos (6U)
5207 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
5208 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
5209 #define USART_CR2_LBCL_Pos (8U)
5210 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
5211 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
5212 #define USART_CR2_CPHA_Pos (9U)
5213 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
5214 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
5215 #define USART_CR2_CPOL_Pos (10U)
5216 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
5217 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
5218 #define USART_CR2_CLKEN_Pos (11U)
5219 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
5220 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
5221
5222 #define USART_CR2_STOP_Pos (12U)
5223 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
5224 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
5225 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
5226 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
5227
5228 #define USART_CR2_LINEN_Pos (14U)
5229 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
5230 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
5231
5232 /****************** Bit definition for USART_CR3 register *******************/
5233 #define USART_CR3_EIE_Pos (0U)
5234 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
5235 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
5236 #define USART_CR3_IREN_Pos (1U)
5237 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
5238 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
5239 #define USART_CR3_IRLP_Pos (2U)
5240 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
5241 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
5242 #define USART_CR3_HDSEL_Pos (3U)
5243 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
5244 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
5245 #define USART_CR3_NACK_Pos (4U)
5246 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
5247 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
5248 #define USART_CR3_SCEN_Pos (5U)
5249 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
5250 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
5251 #define USART_CR3_DMAR_Pos (6U)
5252 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
5253 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
5254 #define USART_CR3_DMAT_Pos (7U)
5255 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
5256 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
5257 #define USART_CR3_RTSE_Pos (8U)
5258 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
5259 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
5260 #define USART_CR3_CTSE_Pos (9U)
5261 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
5262 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
5263 #define USART_CR3_CTSIE_Pos (10U)
5264 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
5265 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
5266
5267 /****************** Bit definition for USART_GTPR register ******************/
5268 #define USART_GTPR_PSC_Pos (0U)
5269 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
5270 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
5271 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
5272 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
5273 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
5274 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
5275 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
5276 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
5277 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
5278 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
5279
5280 #define USART_GTPR_GT_Pos (8U)
5281 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
5282 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
5283
5284 /******************************************************************************/
5285 /* */
5286 /* Debug MCU */
5287 /* */
5288 /******************************************************************************/
5289
5290 /**************** Bit definition for DBGMCU_IDCODE register *****************/
5291 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
5292 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
5293 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
5294
5295 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
5296 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
5297 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
5298 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
5299 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
5300 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
5301 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
5302 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
5303 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
5304 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
5305 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
5306 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
5307 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
5308 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
5309 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
5310 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
5311 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
5312 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
5313 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
5314
5315 /****************** Bit definition for DBGMCU_CR register *******************/
5316 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
5317 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
5318 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
5319 #define DBGMCU_CR_DBG_STOP_Pos (1U)
5320 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
5321 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
5322 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
5323 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
5324 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
5325 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
5326 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
5327 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
5328
5329 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
5330 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
5331 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
5332 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
5333 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
5334
5335 #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
5336 #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
5337 #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
5338 #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
5339 #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
5340 #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
5341 #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
5342 #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
5343 #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
5344 #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
5345 #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
5346 #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
5347 #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
5348 #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
5349 #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
5350 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
5351 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
5352 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
5353 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
5354 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
5355 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
5356
5357 /******************************************************************************/
5358 /* */
5359 /* FLASH and Option Bytes Registers */
5360 /* */
5361 /******************************************************************************/
5362 /******************* Bit definition for FLASH_ACR register ******************/
5363 #define FLASH_ACR_LATENCY_Pos (0U)
5364 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
5365 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
5366 #define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
5367 #define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
5368 #define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
5369
5370 #define FLASH_ACR_HLFCYA_Pos (3U)
5371 #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
5372 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
5373 #define FLASH_ACR_PRFTBE_Pos (4U)
5374 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
5375 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
5376 #define FLASH_ACR_PRFTBS_Pos (5U)
5377 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
5378 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
5379
5380 /****************** Bit definition for FLASH_KEYR register ******************/
5381 #define FLASH_KEYR_FKEYR_Pos (0U)
5382 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
5383 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
5384
5385 #define RDP_KEY_Pos (0U)
5386 #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
5387 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
5388 #define FLASH_KEY1_Pos (0U)
5389 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
5390 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
5391 #define FLASH_KEY2_Pos (0U)
5392 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
5393 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
5394
5395 /***************** Bit definition for FLASH_OPTKEYR register ****************/
5396 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
5397 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
5398 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
5399
5400 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
5401 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
5402
5403 /****************** Bit definition for FLASH_SR register ********************/
5404 #define FLASH_SR_BSY_Pos (0U)
5405 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
5406 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
5407 #define FLASH_SR_PGERR_Pos (2U)
5408 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
5409 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
5410 #define FLASH_SR_WRPRTERR_Pos (4U)
5411 #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
5412 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
5413 #define FLASH_SR_EOP_Pos (5U)
5414 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
5415 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
5416
5417 /******************* Bit definition for FLASH_CR register *******************/
5418 #define FLASH_CR_PG_Pos (0U)
5419 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
5420 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
5421 #define FLASH_CR_PER_Pos (1U)
5422 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
5423 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
5424 #define FLASH_CR_MER_Pos (2U)
5425 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
5426 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
5427 #define FLASH_CR_OPTPG_Pos (4U)
5428 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
5429 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
5430 #define FLASH_CR_OPTER_Pos (5U)
5431 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
5432 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
5433 #define FLASH_CR_STRT_Pos (6U)
5434 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
5435 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
5436 #define FLASH_CR_LOCK_Pos (7U)
5437 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
5438 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
5439 #define FLASH_CR_OPTWRE_Pos (9U)
5440 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
5441 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
5442 #define FLASH_CR_ERRIE_Pos (10U)
5443 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
5444 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
5445 #define FLASH_CR_EOPIE_Pos (12U)
5446 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
5447 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
5448
5449 /******************* Bit definition for FLASH_AR register *******************/
5450 #define FLASH_AR_FAR_Pos (0U)
5451 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
5452 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
5453
5454 /****************** Bit definition for FLASH_OBR register *******************/
5455 #define FLASH_OBR_OPTERR_Pos (0U)
5456 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
5457 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
5458 #define FLASH_OBR_RDPRT_Pos (1U)
5459 #define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
5460 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
5461
5462 #define FLASH_OBR_IWDG_SW_Pos (2U)
5463 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
5464 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
5465 #define FLASH_OBR_nRST_STOP_Pos (3U)
5466 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
5467 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
5468 #define FLASH_OBR_nRST_STDBY_Pos (4U)
5469 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
5470 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
5471 #define FLASH_OBR_USER_Pos (2U)
5472 #define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
5473 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
5474 #define FLASH_OBR_DATA0_Pos (10U)
5475 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
5476 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
5477 #define FLASH_OBR_DATA1_Pos (18U)
5478 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
5479 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
5480
5481 /****************** Bit definition for FLASH_WRPR register ******************/
5482 #define FLASH_WRPR_WRP_Pos (0U)
5483 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
5484 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
5485
5486 /*----------------------------------------------------------------------------*/
5487
5488 /****************** Bit definition for FLASH_RDP register *******************/
5489 #define FLASH_RDP_RDP_Pos (0U)
5490 #define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
5491 #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
5492 #define FLASH_RDP_nRDP_Pos (8U)
5493 #define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
5494 #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
5495
5496 /****************** Bit definition for FLASH_USER register ******************/
5497 #define FLASH_USER_USER_Pos (16U)
5498 #define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
5499 #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
5500 #define FLASH_USER_nUSER_Pos (24U)
5501 #define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
5502 #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
5503
5504 /****************** Bit definition for FLASH_Data0 register *****************/
5505 #define FLASH_DATA0_DATA0_Pos (0U)
5506 #define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
5507 #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
5508 #define FLASH_DATA0_nDATA0_Pos (8U)
5509 #define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
5510 #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
5511
5512 /****************** Bit definition for FLASH_Data1 register *****************/
5513 #define FLASH_DATA1_DATA1_Pos (16U)
5514 #define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
5515 #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
5516 #define FLASH_DATA1_nDATA1_Pos (24U)
5517 #define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
5518 #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
5519
5520 /****************** Bit definition for FLASH_WRP0 register ******************/
5521 #define FLASH_WRP0_WRP0_Pos (0U)
5522 #define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
5523 #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
5524 #define FLASH_WRP0_nWRP0_Pos (8U)
5525 #define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
5526 #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
5527
5528 /****************** Bit definition for FLASH_WRP1 register ******************/
5529 #define FLASH_WRP1_WRP1_Pos (16U)
5530 #define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
5531 #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
5532 #define FLASH_WRP1_nWRP1_Pos (24U)
5533 #define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
5534 #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
5535
5536 /****************** Bit definition for FLASH_WRP2 register ******************/
5537 #define FLASH_WRP2_WRP2_Pos (0U)
5538 #define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
5539 #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
5540 #define FLASH_WRP2_nWRP2_Pos (8U)
5541 #define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
5542 #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
5543
5544 /****************** Bit definition for FLASH_WRP3 register ******************/
5545 #define FLASH_WRP3_WRP3_Pos (16U)
5546 #define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
5547 #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
5548 #define FLASH_WRP3_nWRP3_Pos (24U)
5549 #define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
5550 #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
5551
5552
5553
5554 /**
5555 * @}
5556 */
5557
5558 /**
5559 * @}
5560 */
5561
5562 /** @addtogroup Exported_macro
5563 * @{
5564 */
5565
5566 /****************************** ADC Instances *********************************/
5567 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
5568
5569 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
5570
5571 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
5572
5573 /****************************** CRC Instances *********************************/
5574 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
5575
5576 /****************************** DAC Instances *********************************/
5577
5578 /****************************** DMA Instances *********************************/
5579 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
5580 ((INSTANCE) == DMA1_Channel2) || \
5581 ((INSTANCE) == DMA1_Channel3) || \
5582 ((INSTANCE) == DMA1_Channel4) || \
5583 ((INSTANCE) == DMA1_Channel5) || \
5584 ((INSTANCE) == DMA1_Channel6) || \
5585 ((INSTANCE) == DMA1_Channel7))
5586
5587 /******************************* GPIO Instances *******************************/
5588 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5589 ((INSTANCE) == GPIOB) || \
5590 ((INSTANCE) == GPIOC) || \
5591 ((INSTANCE) == GPIOD) || \
5592 ((INSTANCE) == GPIOE))
5593
5594 /**************************** GPIO Alternate Function Instances ***************/
5595 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
5596
5597 /**************************** GPIO Lock Instances *****************************/
5598 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
5599
5600 /******************************** I2C Instances *******************************/
5601 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
5602 ((INSTANCE) == I2C2))
5603
5604 /******************************* SMBUS Instances ******************************/
5605 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
5606
5607 /****************************** IWDG Instances ********************************/
5608 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
5609
5610 /******************************** SPI Instances *******************************/
5611 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
5612 ((INSTANCE) == SPI2))
5613
5614 /****************************** START TIM Instances ***************************/
5615 /****************************** TIM Instances *********************************/
5616 #define IS_TIM_INSTANCE(INSTANCE)\
5617 (((INSTANCE) == TIM2) || \
5618 ((INSTANCE) == TIM3) || \
5619 ((INSTANCE) == TIM4))
5620
5621 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) 0U
5622
5623 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
5624 (((INSTANCE) == TIM2) || \
5625 ((INSTANCE) == TIM3) || \
5626 ((INSTANCE) == TIM4))
5627
5628 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
5629 (((INSTANCE) == TIM2) || \
5630 ((INSTANCE) == TIM3) || \
5631 ((INSTANCE) == TIM4))
5632
5633 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
5634 (((INSTANCE) == TIM2) || \
5635 ((INSTANCE) == TIM3) || \
5636 ((INSTANCE) == TIM4))
5637
5638 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
5639 (((INSTANCE) == TIM2) || \
5640 ((INSTANCE) == TIM3) || \
5641 ((INSTANCE) == TIM4))
5642
5643 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
5644 (((INSTANCE) == TIM2) || \
5645 ((INSTANCE) == TIM3) || \
5646 ((INSTANCE) == TIM4))
5647
5648 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
5649 (((INSTANCE) == TIM2) || \
5650 ((INSTANCE) == TIM3) || \
5651 ((INSTANCE) == TIM4))
5652
5653 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
5654 (((INSTANCE) == TIM2) || \
5655 ((INSTANCE) == TIM3) || \
5656 ((INSTANCE) == TIM4))
5657
5658 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
5659 (((INSTANCE) == TIM2) || \
5660 ((INSTANCE) == TIM3) || \
5661 ((INSTANCE) == TIM4))
5662
5663 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
5664 (((INSTANCE) == TIM2) || \
5665 ((INSTANCE) == TIM3) || \
5666 ((INSTANCE) == TIM4))
5667
5668 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
5669 (((INSTANCE) == TIM2) || \
5670 ((INSTANCE) == TIM3) || \
5671 ((INSTANCE) == TIM4))
5672
5673 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
5674 (((INSTANCE) == TIM2) || \
5675 ((INSTANCE) == TIM3) || \
5676 ((INSTANCE) == TIM4))
5677
5678 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
5679 (((INSTANCE) == TIM2) || \
5680 ((INSTANCE) == TIM3) || \
5681 ((INSTANCE) == TIM4))
5682
5683 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
5684 (((INSTANCE) == TIM2) || \
5685 ((INSTANCE) == TIM3) || \
5686 ((INSTANCE) == TIM4))
5687
5688 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
5689 (((INSTANCE) == TIM2) || \
5690 ((INSTANCE) == TIM3) || \
5691 ((INSTANCE) == TIM4))
5692
5693 #define IS_TIM_BREAK_INSTANCE(INSTANCE) 0U
5694
5695 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
5696 ((((INSTANCE) == TIM2) && \
5697 (((CHANNEL) == TIM_CHANNEL_1) || \
5698 ((CHANNEL) == TIM_CHANNEL_2) || \
5699 ((CHANNEL) == TIM_CHANNEL_3) || \
5700 ((CHANNEL) == TIM_CHANNEL_4))) \
5701 || \
5702 (((INSTANCE) == TIM3) && \
5703 (((CHANNEL) == TIM_CHANNEL_1) || \
5704 ((CHANNEL) == TIM_CHANNEL_2) || \
5705 ((CHANNEL) == TIM_CHANNEL_3) || \
5706 ((CHANNEL) == TIM_CHANNEL_4))) \
5707 || \
5708 (((INSTANCE) == TIM4) && \
5709 (((CHANNEL) == TIM_CHANNEL_1) || \
5710 ((CHANNEL) == TIM_CHANNEL_2) || \
5711 ((CHANNEL) == TIM_CHANNEL_3) || \
5712 ((CHANNEL) == TIM_CHANNEL_4))))
5713
5714 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) 0U
5715
5716 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
5717 (((INSTANCE) == TIM2) || \
5718 ((INSTANCE) == TIM3) || \
5719 ((INSTANCE) == TIM4))
5720
5721 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) 0U
5722
5723 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
5724 (((INSTANCE) == TIM2) || \
5725 ((INSTANCE) == TIM3) || \
5726 ((INSTANCE) == TIM4))
5727
5728 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
5729 (((INSTANCE) == TIM2) || \
5730 ((INSTANCE) == TIM3) || \
5731 ((INSTANCE) == TIM4))
5732
5733 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
5734 (((INSTANCE) == TIM2) || \
5735 ((INSTANCE) == TIM3) || \
5736 ((INSTANCE) == TIM4))
5737
5738 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) 0U
5739
5740 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5741 ((INSTANCE) == TIM3) || \
5742 ((INSTANCE) == TIM4))
5743
5744 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5745 ((INSTANCE) == TIM3) || \
5746 ((INSTANCE) == TIM4))
5747
5748 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
5749
5750 /****************************** END TIM Instances *****************************/
5751
5752
5753 /******************** USART Instances : Synchronous mode **********************/
5754 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5755 ((INSTANCE) == USART2) || \
5756 ((INSTANCE) == USART3))
5757
5758 /******************** UART Instances : Asynchronous mode **********************/
5759 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5760 ((INSTANCE) == USART2) || \
5761 ((INSTANCE) == USART3))
5762
5763 /******************** UART Instances : Half-Duplex mode **********************/
5764 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5765 ((INSTANCE) == USART2) || \
5766 ((INSTANCE) == USART3))
5767
5768 /******************** UART Instances : LIN mode **********************/
5769 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5770 ((INSTANCE) == USART2) || \
5771 ((INSTANCE) == USART3))
5772
5773 /****************** UART Instances : Hardware Flow control ********************/
5774 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5775 ((INSTANCE) == USART2) || \
5776 ((INSTANCE) == USART3))
5777
5778 /********************* UART Instances : Smard card mode ***********************/
5779 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5780 ((INSTANCE) == USART2) || \
5781 ((INSTANCE) == USART3))
5782
5783 /*********************** UART Instances : IRDA mode ***************************/
5784 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5785 ((INSTANCE) == USART2) || \
5786 ((INSTANCE) == USART3))
5787
5788 /***************** UART Instances : Multi-Processor mode **********************/
5789 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5790 ((INSTANCE) == USART2) || \
5791 ((INSTANCE) == USART3))
5792
5793 /***************** UART Instances : DMA mode available **********************/
5794 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5795 ((INSTANCE) == USART2) || \
5796 ((INSTANCE) == USART3))
5797
5798 /****************************** RTC Instances *********************************/
5799 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
5800
5801 /**************************** WWDG Instances *****************************/
5802 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
5803
5804
5805
5806
5807 #define RCC_HSE_MIN 4000000U
5808 #define RCC_HSE_MAX 16000000U
5809
5810 #define RCC_MAX_FREQUENCY 72000000U
5811
5812 /**
5813 * @}
5814 */
5815 /******************************************************************************/
5816 /* For a painless codes migration between the STM32F1xx device product */
5817 /* lines, the aliases defined below are put in place to overcome the */
5818 /* differences in the interrupt handlers and IRQn definitions. */
5819 /* No need to update developed interrupt code when moving across */
5820 /* product lines within the same STM32F1 Family */
5821 /******************************************************************************/
5822
5823 /* Aliases for __IRQn */
5824 #define ADC1_2_IRQn ADC1_IRQn
5825
5826
5827 /* Aliases for __IRQHandler */
5828 #define ADC1_2_IRQHandler ADC1_IRQHandler
5829
5830
5831 /**
5832 * @}
5833 */
5834
5835 /**
5836 * @}
5837 */
5838
5839
5840 #ifdef __cplusplus
5841 }
5842 #endif /* __cplusplus */
5843
5844 #endif /* __STM32F101xB_H */
5845
5846
5847
5848 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/