lib/main/STM32F1/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c

   1 /* ----------------------------------------------------------------------
   2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
   3 *
   4 * $Date:        19. March 2015
   5 * $Revision:    V.1.4.5
   6 *
   7 * Project:          CMSIS DSP Library
   8 * Title:                arm_power_q31.c
   9 *
  10 * Description:  Sum of the squares of the elements of a Q31 vector.
  11 *
  12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13 *
  14 * Redistribution and use in source and binary forms, with or without
  15 * modification, are permitted provided that the following conditions
  16 * are met:
  17 *   - Redistributions of source code must retain the above copyright
  18 *     notice, this list of conditions and the following disclaimer.
  19 *   - Redistributions in binary form must reproduce the above copyright
  20 *     notice, this list of conditions and the following disclaimer in
  21 *     the documentation and/or other materials provided with the
  22 *     distribution.
  23 *   - Neither the name of ARM LIMITED nor the names of its contributors
  24 *     may be used to endorse or promote products derived from this
  25 *     software without specific prior written permission.
  26 *
  27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38 * POSSIBILITY OF SUCH DAMAGE.
  39 * -------------------------------------------------------------------- */
  40
  41 #include "arm_math.h"
  42
  43 /**
  44  * @ingroup groupStats
  45  */
  46
  47 /**
  48  * @addtogroup power
  49  * @{
  50  */
  51
  52 /**
  53  * @brief Sum of the squares of the elements of a Q31 vector.
  54  * @param[in]       *pSrc points to the input vector
  55  * @param[in]       blockSize length of the input vector
  56  * @param[out]      *pResult sum of the squares value returned here
  57  * @return none.
  58  *
  59  * @details
  60  * <b>Scaling and Overflow Behavior:</b>
  61  *
  62  * \par
  63  * The function is implemented using a 64-bit internal accumulator.
  64  * The input is represented in 1.31 format.
  65  * Intermediate multiplication yields a 2.62 format, and this
  66  * result is truncated to 2.48 format by discarding the lower 14 bits.
  67  * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
  68  * With 15 guard bits in the accumulator, there is no risk of overflow, and the
  69  * full precision of the intermediate multiplication is preserved.
  70  * Finally, the return result is in 16.48 format.
  71  *
  72  */
  73
  74 void arm_power_q31(
  75   q31_t * pSrc,
  76   uint32_t blockSize,
  77   q63_t * pResult)
  78 {
  79   q63_t sum = 0;                                 /* Temporary result storage */
  80   q31_t in;
  81   uint32_t blkCnt;                               /* loop counter */
  82
  83
  84 #ifndef ARM_MATH_CM0_FAMILY
  85
  86   /* Run the below code for Cortex-M4 and Cortex-M3 */
  87
  88   /*loop Unrolling */
  89   blkCnt = blockSize >> 2u;
  90
  91   /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
  92    ** a second loop below computes the remaining 1 to 3 samples. */
  93   while(blkCnt > 0u)
  94   {
  95     /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
  96     /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
  97     in = *pSrc++;
  98     sum += ((q63_t) in * in) >> 14u;
  99
 100     in = *pSrc++;
 101     sum += ((q63_t) in * in) >> 14u;
 102
 103     in = *pSrc++;
 104     sum += ((q63_t) in * in) >> 14u;
 105
 106     in = *pSrc++;
 107     sum += ((q63_t) in * in) >> 14u;
 108
 109     /* Decrement the loop counter */
 110     blkCnt--;
 111   }
 112
 113   /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
 114    ** No loop unrolling is used. */
 115   blkCnt = blockSize % 0x4u;
 116
 117 #else
 118
 119   /* Run the below code for Cortex-M0 */
 120
 121   /* Loop over blockSize number of values */
 122   blkCnt = blockSize;
 123
 124 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
 125
 126   while(blkCnt > 0u)
 127   {
 128     /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
 129     /* Compute Power and then store the result in a temporary variable, sum. */
 130     in = *pSrc++;
 131     sum += ((q63_t) in * in) >> 14u;
 132
 133     /* Decrement the loop counter */
 134     blkCnt--;
 135   }
 136
 137   /* Store the results in 16.48 format  */
 138   *pResult = sum;
 139 }
 140
 141 /**
 142  * @} end of power group
 143  */