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Remove overshoot in warning suppression introduced in #8713.
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_spi.h
blob918907c66897cb232e33f54c9f1e758a7f331951
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_SPI_H
22 #define STM32H7xx_LL_SPI_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
36
37 /** @defgroup SPI_LL SPI
38 * @{
39 */
40
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
48 * @{
49 */
50
51 /**
52 * @brief SPI Init structures definition
53 */
54 typedef struct
55 {
56 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
57 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
58
59 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
60
61 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
62 This parameter can be a value of @ref SPI_LL_EC_MODE.
63
64 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
65
66 uint32_t DataWidth; /*!< Specifies the SPI data width.
67 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
68
69 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
70
71 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
72 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
73
74 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
75
76 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
77 This parameter can be a value of @ref SPI_LL_EC_PHASE.
78
79 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
80
81 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
82 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
83
84 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
85
86 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
87 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
88 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
89
90 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
91
92 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
93 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
94
95 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
96
97 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
98 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
99
100 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
101
102 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
103 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFFFFF.
104
105 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
106
107 } LL_SPI_InitTypeDef;
108
109 /**
110 * @}
111 */
112 #endif /*USE_FULL_LL_DRIVER*/
113
114 /* Exported types ------------------------------------------------------------*/
115
116 /* Exported constants --------------------------------------------------------*/
117 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
118 * @{
119 */
120
121 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
122 * @brief Flags defines which can be used with LL_SPI_ReadReg function
123 * @{
124 */
125 #define LL_SPI_SR_RXP (SPI_SR_RXP)
126 #define LL_SPI_SR_TXP (SPI_SR_TXP)
127 #define LL_SPI_SR_DXP (SPI_SR_DXP)
128 #define LL_SPI_SR_EOT (SPI_SR_EOT)
129 #define LL_SPI_SR_TXTF (SPI_SR_TXTF)
130 #define LL_SPI_SR_UDR (SPI_SR_UDR)
131 #define LL_SPI_SR_CRCERR (SPI_SR_CRCERR)
132 #define LL_SPI_SR_MODF (SPI_SR_MODF)
133 #define LL_SPI_SR_OVR (SPI_SR_OVR)
134 #define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
135 #define LL_SPI_SR_TSERF (SPI_SR_TSERF)
136 #define LL_SPI_SR_SUSP (SPI_SR_SUSP)
137 #define LL_SPI_SR_TXC (SPI_SR_TXC)
138 #define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
139 /**
140 * @}
141 */
142
143 /** @defgroup SPI_LL_EC_IT IT Defines
144 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
145 * @{
146 */
147 #define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
148 #define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
149 #define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
150 #define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
151 #define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
152 #define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
153 #define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
154 #define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
155 #define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
156 #define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
157 #define LL_SPI_IER_TSERFIE (SPI_IER_TSERFIE)
158 /**
159 * @}
160 */
161
162 /** @defgroup SPI_LL_EC_MODE Mode
163 * @{
164 */
165 #define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
166 #define LL_SPI_MODE_SLAVE (0x00000000UL)
167 /**
168 * @}
169 */
170
171 /** @defgroup SPI_LL_EC_SS_LEVEL SS Level
172 * @{
173 */
174 #define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
175 #define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
176 /**
177 * @}
178 */
179
180 /** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
181 * @{
182 */
183 #define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
184 #define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
185 #define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
186 #define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
187 #define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
188 #define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
189 #define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
190 #define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
191 #define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
192 #define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
193 #define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
194 #define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
195 #define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
196 #define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
197 #define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
198 #define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
199 /**
200 * @}
201 */
202
203 /** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
204 * @{
205 */
206 #define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
207 #define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
208 #define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
209 #define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
210 #define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
211 #define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
212 #define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
213 #define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
214 #define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
215 #define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
216 #define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
217 #define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
218 #define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
219 #define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
220 #define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
221 #define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
222 /**
223 * @}
224 */
225
226 /** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
227 * @{
228 */
229 #define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
230 #define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
231 /**
232 * @}
233 */
234
235 /** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
236 * @{
237 */
238 #define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
239 #define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
240 /**
241 * @}
242 */
243
244 /** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
245 * @{
246 */
247 #define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
248 #define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG_0)
249 #define LL_SPI_UDR_CONFIG_LAST_TRANSMITTED (SPI_CFG1_UDRCFG_1)
250 /**
251 * @}
252 */
253
254 /** @defgroup SPI_LL_EC_UDR_DETECT_BEGIN_DATA UDR Detect Begin Data
255 * @{
256 */
257 #define LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
258 #define LL_SPI_UDR_DETECT_END_DATA_FRAME (SPI_CFG1_UDRDET_0)
259 #define LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS (SPI_CFG1_UDRDET_1)
260 /**
261 * @}
262 */
263
264 /** @defgroup SPI_LL_EC_PROTOCOL Protocol
265 * @{
266 */
267 #define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
268 #define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
269 /**
270 * @}
271 */
272
273 /** @defgroup SPI_LL_EC_PHASE Phase
274 * @{
275 */
276 #define LL_SPI_PHASE_1EDGE (0x00000000UL)
277 #define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
278 /**
279 * @}
280 */
281
282 /** @defgroup SPI_LL_EC_POLARITY Polarity
283 * @{
284 */
285 #define LL_SPI_POLARITY_LOW (0x00000000UL)
286 #define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
287 /**
288 * @}
289 */
290
291 /** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
292 * @{
293 */
294 #define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
295 #define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
296 /**
297 * @}
298 */
299
300 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
301 * @{
302 */
303 #define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
304 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
305 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
306 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
307 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
308 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
309 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
310 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
311 /**
312 * @}
313 */
314
315 /** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
316 * @{
317 */
318 #define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
319 #define LL_SPI_MSB_FIRST (0x00000000UL)
320 /**
321 * @}
322 */
323
324 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
325 * @{
326 */
327 #define LL_SPI_FULL_DUPLEX (0x00000000UL)
328 #define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
329 #define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
330 #define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
331 #define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
332 /**
333 * @}
334 */
335
336 /** @defgroup SPI_LL_EC_DATAWIDTH Data Width
337 * @{
338 */
339 #define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
340 #define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
341 #define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
342 #define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
343 #define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
344 #define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
345 #define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
346 #define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
347 #define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
348 #define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
349 #define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
350 #define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
351 #define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
352 #define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
353 #define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
354 #define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
355 #define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
356 #define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
357 #define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
358 #define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
359 #define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
360 #define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
361 #define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
362 #define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
363 #define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
364 #define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
365 #define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
366 #define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
367 #define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
368 /**
369 * @}
370 */
371
372 /** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
373 * @{
374 */
375 #define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
376 #define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
377 #define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
378 #define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
379 #define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
380 #define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
381 #define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
382 #define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
383 #define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
384 #define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
385 #define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
386 #define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
387 #define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
388 #define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
389 #define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
390 #define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
391 /**
392 * @}
393 */
394
395 #if defined(USE_FULL_LL_DRIVER)
396
397 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
398 * @{
399 */
400 #define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */
401 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */
402 /**
403 * @}
404 */
405 #endif /* USE_FULL_LL_DRIVER */
406
407 /** @defgroup SPI_LL_EC_CRC CRC
408 * @{
409 */
410 #define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
411 #define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
412 #define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
413 #define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
414 #define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
415 #define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
416 #define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
417 #define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
418 #define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
419 #define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
420 #define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
421 #define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
422 #define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
423 #define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
424 #define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
425 #define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
426 #define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
427 #define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
428 #define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
429 #define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
430 #define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
431 #define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
432 #define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
433 #define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
434 #define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
435 #define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
436 #define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
437 #define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
438 #define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
439 /**
440 * @}
441 */
442
443 /** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
444 * @{
445 */
446 #define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
447 #define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
448 #define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
449 /**
450 * @}
451 */
452
453 /** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
454 * @{
455 */
456 #define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
457 #define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
458 #define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
459 #define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
460 /**
461 * @}
462 */
463
464 /**
465 * @}
466 */
467
468 /* Exported macro ------------------------------------------------------------*/
469 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
470 * @{
471 */
472
473 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
474 * @{
475 */
476
477 /**
478 * @brief Write a value in SPI register
479 * @param __INSTANCE__ SPI Instance
480 * @param __REG__ Register to be written
481 * @param __VALUE__ Value to be written in the register
482 * @retval None
483 */
484 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
485
486 /**
487 * @brief Read a value in SPI register
488 * @param __INSTANCE__ SPI Instance
489 * @param __REG__ Register to be read
490 * @retval Register value
491 */
492 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
493 /**
494 * @}
495 */
496
497 /**
498 * @}
499 */
500
501
502 /* Exported functions --------------------------------------------------------*/
503
504 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
505 * @{
506 */
507
508 /** @defgroup SPI_LL_EF_Configuration Configuration
509 * @{
510 */
511
512 /**
513 * @brief Enable SPI peripheral
514 * @rmtoll CR1 SPE LL_SPI_Enable
515 * @param SPIx SPI Instance
516 * @retval None
517 */
518 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
519 {
520 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
521 }
522
523 /**
524 * @brief Disable SPI peripheral
525 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
526 * @rmtoll CR1 SPE LL_SPI_Disable
527 * @param SPIx SPI Instance
528 * @retval None
529 */
530 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
531 {
532 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
533 }
534
535 /**
536 * @brief Check if SPI peripheral is enabled
537 * @rmtoll CR1 SPE LL_SPI_IsEnabled
538 * @param SPIx SPI Instance
539 * @retval State of bit (1 or 0)
540 */
541 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
542 {
543 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
544 }
545
546 /**
547 * @brief Swap the MOSI and MISO pin
548 * @note This configuration can not be changed when SPI is enabled.
549 * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap
550 * @param SPIx SPI Instance
551 * @retval None
552 */
553 __STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
554 {
555 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
556 }
557
558 /**
559 * @brief Restore default function for MOSI and MISO pin
560 * @note This configuration can not be changed when SPI is enabled.
561 * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap
562 * @param SPIx SPI Instance
563 * @retval None
564 */
565 __STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
566 {
567 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
568 }
569
570 /**
571 * @brief Check if MOSI and MISO pin are swapped
572 * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap
573 * @param SPIx SPI Instance
574 * @retval State of bit (1 or 0)
575 */
576 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)
577 {
578 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
579 }
580
581 /**
582 * @brief Enable GPIO control
583 * @note This configuration can not be changed when SPI is enabled.
584 * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl
585 * @param SPIx SPI Instance
586 * @retval None
587 */
588 __STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
589 {
590 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
591 }
592
593 /**
594 * @brief Disable GPIO control
595 * @note This configuration can not be changed when SPI is enabled.
596 * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl
597 * @param SPIx SPI Instance
598 * @retval None
599 */
600 __STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
601 {
602 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
603 }
604
605 /**
606 * @brief Check if GPIO control is active
607 * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
608 * @param SPIx SPI Instance
609 * @retval State of bit (1 or 0)
610 */
611 __STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
612 {
613 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
614 }
615
616 /**
617 * @brief Set SPI Mode to Master or Slave
618 * @note This configuration can not be changed when SPI is enabled.
619 * @rmtoll CFG2 MASTER LL_SPI_SetMode
620 * @param SPIx SPI Instance
621 * @param Mode This parameter can be one of the following values:
622 * @arg @ref LL_SPI_MODE_MASTER
623 * @arg @ref LL_SPI_MODE_SLAVE
624 * @retval None
625 */
626 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
627 {
628 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
629 }
630
631 /**
632 * @brief Get SPI Mode (Master or Slave)
633 * @rmtoll CFG2 MASTER LL_SPI_GetMode
634 * @param SPIx SPI Instance
635 * @retval Returned value can be one of the following values:
636 * @arg @ref LL_SPI_MODE_MASTER
637 * @arg @ref LL_SPI_MODE_SLAVE
638 */
639 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
640 {
641 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
642 }
643
644 /**
645 * @brief Configure the Idleness applied by master between active edge of SS and first send data
646 * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness
647 * @param SPIx SPI Instance
648 * @param MasterSSIdleness This parameter can be one of the following values:
649 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
650 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
651 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
652 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
653 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
654 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
655 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
656 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
657 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
658 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
659 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
660 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
661 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
662 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
663 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
664 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
665 * @retval None
666 */
667 __STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
668 {
669 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
670 }
671
672 /**
673 * @brief Get the configured Idleness applied by master
674 * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness
675 * @param SPIx SPI Instance
676 * @retval Returned value can be one of the following values:
677 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
678 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
679 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
680 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
681 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
682 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
683 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
684 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
685 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
686 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
687 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
688 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
689 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
690 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
691 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
692 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
693 */
694 __STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)
695 {
696 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
697 }
698
699 /**
700 * @brief Configure the idleness applied by master between data frame
701 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
702 * @param SPIx SPI Instance
703 * @param MasterInterDataIdleness This parameter can be one of the following values:
704 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
705 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
706 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
707 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
708 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
709 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
710 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
711 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
712 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
713 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
714 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
715 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
716 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
717 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
718 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
719 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
720 * @retval None
721 */
722 __STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
723 {
724 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
725 }
726
727 /**
728 * @brief Get the configured inter data idleness
729 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
730 * @param SPIx SPI Instance
731 * @retval Returned value can be one of the following values:
732 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
733 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
734 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
735 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
736 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
737 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
738 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
739 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
740 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
741 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
742 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
743 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
744 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
745 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
746 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
747 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
748 */
749 __STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)
750 {
751 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
752 }
753
754 /**
755 * @brief Set transfer size
756 * @note Count is the number of frame to be transferred
757 * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize
758 * @param SPIx SPI Instance
759 * @param Count 0..0xFFFF
760 * @retval None
761 */
762 __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
763 {
764 MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
765 }
766
767 /**
768 * @brief Get transfer size
769 * @note Count is the number of frame to be transferred
770 * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize
771 * @param SPIx SPI Instance
772 * @retval 0..0xFFFF
773 */
774 __STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)
775 {
776 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
777 }
778
779 /**
780 * @brief Set reload transfer size
781 * @note Count is the number of frame to be transferred
782 * @rmtoll CR2 TSER LL_SPI_SetReloadSize
783 * @param SPIx SPI Instance
784 * @param Count 0..0xFFFF
785 * @retval None
786 */
787 __STATIC_INLINE void LL_SPI_SetReloadSize(SPI_TypeDef *SPIx, uint32_t Count)
788 {
789 MODIFY_REG(SPIx->CR2, SPI_CR2_TSER, Count << SPI_CR2_TSER_Pos);
790 }
791
792 /**
793 * @brief Get reload transfer size
794 * @note Count is the number of frame to be transferred
795 * @rmtoll CR2 TSER LL_SPI_GetReloadSize
796 * @param SPIx SPI Instance
797 * @retval 0..0xFFFF
798 */
799 __STATIC_INLINE uint32_t LL_SPI_GetReloadSize(SPI_TypeDef *SPIx)
800 {
801 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSER) >> SPI_CR2_TSER_Pos);
802 }
803
804 /**
805 * @brief Lock the AF configuration of associated IOs
806 * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
807 * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
808 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
809 * @param SPIx SPI Instance
810 * @retval None
811 */
812 __STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
813 {
814 SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
815 }
816
817 /**
818 * @brief Check if the AF configuration is locked.
819 * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock
820 * @param SPIx SPI Instance
821 * @retval State of bit (1 or 0)
822 */
823 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
824 {
825 return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
826 }
827
828 /**
829 * @brief Set Tx CRC Initialization Pattern
830 * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
831 * @param SPIx SPI Instance
832 * @param TXCRCInitAll This parameter can be one of the following values:
833 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
834 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
835 * @retval None
836 */
837 __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
838 {
839 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
840 }
841
842 /**
843 * @brief Get Tx CRC Initialization Pattern
844 * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
845 * @param SPIx SPI Instance
846 * @retval Returned value can be one of the following values:
847 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
848 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
849 */
850 __STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)
851 {
852 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
853 }
854
855 /**
856 * @brief Set Rx CRC Initialization Pattern
857 * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
858 * @param SPIx SPI Instance
859 * @param RXCRCInitAll This parameter can be one of the following values:
860 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
861 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
862 * @retval None
863 */
864 __STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
865 {
866 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
867 }
868
869 /**
870 * @brief Get Rx CRC Initialization Pattern
871 * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
872 * @param SPIx SPI Instance
873 * @retval Returned value can be one of the following values:
874 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
875 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
876 */
877 __STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)
878 {
879 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
880 }
881
882 /**
883 * @brief Set internal SS input level ignoring what comes from PIN.
884 * @note This configuration has effect only with config LL_SPI_NSS_SOFT
885 * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel
886 * @param SPIx SPI Instance
887 * @param SSLevel This parameter can be one of the following values:
888 * @arg @ref LL_SPI_SS_LEVEL_HIGH
889 * @arg @ref LL_SPI_SS_LEVEL_LOW
890 * @retval None
891 */
892 __STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
893 {
894 MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
895 }
896
897 /**
898 * @brief Get internal SS input level
899 * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel
900 * @param SPIx SPI Instance
901 * @retval Returned value can be one of the following values:
902 * @arg @ref LL_SPI_SS_LEVEL_HIGH
903 * @arg @ref LL_SPI_SS_LEVEL_LOW
904 */
905 __STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)
906 {
907 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
908 }
909
910 /**
911 * @brief Enable CRC computation on 33/17 bits
912 * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
913 * @param SPIx SPI Instance
914 * @retval None
915 */
916 __STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
917 {
918 SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
919 }
920
921 /**
922 * @brief Disable CRC computation on 33/17 bits
923 * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
924 * @param SPIx SPI Instance
925 * @retval None
926 */
927 __STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
928 {
929 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
930 }
931
932 /**
933 * @brief Check if Enable CRC computation on 33/17 bits is enabled
934 * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
935 * @param SPIx SPI Instance
936 * @retval State of bit (1 or 0)
937 */
938 __STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)
939 {
940 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
941 }
942
943 /**
944 * @brief Suspend an ongoing transfer for Master configuration
945 * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer
946 * @param SPIx SPI Instance
947 * @retval None
948 */
949 __STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
950 {
951 SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
952 }
953
954 /**
955 * @brief Start effective transfer on wire for Master configuration
956 * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
957 * @param SPIx SPI Instance
958 * @retval None
959 */
960 __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
961 {
962 SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
963 }
964
965 /**
966 * @brief Check if there is an unfinished master transfer
967 * @rmtoll CR1 CSTART LL_SPI_IsMasterTransferActive
968 * @param SPIx SPI Instance
969 * @retval State of bit (1 or 0)
970 */
971 __STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)
972 {
973 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
974 }
975
976 /**
977 * @brief Enable Master Rx auto suspend in case of overrun
978 * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
979 * @param SPIx SPI Instance
980 * @retval None
981 */
982 __STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
983 {
984 SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
985 }
986
987 /**
988 * @brief Disable Master Rx auto suspend in case of overrun
989 * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
990 * @param SPIx SPI Instance
991 * @retval None
992 */
993 __STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
994 {
995 CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
996 }
997
998 /**
999 * @brief Check if Master Rx auto suspend is activated
1000 * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
1001 * @param SPIx SPI Instance
1002 * @retval State of bit (1 or 0)
1003 */
1004 __STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1005 {
1006 return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
1007 }
1008
1009 /**
1010 * @brief Set Underrun behavior
1011 * @note This configuration can not be changed when SPI is enabled.
1012 * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration
1013 * @param SPIx SPI Instance
1014 * @param UDRConfig This parameter can be one of the following values:
1015 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1016 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1017 * @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
1018 * @retval None
1019 */
1020 __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
1021 {
1022 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
1023 }
1024
1025 /**
1026 * @brief Get Underrun behavior
1027 * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration
1028 * @param SPIx SPI Instance
1029 * @retval Returned value can be one of the following values:
1030 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1031 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1032 * @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
1033 */
1034 __STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)
1035 {
1036 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
1037 }
1038
1039 /**
1040 * @brief Set Underrun Detection method
1041 * @note This configuration can not be changed when SPI is enabled.
1042 * @rmtoll CFG1 UDRDET LL_SPI_SetUDRDetection
1043 * @param SPIx SPI Instance
1044 * @param UDRDetection This parameter can be one of the following values:
1045 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
1046 * @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
1047 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
1048 * @retval None
1049 */
1050 __STATIC_INLINE void LL_SPI_SetUDRDetection(SPI_TypeDef *SPIx, uint32_t UDRDetection)
1051 {
1052 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRDET, UDRDetection);
1053 }
1054
1055 /**
1056 * @brief Get Underrun Detection method
1057 * @rmtoll CFG1 UDRDET LL_SPI_GetUDRDetection
1058 * @param SPIx SPI Instance
1059 * @retval Returned value can be one of the following values:
1060 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
1061 * @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
1062 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
1063 */
1064 __STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(SPI_TypeDef *SPIx)
1065 {
1066 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET));
1067 }
1068
1069 /**
1070 * @brief Set Serial protocol used
1071 * @note This configuration can not be changed when SPI is enabled.
1072 * @rmtoll CFG2 SP LL_SPI_SetStandard
1073 * @param SPIx SPI Instance
1074 * @param Standard This parameter can be one of the following values:
1075 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1076 * @arg @ref LL_SPI_PROTOCOL_TI
1077 * @retval None
1078 */
1079 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1080 {
1081 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
1082 }
1083
1084 /**
1085 * @brief Get Serial protocol used
1086 * @rmtoll CFG2 SP LL_SPI_GetStandard
1087 * @param SPIx SPI Instance
1088 * @retval Returned value can be one of the following values:
1089 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1090 * @arg @ref LL_SPI_PROTOCOL_TI
1091 */
1092 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
1093 {
1094 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
1095 }
1096
1097 /**
1098 * @brief Set Clock phase
1099 * @note This configuration can not be changed when SPI is enabled.
1100 * This bit is not used in SPI TI mode.
1101 * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase
1102 * @param SPIx SPI Instance
1103 * @param ClockPhase This parameter can be one of the following values:
1104 * @arg @ref LL_SPI_PHASE_1EDGE
1105 * @arg @ref LL_SPI_PHASE_2EDGE
1106 * @retval None
1107 */
1108 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
1109 {
1110 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
1111 }
1112
1113 /**
1114 * @brief Get Clock phase
1115 * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase
1116 * @param SPIx SPI Instance
1117 * @retval Returned value can be one of the following values:
1118 * @arg @ref LL_SPI_PHASE_1EDGE
1119 * @arg @ref LL_SPI_PHASE_2EDGE
1120 */
1121 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
1122 {
1123 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
1124 }
1125
1126 /**
1127 * @brief Set Clock polarity
1128 * @note This configuration can not be changed when SPI is enabled.
1129 * This bit is not used in SPI TI mode.
1130 * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity
1131 * @param SPIx SPI Instance
1132 * @param ClockPolarity This parameter can be one of the following values:
1133 * @arg @ref LL_SPI_POLARITY_LOW
1134 * @arg @ref LL_SPI_POLARITY_HIGH
1135 * @retval None
1136 */
1137 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1138 {
1139 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
1140 }
1141
1142 /**
1143 * @brief Get Clock polarity
1144 * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity
1145 * @param SPIx SPI Instance
1146 * @retval Returned value can be one of the following values:
1147 * @arg @ref LL_SPI_POLARITY_LOW
1148 * @arg @ref LL_SPI_POLARITY_HIGH
1149 */
1150 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
1151 {
1152 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
1153 }
1154
1155 /**
1156 * @brief Set NSS polarity
1157 * @note This configuration can not be changed when SPI is enabled.
1158 * This bit is not used in SPI TI mode.
1159 * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity
1160 * @param SPIx SPI Instance
1161 * @param NSSPolarity This parameter can be one of the following values:
1162 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1163 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1164 * @retval None
1165 */
1166 __STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
1167 {
1168 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
1169 }
1170
1171 /**
1172 * @brief Get NSS polarity
1173 * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity
1174 * @param SPIx SPI Instance
1175 * @retval Returned value can be one of the following values:
1176 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1177 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1178 */
1179 __STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)
1180 {
1181 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
1182 }
1183
1184 /**
1185 * @brief Set Baudrate Prescaler
1186 * @note This configuration can not be changed when SPI is enabled.
1187 * SPI BaudRate = fPCLK/Pescaler.
1188 * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler
1189 * @param SPIx SPI Instance
1190 * @param Baudrate This parameter can be one of the following values:
1191 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1192 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1193 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1194 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1195 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1196 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1197 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1198 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1199 * @retval None
1200 */
1201 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
1202 {
1203 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR, Baudrate);
1204 }
1205
1206 /**
1207 * @brief Get Baudrate Prescaler
1208 * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler
1209 * @param SPIx SPI Instance
1210 * @retval Returned value can be one of the following values:
1211 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1212 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1213 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1214 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1215 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1216 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1217 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1218 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1219 */
1220 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
1221 {
1222 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR));
1223 }
1224
1225 /**
1226 * @brief Set Transfer Bit Order
1227 * @note This configuration can not be changed when SPI is enabled.
1228 * This bit is not used in SPI TI mode.
1229 * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder
1230 * @param SPIx SPI Instance
1231 * @param BitOrder This parameter can be one of the following values:
1232 * @arg @ref LL_SPI_LSB_FIRST
1233 * @arg @ref LL_SPI_MSB_FIRST
1234 * @retval None
1235 */
1236 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
1237 {
1238 MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
1239 }
1240
1241 /**
1242 * @brief Get Transfer Bit Order
1243 * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder
1244 * @param SPIx SPI Instance
1245 * @retval Returned value can be one of the following values:
1246 * @arg @ref LL_SPI_LSB_FIRST
1247 * @arg @ref LL_SPI_MSB_FIRST
1248 */
1249 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
1250 {
1251 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
1252 }
1253
1254 /**
1255 * @brief Set Transfer Mode
1256 * @note This configuration can not be changed when SPI is enabled except for half duplex direction using LL_SPI_SetHalfDuplexDirection.
1257 * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
1258 * CFG2 COMM LL_SPI_SetTransferDirection
1259 * @param SPIx SPI Instance
1260 * @param TransferDirection This parameter can be one of the following values:
1261 * @arg @ref LL_SPI_FULL_DUPLEX
1262 * @arg @ref LL_SPI_SIMPLEX_TX
1263 * @arg @ref LL_SPI_SIMPLEX_RX
1264 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1265 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1266 * @retval None
1267 */
1268 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
1269 {
1270 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
1271 MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
1272 }
1273
1274 /**
1275 * @brief Get Transfer Mode
1276 * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n
1277 * CFG2 COMM LL_SPI_GetTransferDirection
1278 * @param SPIx SPI Instance
1279 * @retval Returned value can be one of the following values:
1280 * @arg @ref LL_SPI_FULL_DUPLEX
1281 * @arg @ref LL_SPI_SIMPLEX_TX
1282 * @arg @ref LL_SPI_SIMPLEX_RX
1283 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1284 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1285 */
1286 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
1287 {
1288 register uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
1289 register uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
1290 return (Hddir | Comm);
1291 }
1292
1293 /**
1294 * @brief Set direction for Half-Duplex Mode
1295 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1296 * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection
1297 * @param SPIx SPI Instance
1298 * @param HalfDuplexDirection This parameter can be one of the following values:
1299 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1300 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1301 * @retval None
1302 */
1303 __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
1304 {
1305 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
1306 }
1307
1308 /**
1309 * @brief Get direction for Half-Duplex Mode
1310 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1311 * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection
1312 * @param SPIx SPI Instance
1313 * @retval Returned value can be one of the following values:
1314 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1315 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1316 */
1317 __STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
1318 {
1319 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
1320 }
1321
1322 /**
1323 * @brief Set Frame Data Size
1324 * @note This configuration can not be changed when SPI is enabled.
1325 * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth
1326 * @param SPIx SPI Instance
1327 * @param DataWidth This parameter can be one of the following values:
1328 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1329 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1330 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1331 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1332 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1333 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1334 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1335 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1336 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1337 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1338 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1339 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1340 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1341 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1342 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1343 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1344 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1345 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1346 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1347 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1348 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1349 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1350 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1351 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1352 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1353 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1354 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1355 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1356 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1357 * @retval None
1358 */
1359 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
1360 {
1361 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
1362 }
1363
1364 /**
1365 * @brief Get Frame Data Size
1366 * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth
1367 * @param SPIx SPI Instance
1368 * @retval Returned value can be one of the following values:
1369 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1370 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1371 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1372 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1373 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1374 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1375 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1376 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1377 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1378 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1379 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1380 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1381 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1382 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1383 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1384 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1385 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1386 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1387 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1388 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1389 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1390 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1391 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1392 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1393 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1394 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1395 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1396 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1397 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1398 */
1399 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
1400 {
1401 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
1402 }
1403
1404 /**
1405 * @brief Set threshold of FIFO that triggers a transfer event
1406 * @note This configuration can not be changed when SPI is enabled.
1407 * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold
1408 * @param SPIx SPI Instance
1409 * @param Threshold This parameter can be one of the following values:
1410 * @arg @ref LL_SPI_FIFO_TH_01DATA
1411 * @arg @ref LL_SPI_FIFO_TH_02DATA
1412 * @arg @ref LL_SPI_FIFO_TH_03DATA
1413 * @arg @ref LL_SPI_FIFO_TH_04DATA
1414 * @arg @ref LL_SPI_FIFO_TH_05DATA
1415 * @arg @ref LL_SPI_FIFO_TH_06DATA
1416 * @arg @ref LL_SPI_FIFO_TH_07DATA
1417 * @arg @ref LL_SPI_FIFO_TH_08DATA
1418 * @arg @ref LL_SPI_FIFO_TH_09DATA
1419 * @arg @ref LL_SPI_FIFO_TH_10DATA
1420 * @arg @ref LL_SPI_FIFO_TH_11DATA
1421 * @arg @ref LL_SPI_FIFO_TH_12DATA
1422 * @arg @ref LL_SPI_FIFO_TH_13DATA
1423 * @arg @ref LL_SPI_FIFO_TH_14DATA
1424 * @arg @ref LL_SPI_FIFO_TH_15DATA
1425 * @arg @ref LL_SPI_FIFO_TH_16DATA
1426 * @retval None
1427 */
1428 __STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
1429 {
1430 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
1431 }
1432
1433 /**
1434 * @brief Get threshold of FIFO that triggers a transfer event
1435 * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold
1436 * @param SPIx SPI Instance
1437 * @retval Returned value can be one of the following values:
1438 * @arg @ref LL_SPI_FIFO_TH_01DATA
1439 * @arg @ref LL_SPI_FIFO_TH_02DATA
1440 * @arg @ref LL_SPI_FIFO_TH_03DATA
1441 * @arg @ref LL_SPI_FIFO_TH_04DATA
1442 * @arg @ref LL_SPI_FIFO_TH_05DATA
1443 * @arg @ref LL_SPI_FIFO_TH_06DATA
1444 * @arg @ref LL_SPI_FIFO_TH_07DATA
1445 * @arg @ref LL_SPI_FIFO_TH_08DATA
1446 * @arg @ref LL_SPI_FIFO_TH_09DATA
1447 * @arg @ref LL_SPI_FIFO_TH_10DATA
1448 * @arg @ref LL_SPI_FIFO_TH_11DATA
1449 * @arg @ref LL_SPI_FIFO_TH_12DATA
1450 * @arg @ref LL_SPI_FIFO_TH_13DATA
1451 * @arg @ref LL_SPI_FIFO_TH_14DATA
1452 * @arg @ref LL_SPI_FIFO_TH_15DATA
1453 * @arg @ref LL_SPI_FIFO_TH_16DATA
1454 */
1455 __STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)
1456 {
1457 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
1458 }
1459
1460 /**
1461 * @brief Enable CRC
1462 * @note This configuration can not be changed when SPI is enabled.
1463 * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC
1464 * @param SPIx SPI Instance
1465 * @retval None
1466 */
1467 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
1468 {
1469 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1470 }
1471
1472 /**
1473 * @brief Disable CRC
1474 * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC
1475 * @param SPIx SPI Instance
1476 * @retval None
1477 */
1478 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
1479 {
1480 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1481 }
1482
1483 /**
1484 * @brief Check if CRC is enabled
1485 * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC
1486 * @param SPIx SPI Instance
1487 * @retval State of bit (1 or 0).
1488 */
1489 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
1490 {
1491 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
1492 }
1493
1494 /**
1495 * @brief Set CRC Length
1496 * @note This configuration can not be changed when SPI is enabled.
1497 * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth
1498 * @param SPIx SPI Instance
1499 * @param CRCLength This parameter can be one of the following values:
1500 * @arg @ref LL_SPI_CRC_4BIT
1501 * @arg @ref LL_SPI_CRC_5BIT
1502 * @arg @ref LL_SPI_CRC_6BIT
1503 * @arg @ref LL_SPI_CRC_7BIT
1504 * @arg @ref LL_SPI_CRC_8BIT
1505 * @arg @ref LL_SPI_CRC_9BIT
1506 * @arg @ref LL_SPI_CRC_10BIT
1507 * @arg @ref LL_SPI_CRC_11BIT
1508 * @arg @ref LL_SPI_CRC_12BIT
1509 * @arg @ref LL_SPI_CRC_13BIT
1510 * @arg @ref LL_SPI_CRC_14BIT
1511 * @arg @ref LL_SPI_CRC_15BIT
1512 * @arg @ref LL_SPI_CRC_16BIT
1513 * @arg @ref LL_SPI_CRC_17BIT
1514 * @arg @ref LL_SPI_CRC_18BIT
1515 * @arg @ref LL_SPI_CRC_19BIT
1516 * @arg @ref LL_SPI_CRC_20BIT
1517 * @arg @ref LL_SPI_CRC_21BIT
1518 * @arg @ref LL_SPI_CRC_22BIT
1519 * @arg @ref LL_SPI_CRC_23BIT
1520 * @arg @ref LL_SPI_CRC_24BIT
1521 * @arg @ref LL_SPI_CRC_25BIT
1522 * @arg @ref LL_SPI_CRC_26BIT
1523 * @arg @ref LL_SPI_CRC_27BIT
1524 * @arg @ref LL_SPI_CRC_28BIT
1525 * @arg @ref LL_SPI_CRC_29BIT
1526 * @arg @ref LL_SPI_CRC_30BIT
1527 * @arg @ref LL_SPI_CRC_31BIT
1528 * @arg @ref LL_SPI_CRC_32BIT
1529 * @retval None
1530 */
1531 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
1532 {
1533 MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
1534 }
1535
1536 /**
1537 * @brief Get CRC Length
1538 * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth
1539 * @param SPIx SPI Instance
1540 * @retval Returned value can be one of the following values:
1541 * @arg @ref LL_SPI_CRC_4BIT
1542 * @arg @ref LL_SPI_CRC_5BIT
1543 * @arg @ref LL_SPI_CRC_6BIT
1544 * @arg @ref LL_SPI_CRC_7BIT
1545 * @arg @ref LL_SPI_CRC_8BIT
1546 * @arg @ref LL_SPI_CRC_9BIT
1547 * @arg @ref LL_SPI_CRC_10BIT
1548 * @arg @ref LL_SPI_CRC_11BIT
1549 * @arg @ref LL_SPI_CRC_12BIT
1550 * @arg @ref LL_SPI_CRC_13BIT
1551 * @arg @ref LL_SPI_CRC_14BIT
1552 * @arg @ref LL_SPI_CRC_15BIT
1553 * @arg @ref LL_SPI_CRC_16BIT
1554 * @arg @ref LL_SPI_CRC_17BIT
1555 * @arg @ref LL_SPI_CRC_18BIT
1556 * @arg @ref LL_SPI_CRC_19BIT
1557 * @arg @ref LL_SPI_CRC_20BIT
1558 * @arg @ref LL_SPI_CRC_21BIT
1559 * @arg @ref LL_SPI_CRC_22BIT
1560 * @arg @ref LL_SPI_CRC_23BIT
1561 * @arg @ref LL_SPI_CRC_24BIT
1562 * @arg @ref LL_SPI_CRC_25BIT
1563 * @arg @ref LL_SPI_CRC_26BIT
1564 * @arg @ref LL_SPI_CRC_27BIT
1565 * @arg @ref LL_SPI_CRC_28BIT
1566 * @arg @ref LL_SPI_CRC_29BIT
1567 * @arg @ref LL_SPI_CRC_30BIT
1568 * @arg @ref LL_SPI_CRC_31BIT
1569 * @arg @ref LL_SPI_CRC_32BIT
1570 */
1571 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
1572 {
1573 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
1574 }
1575
1576 /**
1577 * @brief Set NSS Mode
1578 * @note This configuration can not be changed when SPI is enabled.
1579 * This bit is not used in SPI TI mode.
1580 * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n
1581 * CFG2 SSOE LL_SPI_SetNSSMode
1582 * @param SPIx SPI Instance
1583 * @param NSS This parameter can be one of the following values:
1584 * @arg @ref LL_SPI_NSS_SOFT
1585 * @arg @ref LL_SPI_NSS_HARD_INPUT
1586 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1587 * @retval None
1588 */
1589 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
1590 {
1591 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
1592 }
1593
1594 /**
1595 * @brief Set NSS Mode
1596 * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n
1597 * CFG2 SSOE LL_SPI_GetNSSMode
1598 * @param SPIx SPI Instance
1599 * @retval Returned value can be one of the following values:
1600 * @arg @ref LL_SPI_NSS_SOFT
1601 * @arg @ref LL_SPI_NSS_HARD_INPUT
1602 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1603 */
1604 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
1605 {
1606 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
1607 }
1608
1609 /**
1610 * @brief Enable NSS pulse mgt
1611 * @note This configuration can not be changed when SPI is enabled.
1612 * This bit is not used in SPI TI mode.
1613 * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt
1614 * @param SPIx SPI Instance
1615 * @retval None
1616 */
1617 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
1618 {
1619 SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1620 }
1621
1622 /**
1623 * @brief Disable NSS pulse mgt
1624 * @note This configuration can not be changed when SPI is enabled.
1625 * This bit is not used in SPI TI mode.
1626 * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt
1627 * @param SPIx SPI Instance
1628 * @retval None
1629 */
1630 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
1631 {
1632 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1633 }
1634
1635 /**
1636 * @brief Check if NSS pulse is enabled
1637 * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse
1638 * @param SPIx SPI Instance
1639 * @retval State of bit (1 or 0)
1640 */
1641 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
1642 {
1643 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
1644 }
1645
1646 /**
1647 * @}
1648 */
1649
1650 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1651 * @{
1652 */
1653
1654 /**
1655 * @brief Check if there is enough data in FIFO to read a full packet
1656 * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
1657 * @param SPIx SPI Instance
1658 * @retval State of bit (1 or 0)
1659 */
1660 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
1661 {
1662 return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
1663 }
1664
1665 /**
1666 * @brief Check if there is enough space in FIFO to hold a full packet
1667 * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP
1668 * @param SPIx SPI Instance
1669 * @retval State of bit (1 or 0)
1670 */
1671 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
1672 {
1673 return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
1674 }
1675
1676 /**
1677 * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
1678 * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP
1679 * @param SPIx SPI Instance
1680 * @retval State of bit (1 or 0)
1681 */
1682 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
1683 {
1684 return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
1685 }
1686
1687 /**
1688 * @brief Check that end of transfer event occured
1689 * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
1690 * @param SPIx SPI Instance
1691 * @retval State of bit (1 or 0).
1692 */
1693 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
1694 {
1695 return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
1696 }
1697
1698 /**
1699 * @brief Check that all required data has been filled in the fifo according to transfer size
1700 * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF
1701 * @param SPIx SPI Instance
1702 * @retval State of bit (1 or 0).
1703 */
1704 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
1705 {
1706 return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
1707 }
1708
1709 /**
1710 * @brief Get Underrun error flag
1711 * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
1712 * @param SPIx SPI Instance
1713 * @retval State of bit (1 or 0).
1714 */
1715 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1716 {
1717 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1718 }
1719
1720 /**
1721 * @brief Get CRC error flag
1722 * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR
1723 * @param SPIx SPI Instance
1724 * @retval State of bit (1 or 0).
1725 */
1726 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
1727 {
1728 return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
1729 }
1730
1731 /**
1732 * @brief Get Mode fault error flag
1733 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
1734 * @param SPIx SPI Instance
1735 * @retval State of bit (1 or 0).
1736 */
1737 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
1738 {
1739 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
1740 }
1741
1742 /**
1743 * @brief Get Overrun error flag
1744 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
1745 * @param SPIx SPI Instance
1746 * @retval State of bit (1 or 0).
1747 */
1748 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1749 {
1750 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
1751 }
1752
1753 /**
1754 * @brief Get TI Frame format error flag
1755 * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE
1756 * @param SPIx SPI Instance
1757 * @retval State of bit (1 or 0).
1758 */
1759 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
1760 {
1761 return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
1762 }
1763
1764 /**
1765 * @brief Check if the additional number of data has been reloaded
1766 * @rmtoll SR TSERF LL_SPI_IsActiveFlag_TSER
1767 * @param SPIx SPI Instance
1768 * @retval State of bit (1 or 0).
1769 */
1770 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx)
1771 {
1772 return ((READ_BIT(SPIx->SR, SPI_SR_TSERF) == (SPI_SR_TSERF)) ? 1UL : 0UL);
1773 }
1774
1775 /**
1776 * @brief Check if a suspend operation is done
1777 * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP
1778 * @param SPIx SPI Instance
1779 * @retval State of bit (1 or 0)
1780 */
1781 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
1782 {
1783 return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
1784 }
1785
1786 /**
1787 * @brief Get TXC flag
1788 * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC
1789 * @param SPIx SPI Instance
1790 * @retval State of bit (1 or 0).
1791 */
1792 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
1793 {
1794 return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
1795 }
1796
1797 /**
1798 * @brief Check if at least one 32-bit data is available in RxFIFO
1799 * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE
1800 * @param SPIx SPI Instance
1801 * @retval State of bit (1 or 0)
1802 */
1803 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
1804 {
1805 return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
1806 }
1807
1808 /**
1809 * @brief Get number of data framed remaining in current TSIZE
1810 * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames
1811 * @param SPIx SPI Instance
1812 * @retval 0..0xFFFF
1813 */
1814 __STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
1815 {
1816 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
1817 }
1818
1819 /**
1820 * @brief Get RxFIFO packing Level
1821 * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
1822 * @param SPIx SPI Instance
1823 * @retval Returned value can be one of the following values:
1824 * @arg @ref LL_SPI_RX_FIFO_0PACKET
1825 * @arg @ref LL_SPI_RX_FIFO_1PACKET
1826 * @arg @ref LL_SPI_RX_FIFO_2PACKET
1827 * @arg @ref LL_SPI_RX_FIFO_3PACKET
1828 */
1829 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)
1830 {
1831 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
1832 }
1833
1834 /**
1835 * @brief Clear End Of Transfer flag
1836 * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT
1837 * @param SPIx SPI Instance
1838 * @retval None
1839 */
1840 __STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
1841 {
1842 SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
1843 }
1844
1845 /**
1846 * @brief Clear TXTF flag
1847 * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF
1848 * @param SPIx SPI Instance
1849 * @retval None
1850 */
1851 __STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
1852 {
1853 SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
1854 }
1855
1856 /**
1857 * @brief Clear Underrun error flag
1858 * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR
1859 * @param SPIx SPI Instance
1860 * @retval None
1861 */
1862 __STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
1863 {
1864 SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
1865 }
1866
1867 /**
1868 * @brief Clear Overrun error flag
1869 * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR
1870 * @param SPIx SPI Instance
1871 * @retval None
1872 */
1873 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1874 {
1875 SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
1876 }
1877
1878 /**
1879 * @brief Clear CRC error flag
1880 * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR
1881 * @param SPIx SPI Instance
1882 * @retval None
1883 */
1884 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1885 {
1886 SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
1887 }
1888
1889 /**
1890 * @brief Clear Mode fault error flag
1891 * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF
1892 * @param SPIx SPI Instance
1893 * @retval None
1894 */
1895 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1896 {
1897 SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
1898 }
1899
1900 /**
1901 * @brief Clear Frame format error flag
1902 * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE
1903 * @param SPIx SPI Instance
1904 * @retval None
1905 */
1906 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1907 {
1908 SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
1909 }
1910
1911 /**
1912 * @brief Clear TSER flag
1913 * @rmtoll IFCR TSERFC LL_SPI_ClearFlag_TSER
1914 * @param SPIx SPI Instance
1915 * @retval None
1916 */
1917 __STATIC_INLINE void LL_SPI_ClearFlag_TSER(SPI_TypeDef *SPIx)
1918 {
1919 SET_BIT(SPIx->IFCR, SPI_IFCR_TSERFC);
1920 }
1921
1922 /**
1923 * @brief Clear SUSP flag
1924 * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP
1925 * @param SPIx SPI Instance
1926 * @retval None
1927 */
1928 __STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
1929 {
1930 SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
1931 }
1932
1933 /**
1934 * @}
1935 */
1936
1937 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1938 * @{
1939 */
1940
1941 /**
1942 * @brief Enable Rx Packet available IT
1943 * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP
1944 * @param SPIx SPI Instance
1945 * @retval None
1946 */
1947 __STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
1948 {
1949 SET_BIT(SPIx->IER, SPI_IER_RXPIE);
1950 }
1951
1952 /**
1953 * @brief Enable Tx Packet space available IT
1954 * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP
1955 * @param SPIx SPI Instance
1956 * @retval None
1957 */
1958 __STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
1959 {
1960 SET_BIT(SPIx->IER, SPI_IER_TXPIE);
1961 }
1962
1963 /**
1964 * @brief Enable Duplex Packet available IT
1965 * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP
1966 * @param SPIx SPI Instance
1967 * @retval None
1968 */
1969 __STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
1970 {
1971 SET_BIT(SPIx->IER, SPI_IER_DXPIE);
1972 }
1973
1974 /**
1975 * @brief Enable End Of Transfer IT
1976 * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT
1977 * @param SPIx SPI Instance
1978 * @retval None
1979 */
1980 __STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
1981 {
1982 SET_BIT(SPIx->IER, SPI_IER_EOTIE);
1983 }
1984
1985 /**
1986 * @brief Enable TXTF IT
1987 * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF
1988 * @param SPIx SPI Instance
1989 * @retval None
1990 */
1991 __STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
1992 {
1993 SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
1994 }
1995
1996 /**
1997 * @brief Enable Underrun IT
1998 * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR
1999 * @param SPIx SPI Instance
2000 * @retval None
2001 */
2002 __STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
2003 {
2004 SET_BIT(SPIx->IER, SPI_IER_UDRIE);
2005 }
2006
2007 /**
2008 * @brief Enable Overrun IT
2009 * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR
2010 * @param SPIx SPI Instance
2011 * @retval None
2012 */
2013 __STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
2014 {
2015 SET_BIT(SPIx->IER, SPI_IER_OVRIE);
2016 }
2017
2018 /**
2019 * @brief Enable CRC Error IT
2020 * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR
2021 * @param SPIx SPI Instance
2022 * @retval None
2023 */
2024 __STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
2025 {
2026 SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
2027 }
2028
2029 /**
2030 * @brief Enable TI Frame Format Error IT
2031 * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE
2032 * @param SPIx SPI Instance
2033 * @retval None
2034 */
2035 __STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
2036 {
2037 SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
2038 }
2039
2040 /**
2041 * @brief Enable MODF IT
2042 * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF
2043 * @param SPIx SPI Instance
2044 * @retval None
2045 */
2046 __STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
2047 {
2048 SET_BIT(SPIx->IER, SPI_IER_MODFIE);
2049 }
2050
2051 /**
2052 * @brief Enable TSER reload IT
2053 * @rmtoll IER TSERFIE LL_SPI_EnableIT_TSER
2054 * @param SPIx SPI Instance
2055 * @retval None
2056 */
2057 __STATIC_INLINE void LL_SPI_EnableIT_TSER(SPI_TypeDef *SPIx)
2058 {
2059 SET_BIT(SPIx->IER, SPI_IER_TSERFIE);
2060 }
2061
2062 /**
2063 * @brief Disable Rx Packet available IT
2064 * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP
2065 * @param SPIx SPI Instance
2066 * @retval None
2067 */
2068 __STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
2069 {
2070 CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
2071 }
2072
2073 /**
2074 * @brief Disable Tx Packet space available IT
2075 * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP
2076 * @param SPIx SPI Instance
2077 * @retval None
2078 */
2079 __STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
2080 {
2081 CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
2082 }
2083
2084 /**
2085 * @brief Disable Duplex Packet available IT
2086 * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP
2087 * @param SPIx SPI Instance
2088 * @retval None
2089 */
2090 __STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
2091 {
2092 CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
2093 }
2094
2095 /**
2096 * @brief Disable End Of Transfer IT
2097 * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT
2098 * @param SPIx SPI Instance
2099 * @retval None
2100 */
2101 __STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
2102 {
2103 CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
2104 }
2105
2106 /**
2107 * @brief Disable TXTF IT
2108 * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF
2109 * @param SPIx SPI Instance
2110 * @retval None
2111 */
2112 __STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
2113 {
2114 CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
2115 }
2116
2117 /**
2118 * @brief Disable Underrun IT
2119 * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR
2120 * @param SPIx SPI Instance
2121 * @retval None
2122 */
2123 __STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
2124 {
2125 CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
2126 }
2127
2128 /**
2129 * @brief Disable Overrun IT
2130 * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR
2131 * @param SPIx SPI Instance
2132 * @retval None
2133 */
2134 __STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
2135 {
2136 CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
2137 }
2138
2139 /**
2140 * @brief Disable CRC Error IT
2141 * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR
2142 * @param SPIx SPI Instance
2143 * @retval None
2144 */
2145 __STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
2146 {
2147 CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
2148 }
2149
2150 /**
2151 * @brief Disable TI Frame Format Error IT
2152 * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE
2153 * @param SPIx SPI Instance
2154 * @retval None
2155 */
2156 __STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
2157 {
2158 CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
2159 }
2160
2161 /**
2162 * @brief Disable MODF IT
2163 * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF
2164 * @param SPIx SPI Instance
2165 * @retval None
2166 */
2167 __STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
2168 {
2169 CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
2170 }
2171
2172 /**
2173 * @brief Disable TSER reload IT
2174 * @rmtoll IER TSERFIE LL_SPI_DisableIT_TSER
2175 * @param SPIx SPI Instance
2176 * @retval None
2177 */
2178 __STATIC_INLINE void LL_SPI_DisableIT_TSER(SPI_TypeDef *SPIx)
2179 {
2180 CLEAR_BIT(SPIx->IER, SPI_IER_TSERFIE);
2181 }
2182
2183 /**
2184 * @brief Check if Rx Packet available IT is enabled
2185 * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP
2186 * @param SPIx SPI Instance
2187 * @retval State of bit (1 or 0)
2188 */
2189 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
2190 {
2191 return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
2192 }
2193
2194 /**
2195 * @brief Check if Tx Packet space available IT is enabled
2196 * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP
2197 * @param SPIx SPI Instance
2198 * @retval State of bit (1 or 0)
2199 */
2200 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
2201 {
2202 return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
2203 }
2204
2205 /**
2206 * @brief Check if Duplex Packet available IT is enabled
2207 * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP
2208 * @param SPIx SPI Instance
2209 * @retval State of bit (1 or 0)
2210 */
2211 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
2212 {
2213 return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
2214 }
2215
2216 /**
2217 * @brief Check if End Of Transfer IT is enabled
2218 * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT
2219 * @param SPIx SPI Instance
2220 * @retval State of bit (1 or 0)
2221 */
2222 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
2223 {
2224 return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
2225 }
2226
2227 /**
2228 * @brief Check if TXTF IT is enabled
2229 * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF
2230 * @param SPIx SPI Instance
2231 * @retval State of bit (1 or 0)
2232 */
2233 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
2234 {
2235 return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
2236 }
2237
2238 /**
2239 * @brief Check if Underrun IT is enabled
2240 * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR
2241 * @param SPIx SPI Instance
2242 * @retval State of bit (1 or 0)
2243 */
2244 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
2245 {
2246 return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
2247 }
2248
2249 /**
2250 * @brief Check if Overrun IT is enabled
2251 * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR
2252 * @param SPIx SPI Instance
2253 * @retval State of bit (1 or 0)
2254 */
2255 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
2256 {
2257 return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
2258 }
2259
2260 /**
2261 * @brief Check if CRC Error IT is enabled
2262 * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
2263 * @param SPIx SPI Instance
2264 * @retval State of bit (1 or 0)
2265 */
2266 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
2267 {
2268 return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
2269 }
2270
2271 /**
2272 * @brief Check if TI Frame Format Error IT is enabled
2273 * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE
2274 * @param SPIx SPI Instance
2275 * @retval State of bit (1 or 0)
2276 */
2277 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
2278 {
2279 return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
2280 }
2281
2282 /**
2283 * @brief Check if MODF IT is enabled
2284 * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF
2285 * @param SPIx SPI Instance
2286 * @retval State of bit (1 or 0)
2287 */
2288 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
2289 {
2290 return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
2291 }
2292
2293 /**
2294 * @brief Check if TSER reload IT is enabled
2295 * @rmtoll IER TSERFIE LL_SPI_IsEnabledIT_TSER
2296 * @param SPIx SPI Instance
2297 * @retval State of bit (1 or 0)
2298 */
2299 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(SPI_TypeDef *SPIx)
2300 {
2301 return ((READ_BIT(SPIx->IER, SPI_IER_TSERFIE) == (SPI_IER_TSERFIE)) ? 1UL : 0UL);
2302 }
2303
2304 /**
2305 * @}
2306 */
2307
2308 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
2309 * @{
2310 */
2311
2312 /**
2313 * @brief Enable DMA Rx
2314 * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
2315 * @param SPIx SPI Instance
2316 * @retval None
2317 */
2318 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
2319 {
2320 SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2321 }
2322
2323 /**
2324 * @brief Disable DMA Rx
2325 * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
2326 * @param SPIx SPI Instance
2327 * @retval None
2328 */
2329 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
2330 {
2331 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2332 }
2333
2334 /**
2335 * @brief Check if DMA Rx is enabled
2336 * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
2337 * @param SPIx SPI Instance
2338 * @retval State of bit (1 or 0)
2339 */
2340 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
2341 {
2342 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
2343 }
2344
2345 /**
2346 * @brief Enable DMA Tx
2347 * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
2348 * @param SPIx SPI Instance
2349 * @retval None
2350 */
2351 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
2352 {
2353 SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2354 }
2355
2356 /**
2357 * @brief Disable DMA Tx
2358 * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
2359 * @param SPIx SPI Instance
2360 * @retval None
2361 */
2362 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
2363 {
2364 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2365 }
2366
2367 /**
2368 * @brief Check if DMA Tx is enabled
2369 * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
2370 * @param SPIx SPI Instance
2371 * @retval State of bit (1 or 0)
2372 */
2373 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
2374 {
2375 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
2376 }
2377
2378 /**
2379 * @}
2380 */
2381
2382 // Avoid strict aliasing warnings from deferencing type-punned pointers
2383 #pragma GCC diagnostic push
2384 #pragma GCC diagnostic ignored "-Wstrict-aliasing"
2385
2386 /** @defgroup SPI_LL_EF_DATA_Management DATA_Management
2387 * @{
2388 */
2389
2390 /**
2391 * @brief Read Data Register
2392 * @rmtoll RXDR . LL_SPI_ReceiveData8
2393 * @param SPIx SPI Instance
2394 * @retval 0..0xFF
2395 */
2396 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
2397 {
2398 return (*((__IO uint8_t *)&SPIx->RXDR));
2399 }
2400
2401 /**
2402 * @brief Read Data Register
2403 * @rmtoll RXDR . LL_SPI_ReceiveData16
2404 * @param SPIx SPI Instance
2405 * @retval 0..0xFFFF
2406 */
2407 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
2408 {
2409 return (*((__IO uint16_t *)&SPIx->RXDR));
2410 }
2411
2412 /**
2413 * @brief Read Data Register
2414 * @rmtoll RXDR . LL_SPI_ReceiveData32
2415 * @param SPIx SPI Instance
2416 * @retval 0..0xFFFFFFFF
2417 */
2418 __STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)
2419 {
2420 return (*((__IO uint32_t *)&SPIx->RXDR));
2421 }
2422
2423 /**
2424 * @brief Write Data Register
2425 * @rmtoll TXDR . LL_SPI_TransmitData8
2426 * @param SPIx SPI Instance
2427 * @param TxData 0..0xFF
2428 * @retval None
2429 */
2430 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
2431 {
2432 *((__IO uint8_t *)&SPIx->TXDR) = TxData;
2433 }
2434
2435 /**
2436 * @brief Write Data Register
2437 * @rmtoll TXDR . LL_SPI_TransmitData16
2438 * @param SPIx SPI Instance
2439 * @param TxData 0..0xFFFF
2440 * @retval None
2441 */
2442 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
2443 {
2444 *((__IO uint16_t *)&SPIx->TXDR) = TxData;
2445 }
2446
2447 /**
2448 * @brief Write Data Register
2449 * @rmtoll TXDR . LL_SPI_TransmitData32
2450 * @param SPIx SPI Instance
2451 * @param TxData 0..0xFFFFFFFF
2452 * @retval None
2453 */
2454 __STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
2455 {
2456 *((__IO uint32_t *)&SPIx->TXDR) = TxData;
2457 }
2458
2459 #pragma GCC diagnostic pop
2460
2461 /**
2462 * @brief Set polynomial for CRC calcul
2463 * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
2464 * @param SPIx SPI Instance
2465 * @param CRCPoly 0..0xFFFFFFFF
2466 * @retval None
2467 */
2468 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
2469 {
2470 WRITE_REG(SPIx->CRCPOLY, CRCPoly);
2471 }
2472
2473 /**
2474 * @brief Get polynomial for CRC calcul
2475 * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
2476 * @param SPIx SPI Instance
2477 * @retval 0..0xFFFFFFFF
2478 */
2479 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
2480 {
2481 return (uint32_t)(READ_REG(SPIx->CRCPOLY));
2482 }
2483
2484 /**
2485 * @brief Set the underrun pattern
2486 * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern
2487 * @param SPIx SPI Instance
2488 * @param Pattern 0..0xFFFFFFFF
2489 * @retval None
2490 */
2491 __STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
2492 {
2493 WRITE_REG(SPIx->UDRDR, Pattern);
2494 }
2495
2496 /**
2497 * @brief Get the underrun pattern
2498 * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern
2499 * @param SPIx SPI Instance
2500 * @retval 0..0xFFFFFFFF
2501 */
2502 __STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
2503 {
2504 return (uint32_t)(READ_REG(SPIx->UDRDR));
2505 }
2506
2507 /**
2508 * @brief Get Rx CRC
2509 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
2510 * @param SPIx SPI Instance
2511 * @retval 0..0xFFFFFFFF
2512 */
2513 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
2514 {
2515 return (uint32_t)(READ_REG(SPIx->RXCRC));
2516 }
2517
2518 /**
2519 * @brief Get Tx CRC
2520 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
2521 * @param SPIx SPI Instance
2522 * @retval 0..0xFFFFFFFF
2523 */
2524 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
2525 {
2526 return (uint32_t)(READ_REG(SPIx->TXCRC));
2527 }
2528
2529 /**
2530 * @}
2531 */
2532
2533 #if defined(USE_FULL_LL_DRIVER)
2534 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
2535 * @{
2536 */
2537
2538 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
2539 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
2540 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
2541
2542 /**
2543 * @}
2544 */
2545 #endif /* USE_FULL_LL_DRIVER */
2546
2547
2548 /** @defgroup I2S_LL I2S
2549 * @{
2550 */
2551
2552 /* Private variables ---------------------------------------------------------*/
2553 /* Private constants ---------------------------------------------------------*/
2554 /* Private macros ------------------------------------------------------------*/
2555
2556 /* Exported types ------------------------------------------------------------*/
2557 #if defined(USE_FULL_LL_DRIVER)
2558 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
2559 * @{
2560 */
2561
2562 /**
2563 * @brief I2S Init structure definition
2564 */
2565
2566 typedef struct
2567 {
2568 uint32_t Mode; /*!< Specifies the I2S operating mode.
2569 This parameter can be a value of @ref I2S_LL_EC_MODE
2570
2571 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
2572
2573 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
2574 This parameter can be a value of @ref I2S_LL_EC_STANDARD
2575
2576 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
2577
2578
2579 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
2580 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
2581
2582 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
2583
2584
2585 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
2586 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
2587
2588 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
2589
2590
2591 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
2592 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
2593
2594 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
2595 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
2596
2597
2598 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
2599 This parameter can be a value of @ref I2S_LL_EC_POLARITY
2600
2601 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
2602
2603 } LL_I2S_InitTypeDef;
2604
2605 /**
2606 * @}
2607 */
2608 #endif /*USE_FULL_LL_DRIVER*/
2609
2610 /* Exported constants --------------------------------------------------------*/
2611 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
2612 * @{
2613 */
2614
2615 /** @defgroup I2S_LL_EC_DATA_FORMAT Data Format
2616 * @{
2617 */
2618 #define LL_I2S_DATAFORMAT_16B (0x00000000UL)
2619 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
2620 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
2621 #define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)
2622 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
2623 /**
2624 * @}
2625 */
2626
2627 /** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length
2628 * @{
2629 */
2630 #define LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL)
2631 #define LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH)
2632 /**
2633 * @}
2634 */
2635
2636 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
2637 * @{
2638 */
2639 #define LL_I2S_POLARITY_LOW (0x00000000UL)
2640 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
2641 /**
2642 * @}
2643 */
2644
2645 /** @defgroup I2S_LL_EC_STANDARD I2S Standard
2646 * @{
2647 */
2648 #define LL_I2S_STANDARD_PHILIPS (0x00000000UL)
2649 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
2650 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
2651 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
2652 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
2653 /**
2654 * @}
2655 */
2656
2657 /** @defgroup I2S_LL_EC_MODE Operation Mode
2658 * @{
2659 */
2660 #define LL_I2S_MODE_SLAVE_TX (0x00000000UL)
2661 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
2662 #define LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2)
2663 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
2664 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)
2665 #define LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
2666 /**
2667 * @}
2668 */
2669
2670 /** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor
2671 * @{
2672 */
2673 #define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */
2674 #define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
2675 /**
2676 * @}
2677 */
2678
2679 /** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level
2680 * @{
2681 */
2682 #define LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA)
2683 #define LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA)
2684 #define LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA)
2685 #define LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA)
2686 #define LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA)
2687 #define LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA)
2688 #define LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA)
2689 #define LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA)
2690 /**
2691 * @}
2692 */
2693
2694 /** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order
2695 * @{
2696 */
2697 #define LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST)
2698 #define LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST)
2699 /**
2700 * @}
2701 */
2702
2703 #if defined(USE_FULL_LL_DRIVER)
2704
2705 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
2706 * @{
2707 */
2708 #define LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL)
2709 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
2710 /**
2711 * @}
2712 */
2713
2714 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
2715 * @{
2716 */
2717
2718 #define LL_I2S_AUDIOFREQ_192K 192000UL /*!< Audio Frequency configuration 192000 Hz */
2719 #define LL_I2S_AUDIOFREQ_96K 96000UL /*!< Audio Frequency configuration 96000 Hz */
2720 #define LL_I2S_AUDIOFREQ_48K 48000UL /*!< Audio Frequency configuration 48000 Hz */
2721 #define LL_I2S_AUDIOFREQ_44K 44100UL /*!< Audio Frequency configuration 44100 Hz */
2722 #define LL_I2S_AUDIOFREQ_32K 32000UL /*!< Audio Frequency configuration 32000 Hz */
2723 #define LL_I2S_AUDIOFREQ_22K 22050UL /*!< Audio Frequency configuration 22050 Hz */
2724 #define LL_I2S_AUDIOFREQ_16K 16000UL /*!< Audio Frequency configuration 16000 Hz */
2725 #define LL_I2S_AUDIOFREQ_11K 11025UL /*!< Audio Frequency configuration 11025 Hz */
2726 #define LL_I2S_AUDIOFREQ_8K 8000UL /*!< Audio Frequency configuration 8000 Hz */
2727 #define LL_I2S_AUDIOFREQ_DEFAULT 0UL /*!< Audio Freq not specified. Register I2SDIV = 0 */
2728 /**
2729 * @}
2730 */
2731 #endif /* USE_FULL_LL_DRIVER */
2732
2733 /**
2734 * @}
2735 */
2736
2737 /* Exported macro ------------------------------------------------------------*/
2738 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
2739 * @{
2740 */
2741
2742 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
2743 * @{
2744 */
2745
2746 /**
2747 * @brief Write a value in I2S register
2748 * @param __INSTANCE__ I2S Instance
2749 * @param __REG__ Register to be written
2750 * @param __VALUE__ Value to be written in the register
2751 * @retval None
2752 */
2753 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2754
2755 /**
2756 * @brief Read a value in I2S register
2757 * @param __INSTANCE__ I2S Instance
2758 * @param __REG__ Register to be read
2759 * @retval Register value
2760 */
2761 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2762 /**
2763 * @}
2764 */
2765
2766 /**
2767 * @}
2768 */
2769
2770
2771 /* Exported functions --------------------------------------------------------*/
2772
2773 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
2774 * @{
2775 */
2776
2777 /** @defgroup I2S_LL_EF_Configuration Configuration
2778 * @{
2779 */
2780
2781 /**
2782 * @brief Set I2S Data frame format
2783 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
2784 * I2SCFGR CHLEN LL_I2S_SetDataFormat\n
2785 * I2SCFGR DATFMT LL_I2S_SetDataFormat
2786 * @param SPIx SPI Handle
2787 * @param DataLength This parameter can be one of the following values:
2788 * @arg @ref LL_I2S_DATAFORMAT_16B
2789 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
2790 * @arg @ref LL_I2S_DATAFORMAT_24B
2791 * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
2792 * @arg @ref LL_I2S_DATAFORMAT_32B
2793 * @retval None
2794 */
2795 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength)
2796 {
2797 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT, DataLength);
2798 }
2799
2800 /**
2801 * @brief Get I2S Data frame format
2802 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
2803 * I2SCFGR CHLEN LL_I2S_GetDataFormat\n
2804 * I2SCFGR DATFMT LL_I2S_GetDataFormat
2805 * @param SPIx SPI Handle
2806 * @retval Return value can be one of the following values:
2807 * @arg @ref LL_I2S_DATAFORMAT_16B
2808 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
2809 * @arg @ref LL_I2S_DATAFORMAT_24B
2810 * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
2811 * @arg @ref LL_I2S_DATAFORMAT_32B
2812 */
2813 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
2814 {
2815 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));
2816 }
2817
2818 /**
2819 * @brief Set I2S Channel Length Type
2820 * @note This feature is usefull with SLAVE only
2821 * @rmtoll I2SCFGR FIXCH LL_I2S_SetChannelLengthType
2822 * @param SPIx SPI Handle
2823 * @param ChannelLengthType This parameter can be one of the following values:
2824 * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
2825 * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
2826 * @retval None
2827 */
2828 __STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType)
2829 {
2830 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType);
2831 }
2832
2833 /**
2834 * @brief Get I2S Channel Length Type
2835 * @note This feature is usefull with SLAVE only
2836 * @rmtoll I2SCFGR FIXCH LL_I2S_GetChannelLengthType
2837 * @param SPIx SPI Handle
2838 * @retval Return value can be one of the following values:
2839 * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
2840 * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
2841 */
2842 __STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(SPI_TypeDef *SPIx)
2843 {
2844 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
2845 }
2846
2847 /**
2848 * @brief Invert the default polarity of WS signal
2849 * @rmtoll I2SCFGR WSINV LL_I2S_EnableWordSelectInversion
2850 * @param SPIx SPI Handle
2851 * @retval None
2852 */
2853 __STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx)
2854 {
2855 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2856 }
2857
2858 /**
2859 * @brief Use the default polarity of WS signal
2860 * @rmtoll I2SCFGR WSINV LL_I2S_DisableWordSelectInversion
2861 * @param SPIx SPI Handle
2862 * @retval None
2863 */
2864 __STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)
2865 {
2866 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2867 }
2868
2869 /**
2870 * @brief Check if polarity of WS signal is inverted
2871 * @rmtoll I2SCFGR WSINV LL_I2S_IsEnabledWordSelectInversion
2872 * @param SPIx SPI Handle
2873 * @retval State of bit (1 or 0)
2874 */
2875 __STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *SPIx)
2876 {
2877 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
2878 }
2879
2880 /**
2881 * @brief Set 2S Clock Polarity
2882 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
2883 * @param SPIx SPI Handle
2884 * @param ClockPolarity This parameter can be one of the following values:
2885 * @arg @ref LL_I2S_POLARITY_LOW
2886 * @arg @ref LL_I2S_POLARITY_HIGH
2887 * @retval None
2888 */
2889 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
2890 {
2891 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity);
2892 }
2893
2894 /**
2895 * @brief Get 2S Clock Polarity
2896 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
2897 * @param SPIx SPI Handle
2898 * @retval Return value can be one of the following values:
2899 * @arg @ref LL_I2S_POLARITY_LOW
2900 * @arg @ref LL_I2S_POLARITY_HIGH
2901 */
2902 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
2903 {
2904 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
2905 }
2906
2907 /**
2908 * @brief Set I2S standard
2909 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
2910 * I2SCFGR PCMSYNC LL_I2S_SetStandard
2911 * @param SPIx SPI Handle
2912 * @param Standard This parameter can be one of the following values:
2913 * @arg @ref LL_I2S_STANDARD_PHILIPS
2914 * @arg @ref LL_I2S_STANDARD_MSB
2915 * @arg @ref LL_I2S_STANDARD_LSB
2916 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
2917 * @arg @ref LL_I2S_STANDARD_PCM_LONG
2918 * @retval None
2919 */
2920 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
2921 {
2922 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
2923 }
2924
2925 /**
2926 * @brief Get I2S standard
2927 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
2928 * I2SCFGR PCMSYNC LL_I2S_GetStandard
2929 * @param SPIx SPI Handle
2930 * @retval Return value can be one of the following values:
2931 * @arg @ref LL_I2S_STANDARD_PHILIPS
2932 * @arg @ref LL_I2S_STANDARD_MSB
2933 * @arg @ref LL_I2S_STANDARD_LSB
2934 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
2935 * @arg @ref LL_I2S_STANDARD_PCM_LONG
2936 */
2937 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
2938 {
2939 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
2940 }
2941
2942 /**
2943 * @brief Set I2S config
2944 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
2945 * @param SPIx SPI Handle
2946 * @param Standard This parameter can be one of the following values:
2947 * @arg @ref LL_I2S_MODE_SLAVE_TX
2948 * @arg @ref LL_I2S_MODE_SLAVE_RX
2949 * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
2950 * @arg @ref LL_I2S_MODE_MASTER_TX
2951 * @arg @ref LL_I2S_MODE_MASTER_RX
2952 * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
2953 * @retval None
2954 */
2955 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard)
2956 {
2957 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard);
2958 }
2959
2960 /**
2961 * @brief Get I2S config
2962 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
2963 * @param SPIx SPI Handle
2964 * @retval Return value can be one of the following values:
2965 * @arg @ref LL_I2S_MODE_SLAVE_TX
2966 * @arg @ref LL_I2S_MODE_SLAVE_RX
2967 * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
2968 * @arg @ref LL_I2S_MODE_MASTER_TX
2969 * @arg @ref LL_I2S_MODE_MASTER_RX
2970 * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
2971 */
2972 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
2973 {
2974 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
2975 }
2976
2977 /**
2978 * @brief Select I2S mode and Enable I2S peripheral
2979 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
2980 * CR1 SPE LL_I2S_Enable
2981 * @param SPIx SPI Handle
2982 * @retval None
2983 */
2984 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
2985 {
2986 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
2987 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
2988 }
2989
2990 /**
2991 * @brief Disable I2S peripheral and disable I2S mode
2992 * @rmtoll CR1 SPE LL_I2S_Disable\n
2993 * I2SCFGR I2SMOD LL_I2S_Disable
2994 * @param SPIx SPI Handle
2995 * @retval None
2996 */
2997 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
2998 {
2999 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
3000 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
3001 }
3002
3003 /**
3004 * @brief Swap the SDO and SDI pin
3005 * @note This configuration can not be changed when I2S is enabled.
3006 * @rmtoll CFG2 IOSWP LL_I2S_EnableIOSwap
3007 * @param SPIx SPI Instance
3008 * @retval None
3009 */
3010 __STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx)
3011 {
3012 LL_SPI_EnableIOSwap(SPIx);
3013 }
3014
3015 /**
3016 * @brief Restore default function for SDO and SDI pin
3017 * @note This configuration can not be changed when I2S is enabled.
3018 * @rmtoll CFG2 IOSWP LL_I2S_DisableIOSwap
3019 * @param SPIx SPI Instance
3020 * @retval None
3021 */
3022 __STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)
3023 {
3024 LL_SPI_DisableIOSwap(SPIx);
3025 }
3026
3027 /**
3028 * @brief Check if SDO and SDI pin are swapped
3029 * @rmtoll CFG2 IOSWP LL_I2S_IsEnabledIOSwap
3030 * @param SPIx SPI Instance
3031 * @retval State of bit (1 or 0)
3032 */
3033 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *SPIx)
3034 {
3035 return LL_SPI_IsEnabledIOSwap(SPIx);
3036 }
3037
3038 /**
3039 * @brief Enable GPIO control
3040 * @note This configuration can not be changed when I2S is enabled.
3041 * @rmtoll CFG2 AFCNTR LL_I2S_EnableGPIOControl
3042 * @param SPIx SPI Instance
3043 * @retval None
3044 */
3045 __STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx)
3046 {
3047 LL_SPI_EnableGPIOControl(SPIx);
3048 }
3049
3050 /**
3051 * @brief Disable GPIO control
3052 * @note This configuration can not be changed when I2S is enabled.
3053 * @rmtoll CFG2 AFCNTR LL_I2S_DisableGPIOControl
3054 * @param SPIx SPI Instance
3055 * @retval None
3056 */
3057 __STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)
3058 {
3059 LL_SPI_DisableGPIOControl(SPIx);
3060 }
3061
3062 /**
3063 * @brief Check if GPIO control is active
3064 * @rmtoll CFG2 AFCNTR LL_I2S_IsEnabledGPIOControl
3065 * @param SPIx SPI Instance
3066 * @retval State of bit (1 or 0)
3067 */
3068 __STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
3069 {
3070 return LL_SPI_IsEnabledGPIOControl(SPIx);
3071 }
3072
3073 /**
3074 * @brief Lock the AF configuration of associated IOs
3075 * @note Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs.
3076 * The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
3077 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
3078 * @param SPIx SPI Instance
3079 * @retval None
3080 */
3081 __STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)
3082 {
3083 LL_SPI_EnableIOLock(SPIx);
3084 }
3085
3086 /**
3087 * @brief Check if the the SPI_CFG2 register is locked
3088 * @rmtoll CR1 IOLOCK LL_I2S_IsEnabledIOLock
3089 * @param SPIx SPI Instance
3090 * @retval State of bit (1 or 0)
3091 */
3092 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *SPIx)
3093 {
3094 return LL_SPI_IsEnabledIOLock(SPIx);
3095 }
3096
3097 /**
3098 * @brief Set Transfer Bit Order
3099 * @note This configuration can not be changed when I2S is enabled.
3100 * @rmtoll CFG2 LSBFRST LL_I2S_SetTransferBitOrder
3101 * @param SPIx SPI Instance
3102 * @param BitOrder This parameter can be one of the following values:
3103 * @arg @ref LL_I2S_LSB_FIRST
3104 * @arg @ref LL_I2S_MSB_FIRST
3105 * @retval None
3106 */
3107 __STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
3108 {
3109 LL_SPI_SetTransferBitOrder(SPIx, BitOrder);
3110 }
3111 /**
3112 * @brief Get Transfer Bit Order
3113 * @rmtoll CFG2 LSBFRST LL_I2S_GetTransferBitOrder
3114 * @param SPIx SPI Instance
3115 * @retval Returned value can be one of the following values:
3116 * @arg @ref LL_I2S_LSB_FIRST
3117 * @arg @ref LL_I2S_MSB_FIRST
3118 */
3119 __STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *SPIx)
3120 {
3121 return LL_SPI_GetTransferBitOrder(SPIx);
3122 }
3123
3124 /**
3125 * @brief Start effective transfer on wire
3126 * @rmtoll CR1 CSTART LL_I2S_StartTransfer
3127 * @param SPIx SPI Instance
3128 * @retval None
3129 */
3130 __STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)
3131 {
3132 LL_SPI_StartMasterTransfer(SPIx);
3133 }
3134
3135 /**
3136 * @brief Check if there is an unfinished transfer
3137 * @rmtoll CR1 CSTART LL_I2S_IsTransferActive
3138 * @param SPIx SPI Instance
3139 * @retval State of bit (1 or 0)
3140 */
3141 __STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *SPIx)
3142 {
3143 return LL_SPI_IsActiveMasterTransfer(SPIx);
3144 }
3145
3146 /**
3147 * @brief Set threshold of FIFO that triggers a transfer event
3148 * @note This configuration can not be changed when I2S is enabled.
3149 * @rmtoll CFG1 FTHLV LL_I2S_SetFIFOThreshold
3150 * @param SPIx SPI Instance
3151 * @param Threshold This parameter can be one of the following values:
3152 * @arg @ref LL_I2S_FIFO_TH_01DATA
3153 * @arg @ref LL_I2S_FIFO_TH_02DATA
3154 * @arg @ref LL_I2S_FIFO_TH_03DATA
3155 * @arg @ref LL_I2S_FIFO_TH_04DATA
3156 * @arg @ref LL_I2S_FIFO_TH_05DATA
3157 * @arg @ref LL_I2S_FIFO_TH_06DATA
3158 * @arg @ref LL_I2S_FIFO_TH_07DATA
3159 * @arg @ref LL_I2S_FIFO_TH_08DATA
3160 * @retval None
3161 */
3162 __STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
3163 {
3164 LL_SPI_SetFIFOThreshold(SPIx, Threshold);
3165 }
3166
3167 /**
3168 * @brief Get threshold of FIFO that triggers a transfer event
3169 * @rmtoll CFG1 FTHLV LL_I2S_GetFIFOThreshold
3170 * @param SPIx SPI Instance
3171 * @retval Returned value can be one of the following values:
3172 * @arg @ref LL_I2S_FIFO_TH_01DATA
3173 * @arg @ref LL_I2S_FIFO_TH_02DATA
3174 * @arg @ref LL_I2S_FIFO_TH_03DATA
3175 * @arg @ref LL_I2S_FIFO_TH_04DATA
3176 * @arg @ref LL_I2S_FIFO_TH_05DATA
3177 * @arg @ref LL_I2S_FIFO_TH_06DATA
3178 * @arg @ref LL_I2S_FIFO_TH_07DATA
3179 * @arg @ref LL_I2S_FIFO_TH_08DATA
3180 */
3181 __STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *SPIx)
3182 {
3183 return LL_SPI_GetFIFOThreshold(SPIx);
3184 }
3185
3186 /**
3187 * @brief Set I2S linear prescaler
3188 * @rmtoll I2SCFGR I2SDIV LL_I2S_SetPrescalerLinear
3189 * @param SPIx SPI Instance
3190 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
3191 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
3192 * @retval None
3193 */
3194 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear)
3195 {
3196 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos));
3197 }
3198
3199 /**
3200 * @brief Get I2S linear prescaler
3201 * @rmtoll I2SCFGR I2SDIV LL_I2S_GetPrescalerLinear
3202 * @param SPIx SPI Instance
3203 * @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
3204 */
3205 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
3206 {
3207 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
3208 }
3209
3210 /**
3211 * @brief Set I2S parity prescaler
3212 * @rmtoll I2SCFGR ODD LL_I2S_SetPrescalerParity
3213 * @param SPIx SPI Instance
3214 * @param PrescalerParity This parameter can be one of the following values:
3215 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
3216 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
3217 * @retval None
3218 */
3219 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
3220 {
3221 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos);
3222 }
3223
3224 /**
3225 * @brief Get I2S parity prescaler
3226 * @rmtoll I2SCFGR ODD LL_I2S_GetPrescalerParity
3227 * @param SPIx SPI Instance
3228 * @retval Returned value can be one of the following values:
3229 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
3230 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
3231 */
3232 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
3233 {
3234 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
3235 }
3236
3237 /**
3238 * @brief Enable the Master Clock Output (Pin MCK)
3239 * @rmtoll I2SCFGR MCKOE LL_I2S_EnableMasterClock
3240 * @param SPIx SPI Handle
3241 * @retval None
3242 */
3243 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
3244 {
3245 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3246 }
3247
3248 /**
3249 * @brief Disable the Master Clock Ouput (Pin MCK)
3250 * @rmtoll I2SCFGR MCKOE LL_I2S_DisableMasterClock
3251 * @param SPIx SPI Handle
3252 * @retval None
3253 */
3254 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
3255 {
3256 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3257 }
3258
3259 /**
3260 * @brief Check if the master clock output (Pin MCK) is enabled
3261 * @rmtoll I2SCFGR MCKOE LL_I2S_IsEnabledMasterClock
3262 * @param SPIx SPI Instance
3263 * @retval State of bit (1 or 0)
3264 */
3265 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
3266 {
3267 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
3268 }
3269
3270
3271 /** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management
3272 * @{
3273 */
3274
3275 /**
3276 * @brief Check if there enough data in FIFO to read a full packet
3277 * @rmtoll SR RXP LL_I2S_IsActiveFlag_RXP
3278 * @param SPIx SPI Instance
3279 * @retval State of bit (1 or 0)
3280 */
3281 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
3282 {
3283 return LL_SPI_IsActiveFlag_RXP(SPIx);
3284 }
3285
3286 /**
3287 * @brief Check if there enough space in FIFO to hold a full packet
3288 * @rmtoll SR TXP LL_I2S_IsActiveFlag_TXP
3289 * @param SPIx SPI Instance
3290 * @retval State of bit (1 or 0)
3291 */
3292 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
3293 {
3294 return LL_SPI_IsActiveFlag_TXP(SPIx);
3295 }
3296
3297 /**
3298 * @brief Get Underrun error flag
3299 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
3300 * @param SPIx SPI Instance
3301 * @retval State of bit (1 or 0)
3302 */
3303 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
3304 {
3305 return LL_SPI_IsActiveFlag_UDR(SPIx);
3306 }
3307
3308 /**
3309 * @brief Get Overrun error flag
3310 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
3311 * @param SPIx SPI Instance
3312 * @retval State of bit (1 or 0).
3313 */
3314 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
3315 {
3316 return LL_SPI_IsActiveFlag_OVR(SPIx);
3317 }
3318
3319 /**
3320 * @brief Get TI Frame format error flag
3321 * @rmtoll SR TIFRE LL_I2S_IsActiveFlag_FRE
3322 * @param SPIx SPI Instance
3323 * @retval State of bit (1 or 0).
3324 */
3325 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
3326 {
3327 return LL_SPI_IsActiveFlag_FRE(SPIx);
3328 }
3329
3330 /**
3331 * @brief Clear Underrun error flag
3332 * @rmtoll IFCR UDRC LL_I2S_ClearFlag_UDR
3333 * @param SPIx SPI Instance
3334 * @retval None
3335 */
3336 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
3337 {
3338 LL_SPI_ClearFlag_UDR(SPIx);
3339 }
3340
3341 /**
3342 * @brief Clear Overrun error flag
3343 * @rmtoll IFCR OVRC LL_I2S_ClearFlag_OVR
3344 * @param SPIx SPI Instance
3345 * @retval None
3346 */
3347 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
3348 {
3349 LL_SPI_ClearFlag_OVR(SPIx);
3350 }
3351
3352 /**
3353 * @brief Clear Frame format error flag
3354 * @rmtoll IFCR TIFREC LL_I2S_ClearFlag_FRE
3355 * @param SPIx SPI Instance
3356 * @retval None
3357 */
3358 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
3359 {
3360 LL_SPI_ClearFlag_FRE(SPIx);
3361 }
3362
3363 /**
3364 * @}
3365 */
3366
3367 /** @defgroup I2S_LL_EF_IT_Management IT_Management
3368 * @{
3369 */
3370
3371 /**
3372 * @brief Enable Rx Packet available IT
3373 * @rmtoll IER RXPIE LL_I2S_EnableIT_RXP
3374 * @param SPIx SPI Instance
3375 * @retval None
3376 */
3377 __STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx)
3378 {
3379 LL_SPI_EnableIT_RXP(SPIx);
3380 }
3381
3382 /**
3383 * @brief Enable Tx Packet space available IT
3384 * @rmtoll IER TXPIE LL_I2S_EnableIT_TXP
3385 * @param SPIx SPI Instance
3386 * @retval None
3387 */
3388 __STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx)
3389 {
3390 LL_SPI_EnableIT_TXP(SPIx);
3391 }
3392
3393 /**
3394 * @brief Enable Underrun IT
3395 * @rmtoll IER UDRIE LL_I2S_EnableIT_UDR
3396 * @param SPIx SPI Instance
3397 * @retval None
3398 */
3399 __STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx)
3400 {
3401 LL_SPI_EnableIT_UDR(SPIx);
3402 }
3403
3404 /**
3405 * @brief Enable Overrun IT
3406 * @rmtoll IER OVRIE LL_I2S_EnableIT_OVR
3407 * @param SPIx SPI Instance
3408 * @retval None
3409 */
3410 __STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx)
3411 {
3412 LL_SPI_EnableIT_OVR(SPIx);
3413 }
3414
3415 /**
3416 * @brief Enable TI Frame Format Error IT
3417 * @rmtoll IER TIFREIE LL_I2S_EnableIT_FRE
3418 * @param SPIx SPI Instance
3419 * @retval None
3420 */
3421 __STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx)
3422 {
3423 LL_SPI_EnableIT_FRE(SPIx);
3424 }
3425
3426 /**
3427 * @brief Disable Rx Packet available IT
3428 * @rmtoll IER RXPIE LL_I2S_DisableIT_RXP
3429 * @param SPIx SPI Instance
3430 * @retval None
3431 */
3432 __STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx)
3433 {
3434 LL_SPI_DisableIT_RXP(SPIx);
3435 }
3436
3437 /**
3438 * @brief Disable Tx Packet space available IT
3439 * @rmtoll IER TXPIE LL_I2S_DisableIT_TXP
3440 * @param SPIx SPI Instance
3441 * @retval None
3442 */
3443 __STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx)
3444 {
3445 LL_SPI_DisableIT_TXP(SPIx);
3446 }
3447
3448 /**
3449 * @brief Disable Underrun IT
3450 * @rmtoll IER UDRIE LL_I2S_DisableIT_UDR
3451 * @param SPIx SPI Instance
3452 * @retval None
3453 */
3454 __STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx)
3455 {
3456 LL_SPI_DisableIT_UDR(SPIx);
3457 }
3458
3459 /**
3460 * @brief Disable Overrun IT
3461 * @rmtoll IER OVRIE LL_I2S_DisableIT_OVR
3462 * @param SPIx SPI Instance
3463 * @retval None
3464 */
3465 __STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx)
3466 {
3467 LL_SPI_DisableIT_OVR(SPIx);
3468 }
3469
3470 /**
3471 * @brief Disable TI Frame Format Error IT
3472 * @rmtoll IER TIFREIE LL_I2S_DisableIT_FRE
3473 * @param SPIx SPI Instance
3474 * @retval None
3475 */
3476 __STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)
3477 {
3478 LL_SPI_DisableIT_FRE(SPIx);
3479 }
3480
3481 /**
3482 * @brief Check if Rx Packet available IT is enabled
3483 * @rmtoll IER RXPIE LL_I2S_IsEnabledIT_RXP
3484 * @param SPIx SPI Instance
3485 * @retval State of bit (1 or 0)
3486 */
3487 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
3488 {
3489 return LL_SPI_IsEnabledIT_RXP(SPIx);
3490 }
3491
3492 /**
3493 * @brief Check if Tx Packet space available IT is enabled
3494 * @rmtoll IER TXPIE LL_I2S_IsEnabledIT_TXP
3495 * @param SPIx SPI Instance
3496 * @retval State of bit (1 or 0)
3497 */
3498 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
3499 {
3500 return LL_SPI_IsEnabledIT_TXP(SPIx);
3501 }
3502
3503 /**
3504 * @brief Check if Underrun IT is enabled
3505 * @rmtoll IER UDRIE LL_I2S_IsEnabledIT_UDR
3506 * @param SPIx SPI Instance
3507 * @retval State of bit (1 or 0)
3508 */
3509 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
3510 {
3511 return LL_SPI_IsEnabledIT_UDR(SPIx);
3512 }
3513
3514 /**
3515 * @brief Check if Overrun IT is enabled
3516 * @rmtoll IER OVRIE LL_I2S_IsEnabledIT_OVR
3517 * @param SPIx SPI Instance
3518 * @retval State of bit (1 or 0)
3519 */
3520 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
3521 {
3522 return LL_SPI_IsEnabledIT_OVR(SPIx);
3523 }
3524
3525 /**
3526 * @brief Check if TI Frame Format Error IT is enabled
3527 * @rmtoll IER TIFREIE LL_I2S_IsEnabledIT_FRE
3528 * @param SPIx SPI Instance
3529 * @retval State of bit (1 or 0)
3530 */
3531 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
3532 {
3533 return LL_SPI_IsEnabledIT_FRE(SPIx);
3534 }
3535
3536 /**
3537 * @}
3538 */
3539
3540 /** @defgroup I2S_LL_EF_DMA_Management DMA_Management
3541 * @{
3542 */
3543
3544 /**
3545 * @brief Enable DMA Rx
3546 * @rmtoll CFG1 RXDMAEN LL_I2S_EnableDMAReq_RX
3547 * @param SPIx SPI Instance
3548 * @retval None
3549 */
3550 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
3551 {
3552 LL_SPI_EnableDMAReq_RX(SPIx);
3553 }
3554
3555 /**
3556 * @brief Disable DMA Rx
3557 * @rmtoll CFG1 RXDMAEN LL_I2S_DisableDMAReq_RX
3558 * @param SPIx SPI Instance
3559 * @retval None
3560 */
3561 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
3562 {
3563 LL_SPI_DisableDMAReq_RX(SPIx);
3564 }
3565
3566 /**
3567 * @brief Check if DMA Rx is enabled
3568 * @rmtoll CFG1 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
3569 * @param SPIx SPI Instance
3570 * @retval State of bit (1 or 0)
3571 */
3572 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
3573 {
3574 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
3575 }
3576
3577 /**
3578 * @brief Enable DMA Tx
3579 * @rmtoll CFG1 TXDMAEN LL_I2S_EnableDMAReq_TX
3580 * @param SPIx SPI Instance
3581 * @retval None
3582 */
3583 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
3584 {
3585 LL_SPI_EnableDMAReq_TX(SPIx);
3586 }
3587
3588 /**
3589 * @brief Disable DMA Tx
3590 * @rmtoll CFG1 TXDMAEN LL_I2S_DisableDMAReq_TX
3591 * @param SPIx SPI Instance
3592 * @retval None
3593 */
3594 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
3595 {
3596 LL_SPI_DisableDMAReq_TX(SPIx);
3597 }
3598
3599 /**
3600 * @brief Check if DMA Tx is enabled
3601 * @rmtoll CFG1 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
3602 * @param SPIx SPI Instance
3603 * @retval State of bit (1 or 0)
3604 */
3605 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
3606 {
3607 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
3608 }
3609
3610 /**
3611 * @}
3612 */
3613
3614 /** @defgroup I2S_LL_EF_DATA_Management DATA_Management
3615 * @{
3616 */
3617
3618 /**
3619 * @brief Read Data Register
3620 * @rmtoll RXDR . LL_I2S_ReceiveData16
3621 * @param SPIx SPI Instance
3622 * @retval 0..0xFFFF
3623 */
3624 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
3625 {
3626 return LL_SPI_ReceiveData16(SPIx);
3627 }
3628
3629 /**
3630 * @brief Read Data Register
3631 * @rmtoll RXDR . LL_I2S_ReceiveData32
3632 * @param SPIx SPI Instance
3633 * @retval 0..0xFFFFFFFF
3634 */
3635 __STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx)
3636 {
3637 return LL_SPI_ReceiveData32(SPIx);
3638 }
3639
3640 /**
3641 * @brief Write Data Register
3642 * @rmtoll TXDR . LL_I2S_TransmitData16
3643 * @param SPIx SPI Instance
3644 * @param TxData 0..0xFFFF
3645 * @retval None
3646 */
3647 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
3648 {
3649 LL_SPI_TransmitData16(SPIx, TxData);
3650 }
3651
3652 /**
3653 * @brief Write Data Register
3654 * @rmtoll TXDR . LL_I2S_TransmitData32
3655 * @param SPIx SPI Instance
3656 * @param TxData 0..0xFFFFFFFF
3657 * @retval None
3658 */
3659 __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
3660 {
3661 LL_SPI_TransmitData32(SPIx, TxData);
3662 }
3663
3664 /**
3665 * @}
3666 */
3667
3668
3669 #if defined(USE_FULL_LL_DRIVER)
3670 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
3671 * @{
3672 */
3673
3674 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
3675 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
3676 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
3677 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
3678
3679 /**
3680 * @}
3681 */
3682 #endif /* USE_FULL_LL_DRIVER */
3683
3684 /**
3685 * @}
3686 */
3687
3688 /**
3689 * @}
3690 */
3691
3692 /**
3693 * @}
3694 */
3695 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
3696
3697 /**
3698 * @}
3699 */
3700
3701 /**
3702 * @}
3703 */
3704
3705 /**
3706 * @}
3707 */
3708 #ifdef __cplusplus
3709 }
3710 #endif
3711
3712 #endif /* STM32H7xx_LL_SPI_H */
3713
3714 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/