src/main/target/system_stm32f30x.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f30x.c
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    28-March-2014
   7   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   8   *          This file contains the system clock configuration for STM32F30x devices,
   9   *          and is generated by the clock configuration tool
  10   *          stm32f30x_Clock_Configuration_V1.0.0.xls
  11   *
  12   * 1.  This file provides two functions and one global variable to be called from
  13   *     user application:
  14   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  15   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
  16   *                      depending on the configuration made in the clock xls tool.
  17   *                      This function is called at startup just after reset and
  18   *                      before branch to main program. This call is made inside
  19   *                      the "startup_stm32f30x.s" file.
  20   *
  21   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  22   *                                  by the user application to setup the SysTick
  23   *                                  timer or configure other parameters.
  24   *
  25   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  26   *                                 be called whenever the core clock is changed
  27   *                                 during program execution.
  28   *
  29   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  30   *    Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
  31   *    configure the system clock before to branch to main program.
  32   *
  33   * 3. If the system clock source selected by user fails to startup, the SystemInit()
  34   *    function will do nothing and HSI still used as system clock source. User can
  35   *    add some code to deal with this issue inside the SetSysClock() function.
  36   *
  37   * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
  38   *    in "stm32f30x.h" file. When HSE is used as system clock source, directly or
  39   *    through PLL, and you are using different crystal you have to adapt the HSE
  40   *    value to your own configuration.
  41   *
  42   * 5. This file configures the system clock as follows:
  43   *=============================================================================
  44   *                         Supported STM32F30x device
  45   *-----------------------------------------------------------------------------
  46   *        System Clock source                    | PLL (HSE)
  47   *-----------------------------------------------------------------------------
  48   *        SYSCLK(Hz)                             | 72000000
  49   *-----------------------------------------------------------------------------
  50   *        HCLK(Hz)                               | 72000000
  51   *-----------------------------------------------------------------------------
  52   *        AHB Prescaler                          | 1
  53   *-----------------------------------------------------------------------------
  54   *        APB2 Prescaler                         | 2
  55   *-----------------------------------------------------------------------------
  56   *        APB1 Prescaler                         | 2
  57   *-----------------------------------------------------------------------------
  58   *        HSE Frequency(Hz)                      | 8000000
  59   *----------------------------------------------------------------------------
  60   *        PLLMUL                                 | 9
  61   *-----------------------------------------------------------------------------
  62   *        PREDIV                                 | 1
  63   *-----------------------------------------------------------------------------
  64   *        USB Clock                              | ENABLE
  65   *-----------------------------------------------------------------------------
  66   *        Flash Latency(WS)                      | 2
  67   *-----------------------------------------------------------------------------
  68   *        Prefetch Buffer                        | ON
  69   *-----------------------------------------------------------------------------
  70   *=============================================================================
  71   ******************************************************************************
  72   * @attention
  73   *
  74   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
  75   *
  76   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  77   * You may not use this file except in compliance with the License.
  78   * You may obtain a copy of the License at:
  79   *
  80   *        http://www.st.com/software_license_agreement_liberty_v2
  81   *
  82   * Unless required by applicable law or agreed to in writing, software
  83   * distributed under the License is distributed on an "AS IS" BASIS,
  84   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  85   * See the License for the specific language governing permissions and
  86   * limitations under the License.
  87   *
  88   ******************************************************************************
  89   */
  90 /** @addtogroup CMSIS
  91   * @{
  92   */
  93
  94 /** @addtogroup stm32f30x_system
  95   * @{
  96   */
  97
  98 /** @addtogroup STM32F30x_System_Private_Includes
  99   * @{
 100   */
 101
 102 #include "stm32f30x.h"
 103
 104 uint32_t hse_value = HSE_VALUE;
 105
 106 /**
 107   * @}
 108   */
 109
 110 /* Private typedef -----------------------------------------------------------*/
 111
 112 /** @addtogroup STM32F30x_System_Private_Defines
 113   * @{
 114   */
 115 /*!< Uncomment the following line if you need to relocate your vector Table in
 116      Internal SRAM. */
 117 /* #define VECT_TAB_SRAM */
 118 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
 119                                   This value must be a multiple of 0x200. */
 120 /**
 121   * @}
 122   */
 123
 124 /* Private macro -------------------------------------------------------------*/
 125
 126 /** @addtogroup STM32F30x_System_Private_Variables
 127   * @{
 128   */
 129
 130   uint32_t SystemCoreClock = 72000000;
 131
 132   __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 133
 134 /**
 135   * @}
 136   */
 137
 138 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
 139   * @{
 140   */
 141
 142 void SetSysClock(void);
 143
 144 /**
 145   * @}
 146   */
 147
 148 /** @addtogroup STM32F30x_System_Private_Functions
 149   * @{
 150   */
 151
 152 /**
 153   * @brief  Setup the microcontroller system
 154   *         Initialize the Embedded Flash Interface, the PLL and update the
 155   *         SystemFrequency variable.
 156   * @param  None
 157   * @retval None
 158   */
 159 void SystemInit(void)
 160 {
 161   /* FPU settings ------------------------------------------------------------*/
 162   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 163     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 164   #endif
 165
 166   /* Reset the RCC clock configuration to the default reset state ------------*/
 167   /* Set HSION bit */
 168   RCC->CR |= (uint32_t)0x00000001;
 169
 170   /* Reset CFGR register */
 171   RCC->CFGR &= 0xF87FC00C;
 172
 173   /* Reset HSEON, CSSON and PLLON bits */
 174   RCC->CR &= (uint32_t)0xFEF6FFFF;
 175
 176   /* Reset HSEBYP bit */
 177   RCC->CR &= (uint32_t)0xFFFBFFFF;
 178
 179   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
 180   RCC->CFGR &= (uint32_t)0xFF80FFFF;
 181
 182   /* Reset PREDIV1[3:0] bits */
 183   RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
 184
 185   /* Reset USARTSW[1:0], I2CSW and TIMs bits */
 186   RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
 187
 188   /* Disable all interrupts */
 189   RCC->CIR = 0x00000000;
 190
 191   /* Configure the System clock source, PLL Multiplier and Divider factors,
 192      AHB/APBx prescalers and Flash settings ----------------------------------*/
 193   //SetSysClock(); // called from main()
 194
 195 #ifdef VECT_TAB_SRAM
 196   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 197 #else
 198   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 199 #endif
 200 }
 201
 202 /**
 203    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 204   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 205   *         be used by the user application to setup the SysTick timer or configure
 206   *         other parameters.
 207   *
 208   * @note   Each time the core clock (HCLK) changes, this function must be called
 209   *         to update SystemCoreClock variable value. Otherwise, any configuration
 210   *         based on this variable will be incorrect.
 211   *
 212   * @note   - The system frequency computed by this function is not the real
 213   *           frequency in the chip. It is calculated based on the predefined
 214   *           constant and the selected clock source:
 215   *
 216   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 217   *
 218   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 219   *
 220   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 221   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 222   *
 223   *         (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
 224   *             8 MHz) but the real value may vary depending on the variations
 225   *             in voltage and temperature.
 226   *
 227   *         (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
 228   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 229   *              frequency of the crystal used. Otherwise, this function may
 230   *              have wrong result.
 231   *
 232   *         - The result of this function could be not correct when using fractional
 233   *           value for HSE crystal.
 234   *
 235   * @param  None
 236   * @retval None
 237   */
 238 void SystemCoreClockUpdate (void)
 239 {
 240   uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
 241
 242   /* Get SYSCLK source -------------------------------------------------------*/
 243   tmp = RCC->CFGR & RCC_CFGR_SWS;
 244
 245   switch (tmp)
 246   {
 247     case 0x00:  /* HSI used as system clock */
 248       SystemCoreClock = HSI_VALUE;
 249       break;
 250     case 0x04:  /* HSE used as system clock */
 251       SystemCoreClock = HSE_VALUE;
 252       break;
 253     case 0x08:  /* PLL used as system clock */
 254       /* Get PLL clock source and multiplication factor ----------------------*/
 255       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
 256       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 257       pllmull = ( pllmull >> 18) + 2;
 258
 259       if (pllsource == 0x00)
 260       {
 261         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
 262         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 263       }
 264       else
 265       {
 266         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
 267         /* HSE oscillator clock selected as PREDIV1 clock entry */
 268         SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
 269       }
 270       break;
 271     default: /* HSI used as system clock */
 272       SystemCoreClock = HSI_VALUE;
 273       break;
 274   }
 275   /* Compute HCLK clock frequency ----------------*/
 276   /* Get HCLK prescaler */
 277   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 278   /* HCLK clock frequency */
 279   SystemCoreClock >>= tmp;
 280 }
 281
 282 /**
 283   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 284   *               AHB/APBx prescalers and Flash settings
 285   * @note   This function should be called only once the RCC clock configuration
 286   *         is reset to the default reset state (done in SystemInit() function).
 287   * @param  None
 288   * @retval None
 289   */
 290 void SetSysClock(void)
 291 {
 292   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 293
 294 /******************************************************************************/
 295 /*            PLL (clocked by HSE) used as System clock source                */
 296 /******************************************************************************/
 297
 298   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
 299   /* Enable HSE */
 300   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 301
 302   /* Wait till HSE is ready and if Time out is reached exit */
 303   do
 304   {
 305     HSEStatus = RCC->CR & RCC_CR_HSERDY;
 306     StartUpCounter++;
 307   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 308
 309   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 310   {
 311     HSEStatus = (uint32_t)0x01;
 312   }
 313   else
 314   {
 315     HSEStatus = (uint32_t)0x00;
 316   }
 317
 318   if (HSEStatus == (uint32_t)0x01)
 319   {
 320     /* Enable Prefetch Buffer and set Flash Latency */
 321     FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
 322
 323      /* HCLK = SYSCLK / 1 */
 324      RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
 325
 326      /* PCLK2 = HCLK / 1 */
 327      RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
 328
 329      /* PCLK1 = HCLK / 2 */
 330      RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
 331
 332     /* PLL configuration */
 333     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
 334     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
 335
 336     /* Enable PLL */
 337     RCC->CR |= RCC_CR_PLLON;
 338
 339     /* Wait till PLL is ready */
 340     while((RCC->CR & RCC_CR_PLLRDY) == 0)
 341     {
 342     }
 343
 344     /* Select PLL as system clock source */
 345     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 346     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
 347
 348     /* Wait till PLL is used as system clock source */
 349     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
 350     {
 351     }
 352   }
 353   else
 354   { /* If HSE fails to start-up, the application will have wrong clock
 355          configuration. User can add here some code to deal with this error */
 356   }
 357 }
 358
 359 /**
 360   * @}
 361   */
 362
 363 /**
 364   * @}
 365   */
 366
 367 /**
 368   * @}
 369   */
 370
 371 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 372