src/main/drivers/dma_stm32h7xx.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <stdbool.h>
  22 #include <stdint.h>
  23 #include <string.h>
  24
  25 #include "platform.h"
  26
  27 #ifdef USE_DMA
  28
  29 #include "drivers/nvic.h"
  30 #include "drivers/dma.h"
  31 #include "drivers/rcc.h"
  32 #include "drivers/resource.h"
  33
  34 /*
  35  * DMA descriptors.
  36  */
  37 static dmaChannelDescriptor_t dmaDescriptors[DMA_LAST_HANDLER] = {
  38     DEFINE_DMA_CHANNEL(DMA1, 0,  0),
  39     DEFINE_DMA_CHANNEL(DMA1, 1,  6),
  40     DEFINE_DMA_CHANNEL(DMA1, 2, 16),
  41     DEFINE_DMA_CHANNEL(DMA1, 3, 22),
  42     DEFINE_DMA_CHANNEL(DMA1, 4, 32),
  43     DEFINE_DMA_CHANNEL(DMA1, 5, 38),
  44     DEFINE_DMA_CHANNEL(DMA1, 6, 48),
  45     DEFINE_DMA_CHANNEL(DMA1, 7, 54),
  46
  47     DEFINE_DMA_CHANNEL(DMA2, 0,  0),
  48     DEFINE_DMA_CHANNEL(DMA2, 1,  6),
  49     DEFINE_DMA_CHANNEL(DMA2, 2, 16),
  50     DEFINE_DMA_CHANNEL(DMA2, 3, 22),
  51     DEFINE_DMA_CHANNEL(DMA2, 4, 32),
  52     DEFINE_DMA_CHANNEL(DMA2, 5, 38),
  53     DEFINE_DMA_CHANNEL(DMA2, 6, 48),
  54     DEFINE_DMA_CHANNEL(DMA2, 7, 54),
  55 };
  56
  57 /*
  58  * DMA IRQ Handlers
  59  */
  60 DEFINE_DMA_IRQ_HANDLER(1, 0, DMA1_ST0_HANDLER)
  61 DEFINE_DMA_IRQ_HANDLER(1, 1, DMA1_ST1_HANDLER)
  62 DEFINE_DMA_IRQ_HANDLER(1, 2, DMA1_ST2_HANDLER)
  63 DEFINE_DMA_IRQ_HANDLER(1, 3, DMA1_ST3_HANDLER)
  64 DEFINE_DMA_IRQ_HANDLER(1, 4, DMA1_ST4_HANDLER)
  65 DEFINE_DMA_IRQ_HANDLER(1, 5, DMA1_ST5_HANDLER)
  66 DEFINE_DMA_IRQ_HANDLER(1, 6, DMA1_ST6_HANDLER)
  67 DEFINE_DMA_IRQ_HANDLER(1, 7, DMA1_ST7_HANDLER)
  68 DEFINE_DMA_IRQ_HANDLER(2, 0, DMA2_ST0_HANDLER)
  69 DEFINE_DMA_IRQ_HANDLER(2, 1, DMA2_ST1_HANDLER)
  70 DEFINE_DMA_IRQ_HANDLER(2, 2, DMA2_ST2_HANDLER)
  71 DEFINE_DMA_IRQ_HANDLER(2, 3, DMA2_ST3_HANDLER)
  72 DEFINE_DMA_IRQ_HANDLER(2, 4, DMA2_ST4_HANDLER)
  73 DEFINE_DMA_IRQ_HANDLER(2, 5, DMA2_ST5_HANDLER)
  74 DEFINE_DMA_IRQ_HANDLER(2, 6, DMA2_ST6_HANDLER)
  75 DEFINE_DMA_IRQ_HANDLER(2, 7, DMA2_ST7_HANDLER)
  76
  77 static void enableDmaClock(int index)
  78 {
  79     RCC_ClockCmd(dmaDescriptors[index].dma == DMA1 ? RCC_AHB1(DMA1) : RCC_AHB1(DMA2), ENABLE);
  80     // There seems to be no explicit control for DMAMUX1 clocking
  81 }
  82
  83 void dmaInit(dmaIdentifier_e identifier, resourceOwner_e owner, uint8_t resourceIndex)
  84 {
  85     const int index = DMA_IDENTIFIER_TO_INDEX(identifier);
  86
  87     enableDmaClock(index);
  88     dmaDescriptors[index].owner.owner = owner;
  89     dmaDescriptors[index].owner.resourceIndex = resourceIndex;
  90 }
  91
  92 void dmaSetHandler(dmaIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam)
  93 {
  94     const int index = DMA_IDENTIFIER_TO_INDEX(identifier);
  95
  96     enableDmaClock(index);
  97     dmaDescriptors[index].irqHandlerCallback = callback;
  98     dmaDescriptors[index].userParam = userParam;
  99
 100     HAL_NVIC_SetPriority(dmaDescriptors[index].irqN, NVIC_PRIORITY_BASE(priority), NVIC_PRIORITY_SUB(priority));
 101     HAL_NVIC_EnableIRQ(dmaDescriptors[index].irqN);
 102 }
 103
 104 const resourceOwner_t *dmaGetOwner(dmaIdentifier_e identifier)
 105 {
 106     return &dmaDescriptors[DMA_IDENTIFIER_TO_INDEX(identifier)].owner;
 107 }
 108
 109 dmaIdentifier_e dmaGetIdentifier(const dmaResource_t* stream)
 110 {
 111     for (int i = 0; i < DMA_LAST_HANDLER; i++) {
 112         if (dmaDescriptors[i].ref == stream) {
 113             return i + 1;
 114         }
 115     }
 116     return 0;
 117 }
 118
 119 dmaResource_t* dmaGetRefByIdentifier(const dmaIdentifier_e identifier)
 120 {
 121     return dmaDescriptors[DMA_IDENTIFIER_TO_INDEX(identifier)].ref;
 122 }
 123
 124 dmaChannelDescriptor_t* dmaGetDescriptorByIdentifier(const dmaIdentifier_e identifier)
 125 {
 126     return &dmaDescriptors[DMA_IDENTIFIER_TO_INDEX(identifier)];
 127 }
 128
 129 uint32_t dmaGetChannel(const uint8_t channel)
 130 {
 131     return ((uint32_t)channel*2)<<24;
 132 }
 133 #endif