src/main/drivers/bus.h

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #pragma once
  22
  23 #include "platform.h"
  24
  25 #include "drivers/bus_i2c.h"
  26 #include "drivers/io_types.h"
  27 #include "drivers/dma.h"
  28
  29 typedef enum {
  30     BUS_TYPE_NONE = 0,
  31     BUS_TYPE_I2C,
  32     BUS_TYPE_SPI,
  33     BUS_TYPE_MPU_SLAVE, // Slave I2C on SPI master
  34     BUS_TYPE_GYRO_AUTO,  // Only used by acc/gyro bus auto detection code
  35 } busType_e;
  36
  37 struct spiDevice_s;
  38
  39 typedef enum {
  40     BUS_READY,
  41     BUS_BUSY,
  42     BUS_ABORT
  43 } busStatus_e;
  44
  45
  46 // Bus interface, independent of connected device
  47 typedef struct busDevice_s {
  48     busType_e busType;
  49     union {
  50         struct busSpi_s {
  51             SPI_TypeDef *instance;
  52             uint16_t speed;
  53             bool leadingEdge;
  54         } spi;
  55         struct busI2C_s {
  56             I2CDevice device;
  57         } i2c;
  58         struct busMpuSlave_s {
  59             struct extDevice_s *master;
  60         } mpuSlave;
  61     } busType_u;
  62     bool useDMA;
  63     uint8_t deviceCount;
  64     dmaChannelDescriptor_t *dmaTx;
  65     dmaChannelDescriptor_t *dmaRx;
  66 #ifndef UNIT_TEST
  67     // Use a reference here as this saves RAM for unused descriptors
  68 #if defined(USE_FULL_LL_DRIVER)
  69     LL_DMA_InitTypeDef          *initTx;
  70     LL_DMA_InitTypeDef          *initRx;
  71 #else
  72     DMA_InitTypeDef             *initTx;
  73     DMA_InitTypeDef             *initRx;
  74 #endif
  75 #endif // UNIT_TEST
  76     volatile struct busSegment_s* volatile curSegment;
  77     bool initSegment;
  78 } busDevice_t;
  79
  80 // External device has an associated bus and bus dependent address
  81 typedef struct extDevice_s {
  82     busDevice_t *bus;
  83     union {
  84         struct extSpi_s {
  85             uint16_t speed;
  86             IO_t csnPin;
  87             bool leadingEdge;
  88         } spi;
  89         struct extI2C_s {
  90             uint8_t address;
  91         } i2c;
  92         struct extMpuSlave_s {
  93             uint8_t address;
  94         } mpuSlave;
  95     } busType_u;
  96 #ifndef UNIT_TEST
  97     // Cache the init structure for the next DMA transfer to reduce inter-segment delay
  98 #if defined(USE_FULL_LL_DRIVER)
  99     LL_DMA_InitTypeDef          initTx;
 100     LL_DMA_InitTypeDef          initRx;
 101 #else
 102     DMA_InitTypeDef             initTx;
 103     DMA_InitTypeDef             initRx;
 104 #endif
 105 #endif // UNIT_TEST
 106     // Support disabling DMA on a per device basis
 107     bool useDMA;
 108     // Per device buffer reference if needed
 109     uint8_t *txBuf, *rxBuf;
 110     // Connected devices on the same bus may support different speeds
 111     uint32_t callbackArg;
 112 } extDevice_t;
 113
 114 /* Each SPI access may comprise multiple parts, for example, wait/write enable/write/data each of which
 115  * is defined by a segment, with optional callback after each is completed.
 116  *
 117  * If there are more than one segments, or a single segment with negateCS negated then DMA will be used irrespective of length
 118  *
 119  */
 120 typedef struct busSegment_s {
 121     union {
 122         struct {
 123             // Transmit buffer
 124             uint8_t *txData;
 125             // Receive buffer, or in the case of the final segment to
 126             uint8_t *rxData;
 127         } buffers;
 128         struct {
 129             // Link to the device associated with the next transfer
 130             const extDevice_t *dev;
 131             // Segments to process in the next transfer.
 132             volatile struct busSegment_s *segments;
 133         } link;
 134     } u;
 135     int len;
 136     bool negateCS; // Should CS be negated at the end of this segment
 137     busStatus_e (*callback)(uint32_t arg);
 138 } busSegment_t;
 139
 140 #ifdef TARGET_BUS_INIT
 141 void targetBusInit(void);
 142 #endif
 143
 144 // Access routines where the register is accessed directly
 145 bool busRawWriteRegister(const extDevice_t *dev, uint8_t reg, uint8_t data);
 146 bool busRawWriteRegisterStart(const extDevice_t *dev, uint8_t reg, uint8_t data);
 147 bool busRawReadRegisterBuffer(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint8_t length);
 148 bool busRawReadRegisterBufferStart(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint8_t length);
 149 // Write routines where the register is masked with 0x7f
 150 bool busWriteRegister(const extDevice_t *dev, uint8_t reg, uint8_t data);
 151 bool busWriteRegisterStart(const extDevice_t *dev, uint8_t reg, uint8_t data);
 152 // Read routines where the register is ORed with 0x80
 153 bool busReadRegisterBuffer(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint8_t length);
 154 bool busReadRegisterBufferStart(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint8_t length);
 155 uint8_t busReadRegister(const extDevice_t *dev, uint8_t reg);
 156
 157 bool busBusy(const extDevice_t *dev, bool *error);
 158 void busDeviceRegister(const extDevice_t *dev);