src/main/startup/system_stm32f7xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f7xx.c
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    22-April-2016
   7   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
   8   *
   9   *   This file provides two functions and one global variable to be called from
  10   *   user application:
  11   *      - SystemInit(): This function is called at startup just after reset and
  12   *                      before branch to main program. This call is made inside
  13   *                      the "startup_stm32f7xx.s" file.
  14   *
  15   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16   *                                  by the user application to setup the SysTick
  17   *                                  timer or configure other parameters.
  18   *
  19   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20   *                                 be called whenever the core clock is changed
  21   *                                 during program execution.
  22   *
  23   *
  24   ******************************************************************************
  25   * @attention
  26   *
  27   * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
  28   *
  29   * Redistribution and use in source and binary forms, with or without modification,
  30   * are permitted provided that the following conditions are met:
  31   *   1. Redistributions of source code must retain the above copyright notice,
  32   *      this list of conditions and the following disclaimer.
  33   *   2. Redistributions in binary form must reproduce the above copyright notice,
  34   *      this list of conditions and the following disclaimer in the documentation
  35   *      and/or other materials provided with the distribution.
  36   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  37   *      may be used to endorse or promote products derived from this software
  38   *      without specific prior written permission.
  39   *
  40   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  41   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  42   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  43   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  44   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  45   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  46   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  47   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  48   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  49   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  50   *
  51   ******************************************************************************
  52   */
  53
  54 /** @addtogroup CMSIS
  55   * @{
  56   */
  57
  58 /** @addtogroup stm32f7xx_system
  59   * @{
  60   */
  61
  62 /** @addtogroup STM32F7xx_System_Private_Includes
  63   * @{
  64   */
  65
  66 #include "stm32f7xx.h"
  67 #include "system_stm32f7xx.h"
  68 #include "platform.h"
  69 #include "drivers/persistent.h"
  70
  71 #if !defined  (HSE_VALUE)
  72   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
  73 #endif /* HSE_VALUE */
  74
  75 #if !defined  (HSI_VALUE)
  76   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
  77 #endif /* HSI_VALUE */
  78
  79 #define PLL_M     8
  80 #define PLL_N     432
  81 #define PLL_P     RCC_PLLP_DIV2 /* 2 */
  82 #define PLL_Q     9
  83
  84 #define PLL_SAIN  384
  85 #define PLL_SAIQ  7
  86 #define PLL_SAIP  RCC_PLLSAIP_DIV8
  87
  88 /**
  89   * @}
  90   */
  91
  92 /** @addtogroup STM32F7xx_System_Private_TypesDefinitions
  93   * @{
  94   */
  95
  96 /**
  97   * @}
  98   */
  99
 100 /** @addtogroup STM32F7xx_System_Private_Defines
 101   * @{
 102   */
 103
 104 /**
 105   * @}
 106   */
 107
 108 /** @addtogroup STM32F7xx_System_Private_Macros
 109   * @{
 110   */
 111
 112 /**
 113   * @}
 114   */
 115
 116 /** @addtogroup STM32F7xx_System_Private_Variables
 117   * @{
 118   */
 119
 120   /* This variable is updated in three ways:
 121       1) by calling CMSIS function SystemCoreClockUpdate()
 122       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 123       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 124          Note: If you use this function to configure the system clock; then there
 125                is no need to call the 2 first functions listed above, since SystemCoreClock
 126                variable is updated automatically.
 127   */
 128   uint32_t SystemCoreClock;
 129   uint32_t pll_p = PLL_P, pll_n = PLL_N, pll_q = PLL_Q;
 130
 131   const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 132   const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
 133
 134 /**
 135   * @}
 136   */
 137
 138 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
 139   * @{
 140   */
 141
 142   /// TODO: F7 check if this is the best configuration for the clocks.
 143   // current settings are just a copy from one of the example projects
 144   void SystemClock_Config(void)
 145   {
 146       RCC_ClkInitTypeDef RCC_ClkInitStruct;
 147       RCC_OscInitTypeDef RCC_OscInitStruct;
 148       RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
 149       HAL_StatusTypeDef ret;
 150
 151       __HAL_RCC_PWR_CLK_ENABLE();
 152
 153       __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 154
 155 #ifdef CLOCK_SOURCE_USE_HSI
 156       /* Enable HSI Oscillator and activate PLL with HSI as source */
 157       RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI;
 158       RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
 159       RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
 160       RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
 161       RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI;
 162       RCC_OscInitStruct.PLL.PLLM             = 16;
 163       RCC_OscInitStruct.PLL.PLLN             = 432;
 164       RCC_OscInitStruct.PLL.PLLP             = RCC_PLLP_DIV2;
 165       RCC_OscInitStruct.PLL.PLLQ             = 9;
 166 #else
 167       /* Enable HSE Oscillator and activate PLL with HSE as source */
 168       RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
 169       RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 170       RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 171       RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 172       RCC_OscInitStruct.PLL.PLLM = PLL_M;
 173       RCC_OscInitStruct.PLL.PLLN = pll_n;
 174       RCC_OscInitStruct.PLL.PLLP = pll_p;
 175       RCC_OscInitStruct.PLL.PLLQ = pll_q;
 176 #endif
 177
 178       ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
 179       if (ret != HAL_OK) {
 180         while (1);
 181       }
 182
 183       /* Activate the OverDrive to reach the 216 MHz Frequency */
 184       ret = HAL_PWREx_EnableOverDrive();
 185       if (ret != HAL_OK) {
 186         while (1);
 187       }
 188       /* Select PLLSAI output as USB clock source */
 189       PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
 190       PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
 191       PeriphClkInitStruct.PLLSAI.PLLSAIN = PLL_SAIN;
 192       PeriphClkInitStruct.PLLSAI.PLLSAIQ = PLL_SAIQ;
 193       PeriphClkInitStruct.PLLSAI.PLLSAIP = PLL_SAIP;
 194       if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
 195         while (1);
 196       }
 197
 198       /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
 199       RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 200       RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 201       RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 202       RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
 203       RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 204
 205       ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
 206       if (ret != HAL_OK) {
 207         while (1);
 208       }
 209
 210       PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2
 211                                   |RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_USART6
 212                                   |RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_UART5
 213                                   |RCC_PERIPHCLK_UART7|RCC_PERIPHCLK_UART8
 214                                   |RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C3
 215                                   |RCC_PERIPHCLK_I2C2|RCC_PERIPHCLK_I2C4;
 216       PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
 217       PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
 218       PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
 219       PeriphClkInitStruct.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1;
 220       PeriphClkInitStruct.Uart5ClockSelection = RCC_UART5CLKSOURCE_PCLK1;
 221       PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
 222       PeriphClkInitStruct.Uart7ClockSelection = RCC_UART7CLKSOURCE_PCLK1;
 223       PeriphClkInitStruct.Uart8ClockSelection = RCC_UART8CLKSOURCE_PCLK1;
 224       PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
 225       PeriphClkInitStruct.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
 226       PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
 227       PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PCLK1;
 228       ret = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 229       if (ret != HAL_OK) {
 230           while (1);
 231       }
 232
 233       // Configure PLLI2S for 27MHz operation
 234       // Actual output will be done by mcoInit in drivers/mco.c
 235
 236       PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_PLLI2S;
 237       PeriphClkInitStruct.PLLI2S.PLLI2SN = 216;
 238       PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
 239       PeriphClkInitStruct.PLLI2S.PLLI2SQ = 2;
 240       PeriphClkInitStruct.PLLI2SDivQ = 1;
 241       if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 242       {
 243           while (1);
 244       }
 245
 246     // Activating the timerprescalers while the APBx prescalers are 1/2/4 will connect the TIMxCLK to HCLK which has been configured to 216MHz
 247     __HAL_RCC_TIMCLKPRESCALER(RCC_TIMPRES_ACTIVATED);
 248
 249     SystemCoreClockUpdate();
 250   }
 251
 252 typedef struct pllConfig_s {
 253   uint16_t n;
 254   uint16_t p;
 255   uint16_t q;
 256 } pllConfig_t;
 257
 258 static const pllConfig_t overclockLevels[] = {
 259   { PLL_N, PLL_P, PLL_Q },    // default
 260   { 480, RCC_PLLP_DIV2, 10 }, // 240 MHz
 261 };
 262
 263 void SystemInitOC(void) {
 264     uint32_t currentOverclockLevel = persistentObjectRead(PERSISTENT_OBJECT_OVERCLOCK_LEVEL);
 265
 266     if (currentOverclockLevel >= ARRAYLEN(overclockLevels)) {
 267       return;
 268     }
 269
 270     /* PLL setting for overclocking */
 271     const pllConfig_t * const pll = overclockLevels + currentOverclockLevel;
 272
 273     pll_n = pll->n;
 274     pll_p = pll->p;
 275     pll_q = pll->q;
 276 }
 277
 278 void OverclockRebootIfNecessary(uint32_t overclockLevel)
 279 {
 280     if (overclockLevel >= ARRAYLEN(overclockLevels)) {
 281         return;
 282     }
 283
 284     const pllConfig_t * const pll = overclockLevels + overclockLevel;
 285
 286     // Reboot to adjust overclock frequency
 287     if (SystemCoreClock != (pll->n / pll->p) * 1000000U) {
 288         persistentObjectWrite(PERSISTENT_OBJECT_OVERCLOCK_LEVEL, overclockLevel);
 289         __disable_irq();
 290         NVIC_SystemReset();
 291     }
 292 }
 293
 294 /**
 295   * @}
 296   */
 297
 298 /** @addtogroup STM32F7xx_System_Private_Functions
 299   * @{
 300   */
 301
 302 /**
 303   * @brief  Setup the microcontroller system
 304   *         Initialize the Embedded Flash Interface, the PLL and update the
 305   *         SystemFrequency variable.
 306   * @param  None
 307   * @retval None
 308   */
 309 void SystemInit(void)
 310 {
 311     SystemInitOC();
 312
 313     SystemCoreClock = (pll_n / pll_p) * 1000000;
 314
 315     /* FPU settings ------------------------------------------------------------*/
 316 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 317     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 318 #endif
 319     /* Reset the RCC clock configuration to the default reset state ------------*/
 320     /* Set HSION bit */
 321     RCC->CR |= (uint32_t)0x00000001;
 322
 323     /* Reset CFGR register */
 324     RCC->CFGR = 0x00000000;
 325
 326     /* Reset HSEON, CSSON and PLLON bits */
 327     RCC->CR &= (uint32_t)0xFEF6FFFF;
 328
 329     /* Reset PLLCFGR register */
 330     RCC->PLLCFGR = 0x24003010;
 331
 332     /* Reset HSEBYP bit */
 333     RCC->CR &= (uint32_t)0xFFFBFFFF;
 334
 335     /* Disable all interrupts */
 336     RCC->CIR = 0x00000000;
 337
 338     /* Configure the Vector Table location add offset address ------------------*/
 339     extern uint8_t isr_vector_table_base;
 340     const uint32_t vtorOffset = (uint32_t) &isr_vector_table_base;
 341 #define VTOR_OFFSET_ALIGNMENT 0x200
 342     if (vtorOffset % VTOR_OFFSET_ALIGNMENT != 0) {
 343         // ISR vector table base is not 512 byte aligned
 344         while (1);
 345     }
 346     SCB->VTOR = vtorOffset;
 347
 348     /* Enable I-Cache */
 349     if (INSTRUCTION_CACHE_ENABLE) {
 350         SCB_EnableICache();
 351     }
 352
 353     /* Enable D-Cache */
 354     if (DATA_CACHE_ENABLE) {
 355         SCB_EnableDCache();
 356     }
 357
 358     if (PREFETCH_ENABLE) {
 359         LL_FLASH_EnablePrefetch();
 360     }
 361
 362     /* Configure the system clock to specified frequency */
 363     SystemClock_Config();
 364
 365     if (SystemCoreClock != (pll_n / pll_p) * 1000000) {
 366         // There is a mismatch between the configured clock and the expected clock in portable.h
 367         while (1);
 368     }
 369 }
 370
 371 /**
 372    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 373   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 374   *         be used by the user application to setup the SysTick timer or configure
 375   *         other parameters.
 376   *
 377   * @note   Each time the core clock (HCLK) changes, this function must be called
 378   *         to update SystemCoreClock variable value. Otherwise, any configuration
 379   *         based on this variable will be incorrect.
 380   *
 381   * @note   - The system frequency computed by this function is not the real
 382   *           frequency in the chip. It is calculated based on the predefined
 383   *           constant and the selected clock source:
 384   *
 385   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 386   *
 387   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 388   *
 389   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 390   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 391   *
 392   *         (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
 393   *             16 MHz) but the real value may vary depending on the variations
 394   *             in voltage and temperature.
 395   *
 396   *         (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
 397   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
 398   *              frequency of the crystal used. Otherwise, this function may
 399   *              have wrong result.
 400   *
 401   *         - The result of this function could be not correct when using fractional
 402   *           value for HSE crystal.
 403   *
 404   * @param  None
 405   * @retval None
 406   */
 407 void SystemCoreClockUpdate(void)
 408 {
 409     uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
 410
 411     /* Get SYSCLK source -------------------------------------------------------*/
 412     tmp = RCC->CFGR & RCC_CFGR_SWS;
 413
 414     switch (tmp) {
 415     case 0x00:  /* HSI used as system clock source */
 416         SystemCoreClock = HSI_VALUE;
 417         break;
 418     case 0x04:  /* HSE used as system clock source */
 419         SystemCoreClock = HSE_VALUE;
 420         break;
 421     case 0x08:  /* PLL used as system clock source */
 422
 423         /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
 424          SYSCLK = PLL_VCO / PLL_P
 425          */
 426         pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 427         pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 428
 429         if (pllsource != 0) {
 430             /* HSE used as PLL clock source */
 431             pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 432         } else {
 433             /* HSI used as PLL clock source */
 434             pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 435         }
 436
 437         pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
 438         SystemCoreClock = pllvco/pllp;
 439         break;
 440     default:
 441         SystemCoreClock = HSI_VALUE;
 442         break;
 443     }
 444     /* Compute HCLK frequency --------------------------------------------------*/
 445     /* Get HCLK prescaler */
 446     tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 447     /* HCLK frequency */
 448     SystemCoreClock >>= tmp;
 449 }
 450
 451 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/