arch/arm/boards/edb93xx/sdram_cfg.c

   1 /*
   2  * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
   3  *
   4  * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include "sdram_cfg.h"
  28 #include "early_udelay.h"
  29
  30 #define PROGRAM_MODE_REG(bank)          (*(volatile uint32_t *)         \
  31                 (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
  32
  33 #define PRECHARGE_BANK(bank)            (*(volatile uint32_t *) \
  34                 (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0
  35
  36 static void precharge_all_banks(void);
  37 static void setup_refresh_timer(void);
  38 static void program_mode_registers(void);
  39
  40 void sdram_cfg(void)
  41 {
  42         struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
  43
  44         writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
  45
  46         /* Issue continous NOP commands */
  47         writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
  48
  49         early_udelay(200);
  50
  51         precharge_all_banks();
  52
  53         setup_refresh_timer();
  54
  55         program_mode_registers();
  56
  57         /* Select normal operation mode */
  58         writel(GLCONFIG_CKE, &sdram->glconfig);
  59 }
  60
  61 static void precharge_all_banks(void)
  62 {
  63         struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
  64
  65         /* Issue PRECHARGE ALL commands */
  66         writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig);
  67
  68         /*
  69          * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always
  70          * issued.
  71          *
  72          *  Cirrus proposes a workaround which consists in performing a read from
  73          * each bank to force the precharge. This causes some boards to hang.
  74          * Writing to the SDRAM banks instead of reading has the same
  75          * side-effect (the SDRAM controller issues the necessary precharges),
  76          * but is known to work on all supported boards
  77          */
  78
  79         PRECHARGE_BANK(0);
  80
  81 #if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2)
  82         PRECHARGE_BANK(1);
  83 #endif
  84
  85 #if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3)
  86         PRECHARGE_BANK(2);
  87 #endif
  88
  89 #if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4)
  90         PRECHARGE_BANK(3);
  91 #endif
  92 }
  93
  94 static void setup_refresh_timer(void)
  95 {
  96         struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
  97
  98         /* Load refresh timer with 10 to issue refresh every 10 cycles */
  99         writel(0x0a, &sdram->refrshtimr);
 100
 101         /*
 102          * Wait at least 80 clock cycles to provide 8 refresh cycles
 103          * to all SDRAMs
 104          */
 105         early_udelay(1);
 106
 107         /*
 108          * Program refresh timer with normal value
 109          * We need 8192 refresh cycles every 64ms
 110          * at 15ns (HCLK >= 66MHz) per cycle:
 111          * 64ms / 8192 = 7.8125us
 112          * 7.8125us / 15ns = 520 (0x208)
 113          */
 114         /*
 115          * TODO: redboot uses 0x1e0 for the slowest possible device
 116          * but i don't understand how this value is calculated
 117          */
 118         writel(0x208, &sdram->refrshtimr);
 119 }
 120
 121 static void program_mode_registers(void)
 122 {
 123         struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
 124
 125         /* Select mode register update mode */
 126         writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
 127
 128         PROGRAM_MODE_REG(0);
 129
 130 #if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2)
 131         PROGRAM_MODE_REG(1);
 132 #endif
 133
 134 #if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3)
 135         PROGRAM_MODE_REG(2);
 136 #endif
 137
 138 #if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4)
 139         PROGRAM_MODE_REG(3);
 140 #endif
 141 }