board/pcm030/pcm030.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2006
   9  * Eric Schumann, Phytec Messtechnik GmbH
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <common.h>
  31 #include <driver.h>
  32 #include <cfi_flash.h>
  33 #include <init.h>
  34 #include <asm/arch/mpc5xxx.h>
  35 #include <asm/arch/fec.h>
  36 #include <types.h>
  37 #include <partition.h>
  38 #include <mem_malloc.h>
  39 #include <reloc.h>
  40
  41 #ifdef CONFIG_VIDEO_OPENIP
  42 #include <openip.h>
  43 #endif
  44
  45 struct device_d cfi_dev = {
  46         .name     = "cfi_flash",
  47         .map_base = 0xff000000,
  48         .size     = 16 * 1024 * 1024,
  49 };
  50
  51 static struct memory_platform_data ram_pdata = {
  52         .name = "ram0",
  53         .flags = DEVFS_RDWR,
  54 };
  55
  56 struct device_d sdram_dev = {
  57         .name     = "mem",
  58         .map_base = 0x0,
  59         .size     = 64 * 1024 * 1024,
  60         .platform_data = &ram_pdata,
  61 };
  62
  63 static struct mpc5xxx_fec_platform_data fec_info = {
  64         .xcv_type = MII100,
  65 };
  66
  67 struct device_d eth_dev = {
  68         .name           = "fec_mpc5xxx",
  69         .map_base       = MPC5XXX_FEC,
  70         .platform_data  = &fec_info,
  71 };
  72
  73 static int devices_init (void)
  74 {
  75         register_device(&cfi_dev);
  76         register_device(&sdram_dev);
  77         register_device(&eth_dev);
  78
  79         devfs_add_partition("nor0", 0x00f00000, 0x40000, PARTITION_FIXED, "self0");
  80         devfs_add_partition("nor0", 0x00f60000, 0x20000, PARTITION_FIXED, "env0");
  81
  82         return 0;
  83 }
  84
  85 device_initcall(devices_init);
  86
  87 static struct device_d psc3 = {
  88         .name     = "mpc5xxx_serial",
  89         .map_base = MPC5XXX_PSC3,
  90         .size     = 4096,
  91 };
  92
  93 static struct device_d psc6 = {
  94         .name     = "mpc5xxx_serial",
  95         .map_base = MPC5XXX_PSC6,
  96         .size     = 4096,
  97 };
  98
  99 static int console_init(void)
 100 {
 101         register_device(&psc3);
 102         register_device(&psc6);
 103         return 0;
 104 }
 105
 106 console_initcall(console_init);
 107
 108 void *get_early_console_base(const char *name)
 109 {
 110         if (!strcmp(name, RELOC("psc3")))
 111                 return (void *)MPC5XXX_PSC3;
 112         if (!strcmp(name, RELOC("psc6")))
 113                 return (void *)MPC5XXX_PSC6;
 114         return NULL;
 115 }
 116
 117 #include "mt46v32m16-75.h"
 118
 119 static void sdram_start (int hi_addr)
 120 {
 121         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
 122
 123         /* unlock mode register */
 124         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
 125         __asm__ volatile ("sync");
 126
 127         /* precharge all banks */
 128         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 129         __asm__ volatile ("sync");
 130
 131 #if SDRAM_DDR
 132         /* set mode register: extended mode */
 133         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
 134         __asm__ volatile ("sync");
 135
 136         /* set mode register: reset DLL */
 137         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
 138         __asm__ volatile ("sync");
 139 #endif
 140
 141         /* precharge all banks */
 142         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 143         __asm__ volatile ("sync");
 144
 145         /* auto refresh */
 146         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
 147         __asm__ volatile ("sync");
 148
 149         /* set mode register */
 150         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
 151         __asm__ volatile ("sync");
 152
 153         /* normal operation */
 154         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
 155         __asm__ volatile ("sync");
 156 }
 157
 158 /*
 159  * ATTENTION: Although partially referenced initdram does NOT make real use
 160  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
 161  *            is something else than 0x00000000.
 162  */
 163
 164 long int initdram (int board_type)
 165 {
 166         ulong dramsize = 0;
 167         ulong dramsize2 = 0;
 168
 169         ulong test1, test2;
 170
 171         if ((ulong)RELOC(initdram) > (2 << 30)) {
 172                 /* setup SDRAM chip selects */
 173                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
 174                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
 175                 __asm__ volatile ("sync");
 176
 177                 /* setup config registers */
 178                 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 179                 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 180                 __asm__ volatile ("sync");
 181
 182 #if SDRAM_DDR && SDRAM_TAPDELAY
 183                 /* set tap delay */
 184                 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 185                 __asm__ volatile ("sync");
 186 #endif
 187
 188                 /* find RAM size using SDRAM CS0 only */
 189                 sdram_start(0);
 190                 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x10000000);
 191                 sdram_start(1);
 192                 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x10000000);
 193                 if (test1 > test2) {
 194                         sdram_start(0);
 195                         dramsize = test1;
 196                 } else {
 197                         dramsize = test2;
 198                 }
 199
 200                 /* memory smaller than 1MB is impossible */
 201                 if (dramsize < (1 << 20)) {
 202                         dramsize = 0;
 203                 }
 204
 205                 /* set SDRAM CS0 size according to the amount of RAM found */
 206                 if (dramsize > 0) {
 207                         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 208                 } else {
 209                         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 210                 }
 211         } else
 212                 puts(RELOC("skipping sdram initialization\n"));
 213
 214         /* retrieve size of memory connected to SDRAM CS0 */
 215         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 216         if (dramsize >= 0x13) {
 217                 dramsize = (1 << (dramsize - 0x13)) << 20;
 218         } else {
 219                 dramsize = 0;
 220         }
 221
 222         /* retrieve size of memory connected to SDRAM CS1 */
 223         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 224         if (dramsize2 >= 0x13) {
 225                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 226         } else {
 227                 dramsize2 = 0;
 228         }
 229
 230         return dramsize + dramsize2;
 231 }
 232
 233 #ifdef  CONFIG_PCI
 234 static struct pci_controller hose;
 235
 236 extern void pci_mpc5xxx_init(struct pci_controller *);
 237
 238 void pci_init_board(void)
 239 {
 240         pci_mpc5xxx_init(&hose);
 241 }
 242 #endif
 243
 244 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 245 void
 246 ft_board_setup(void *blob, bd_t *bd)
 247 {
 248         ft_cpu_setup(blob, bd);
 249 }
 250 #endif
 251
 252 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
 253
 254 #define GPIO_PSC2_4     0x02000000UL
 255
 256 void init_ide_reset (void)
 257 {
 258         debug ("init_ide_reset\n");
 259
 260         /* Configure PSC2_4 as GPIO output for ATA reset */
 261         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC2_4;
 262         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC2_4;
 263         /* Deassert reset */
 264         *(vu_long *) MPC5XXX_WU_GPIO_DATA   |= GPIO_PSC2_4;
 265 }
 266
 267 void ide_set_reset (int idereset)
 268 {
 269         debug ("ide_reset(%d)\n", idereset);
 270
 271         if (idereset) {
 272                 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC2_4;
 273                 /* Make a delay. MPC5200 spec says 25 usec min */
 274                 udelay(500000);
 275         } else {
 276                 *(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC2_4;
 277         }
 278 }
 279 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
 280
 281 #ifdef CONFIG_VIDEO_OPENIP
 282
 283 #define DISPLAY_WIDTH   320
 284 #define DISPLAY_HEIGHT  240
 285
 286 #ifdef CONFIG_VIDEO_OPENIP_8BPP
 287 #error CONFIG_VIDEO_OPENIP_8BPP not supported.
 288 #endif /* CONFIG_VIDEO_OPENIP_8BPP */
 289
 290 #ifdef CONFIG_VIDEO_OPENIP_16BPP
 291 #error CONFIG_VIDEO_OPENIP_16BPP not supported.
 292 #endif /* CONFIG_VIDEO_OPENIP_16BPP */
 293 #ifdef CONFIG_VIDEO_OPENIP_32BPP
 294
 295
 296
 297 static const SMI_REGS init_regs [] =
 298 {
 299         {0x00008, 0x0248013f},
 300         {0x0000c, 0x021100f0},
 301         {0x00010, 0x018c0106},
 302         {0x00014, 0x00800000},
 303         {0x00018, 0x00800000},
 304         {0x00000, 0x00003701},
 305         {0, 0}
 306 };
 307 #endif /* CONFIG_VIDEO_OPENIP_32BPP */
 308
 309 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 310 /*
 311  * Return text to be printed besides the logo.
 312  */
 313 void video_get_info_str (int line_number, char *info)
 314 {
 315         if (line_number == 1) {
 316                 strcpy (info, " Board: phyCORE-MPC5200B tiny (Phytec Messtechnik GmbH)");
 317         } else if (line_number == 2) {
 318                 strcpy (info, "    on a PCM-980 baseboard");
 319         }
 320         else {
 321                 info [0] = '\0';
 322         }
 323 }
 324 #endif
 325
 326 /*
 327  * Returns OPENIP register base address. First thing called in the driver.
 328  */
 329 unsigned int board_video_init (void)
 330 {
 331 ulong dummy;
 332 dummy  = *(vu_long *)OPENIP_MMIO_BASE; /*dummy read*/
 333 dummy  = *(vu_long *)OPENIP_MMIO_BASE; /*dummy read*/
 334         return OPENIP_MMIO_BASE;
 335 }
 336
 337 /*
 338  * Returns OPENIP framebuffer address
 339  */
 340 unsigned int board_video_get_fb (void)
 341 {
 342
 343         return OPENIP_FB_BASE;
 344 }
 345
 346 /*
 347  * Called after initializing the OPENIP and before clearing the screen.
 348  */
 349 void board_validate_screen (unsigned int base)
 350 {
 351 }
 352
 353 /*
 354  * Return a pointer to the initialization sequence.
 355  */
 356 const SMI_REGS *board_get_regs (void)
 357 {
 358         return init_regs;
 359 }
 360
 361 int board_get_width (void)
 362 {
 363         return DISPLAY_WIDTH;
 364 }
 365
 366 int board_get_height (void)
 367 {
 368         return DISPLAY_HEIGHT;
 369 }
 370
 371 #endif /* CONFIG_VIDEO_OPENIP */