drivers/nand/atmel_nand.c

   1 /*
   2  *  Copyright (C) 2003 Rick Bronson
   3  *
   4  *  Derived from drivers/mtd/nand/autcpu12.c
   5  *       Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
   6  *
   7  *  Derived from drivers/mtd/spia.c
   8  *       Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
   9  *
  10  *
  11  *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  12  *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
  13  *
  14  *     Derived from Das U-Boot source code
  15  *              (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  16  *     (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  17  *
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  *
  23  */
  24
  25 #include <common.h>
  26 #include <driver.h>
  27 #include <malloc.h>
  28 #include <init.h>
  29 #include <gpio.h>
  30
  31 #include <linux/mtd/mtd.h>
  32 #include <linux/mtd/nand.h>
  33
  34 #include <asm/io.h>
  35 #include <asm/arch/atmel_nand.h>
  36
  37 #include <errno.h>
  38
  39 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
  40 #define hard_ecc        1
  41 #else
  42 #define hard_ecc        0
  43 #endif
  44
  45 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
  46 #define no_ecc          1
  47 #else
  48 #define no_ecc          0
  49 #endif
  50
  51 /* Register access macros */
  52 #define ecc_readl(add, reg)                             \
  53         readl(add + ATMEL_ECC_##reg)
  54 #define ecc_writel(add, reg, value)                     \
  55         writel((value), add + ATMEL_ECC_##reg)
  56
  57 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  58
  59 /* oob layout for large page size
  60  * bad block info is on bytes 0 and 1
  61  * the bytes have to be consecutives to avoid
  62  * several NAND_CMD_RNDOUT during read
  63  */
  64 static struct nand_ecclayout atmel_oobinfo_large = {
  65         .eccbytes = 4,
  66         .eccpos = {60, 61, 62, 63},
  67         .oobfree = {
  68                 {2, 58}
  69         },
  70 };
  71
  72 /* oob layout for small page size
  73  * bad block info is on bytes 4 and 5
  74  * the bytes have to be consecutives to avoid
  75  * several NAND_CMD_RNDOUT during read
  76  */
  77 static struct nand_ecclayout atmel_oobinfo_small = {
  78         .eccbytes = 4,
  79         .eccpos = {0, 1, 2, 3},
  80         .oobfree = {
  81                 {6, 10}
  82         },
  83 };
  84
  85 struct atmel_nand_host {
  86         struct nand_chip        nand_chip;
  87         struct mtd_info         mtd;
  88         void __iomem            *io_base;
  89         struct atmel_nand_data  *board;
  90         struct device_d         *dev;
  91         void __iomem            *ecc;
  92 };
  93
  94 /*
  95  * Enable NAND.
  96  */
  97 static void atmel_nand_enable(struct atmel_nand_host *host)
  98 {
  99         if (host->board->enable_pin)
 100                 gpio_set_value(host->board->enable_pin, 0);
 101 }
 102
 103 /*
 104  * Disable NAND.
 105  */
 106 static void atmel_nand_disable(struct atmel_nand_host *host)
 107 {
 108         if (host->board->enable_pin)
 109                 gpio_set_value(host->board->enable_pin, 1);
 110 }
 111
 112 /*
 113  * Hardware specific access to control-lines
 114  */
 115 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 116 {
 117         struct nand_chip *nand_chip = mtd->priv;
 118         struct atmel_nand_host *host = nand_chip->priv;
 119
 120         if (ctrl & NAND_CTRL_CHANGE) {
 121                 if (ctrl & NAND_NCE)
 122                         atmel_nand_enable(host);
 123                 else
 124                         atmel_nand_disable(host);
 125         }
 126         if (cmd == NAND_CMD_NONE)
 127                 return;
 128
 129         if (ctrl & NAND_CLE)
 130                 writeb(cmd, host->io_base + (1 << host->board->cle));
 131         else
 132                 writeb(cmd, host->io_base + (1 << host->board->ale));
 133 }
 134
 135 /*
 136  * Read the Device Ready pin.
 137  */
 138 static int atmel_nand_device_ready(struct mtd_info *mtd)
 139 {
 140         struct nand_chip *nand_chip = mtd->priv;
 141         struct atmel_nand_host *host = nand_chip->priv;
 142
 143         return gpio_get_value(host->board->rdy_pin);
 144 }
 145
 146 /*
 147  * Minimal-overhead PIO for data access.
 148  */
 149 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 150 {
 151         struct nand_chip        *nand_chip = mtd->priv;
 152
 153         readsb(nand_chip->IO_ADDR_R, buf, len);
 154 }
 155
 156 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
 157 {
 158         struct nand_chip        *nand_chip = mtd->priv;
 159
 160         readsw(nand_chip->IO_ADDR_R, buf, len / 2);
 161 }
 162
 163 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 164 {
 165         struct nand_chip        *nand_chip = mtd->priv;
 166
 167         writesb(nand_chip->IO_ADDR_W, buf, len);
 168 }
 169
 170 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
 171 {
 172         struct nand_chip        *nand_chip = mtd->priv;
 173
 174         writesw(nand_chip->IO_ADDR_W, buf, len / 2);
 175 }
 176
 177 /*
 178  * Calculate HW ECC
 179  *
 180  * function called after a write
 181  *
 182  * mtd:        MTD block structure
 183  * dat:        raw data (unused)
 184  * ecc_code:   buffer for ECC
 185  */
 186 static int atmel_nand_calculate(struct mtd_info *mtd,
 187                 const u_char *dat, unsigned char *ecc_code)
 188 {
 189         struct nand_chip *nand_chip = mtd->priv;
 190         struct atmel_nand_host *host = nand_chip->priv;
 191 /*      uint32_t *eccpos = nand_chip->ecc.layout->eccpos; */
 192         unsigned int ecc_value;
 193
 194         /* get the first 2 ECC bytes */
 195         ecc_value = ecc_readl(host->ecc, PR);
 196
 197         ecc_code[0] = ecc_value & 0xFF;
 198         ecc_code[1] = (ecc_value >> 8) & 0xFF;
 199
 200         /* get the last 2 ECC bytes */
 201         ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
 202
 203         ecc_code[2] = ecc_value & 0xFF;
 204         ecc_code[3] = (ecc_value >> 8) & 0xFF;
 205
 206         return 0;
 207 }
 208
 209 /*
 210  * HW ECC read page function
 211  *
 212  * mtd:        mtd info structure
 213  * chip:       nand chip info structure
 214  * buf:        buffer to store read data
 215  */
 216 static int atmel_nand_read_page(struct mtd_info *mtd,
 217                 struct nand_chip *chip, uint8_t *buf)
 218 {
 219         int eccsize = chip->ecc.size;
 220         int eccbytes = chip->ecc.bytes;
 221         uint32_t *eccpos = chip->ecc.layout->eccpos;
 222         uint8_t *p = buf;
 223         uint8_t *oob = chip->oob_poi;
 224         uint8_t *ecc_pos;
 225         int stat;
 226
 227         /*
 228          * Errata: ALE is incorrectly wired up to the ECC controller
 229          * on the AP7000, so it will include the address cycles in the
 230          * ECC calculation.
 231          *
 232          * Workaround: Reset the parity registers before reading the
 233          * actual data.
 234          */
 235 #if 0
 236         if (cpu_is_at32ap7000()) {
 237                 struct atmel_nand_host *host = chip->priv;
 238                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
 239         }
 240 #endif
 241
 242         /* read the page */
 243         chip->read_buf(mtd, p, eccsize);
 244
 245         /* move to ECC position if needed */
 246         if (eccpos[0] != 0) {
 247                 /* This only works on large pages
 248                  * because the ECC controller waits for
 249                  * NAND_CMD_RNDOUTSTART after the
 250                  * NAND_CMD_RNDOUT.
 251                  * anyway, for small pages, the eccpos[0] == 0
 252                  */
 253                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
 254                                 mtd->writesize + eccpos[0], -1);
 255         }
 256
 257         /* the ECC controller needs to read the ECC just after the data */
 258         ecc_pos = oob + eccpos[0];
 259         chip->read_buf(mtd, ecc_pos, eccbytes);
 260
 261         /* check if there's an error */
 262         stat = chip->ecc.correct(mtd, p, oob, NULL);
 263
 264         if (stat < 0)
 265                 mtd->ecc_stats.failed++;
 266         else
 267                 mtd->ecc_stats.corrected += stat;
 268
 269         /* get back to oob start (end of page) */
 270         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 271
 272         /* read the oob */
 273         chip->read_buf(mtd, oob, mtd->oobsize);
 274
 275         return 0;
 276 }
 277
 278 /*
 279  * HW ECC Correction
 280  *
 281  * function called after a read
 282  *
 283  * mtd:        MTD block structure
 284  * dat:        raw data read from the chip
 285  * read_ecc:   ECC from the chip (unused)
 286  * isnull:     unused
 287  *
 288  * Detect and correct a 1 bit error for a page
 289  */
 290 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
 291                 u_char *read_ecc, u_char *isnull)
 292 {
 293         struct nand_chip *nand_chip = mtd->priv;
 294         struct atmel_nand_host *host = nand_chip->priv;
 295         unsigned int ecc_status;
 296         unsigned int ecc_word, ecc_bit;
 297
 298         /* get the status from the Status Register */
 299         ecc_status = ecc_readl(host->ecc, SR);
 300
 301         /* if there's no error */
 302         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
 303                 return 0;
 304
 305         /* get error bit offset (4 bits) */
 306         ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
 307         /* get word address (12 bits) */
 308         ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
 309         ecc_word >>= 4;
 310
 311         /* if there are multiple errors */
 312         if (ecc_status & ATMEL_ECC_MULERR) {
 313                 /* check if it is a freshly erased block
 314                  * (filled with 0xff) */
 315                 if ((ecc_bit == ATMEL_ECC_BITADDR)
 316                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
 317                         /* the block has just been erased, return OK */
 318                         return 0;
 319                 }
 320                 /* it doesn't seems to be a freshly
 321                  * erased block.
 322                  * We can't correct so many errors */
 323                 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
 324                                 " Unable to correct.\n");
 325                 return -EIO;
 326         }
 327
 328         /* if there's a single bit error : we can correct it */
 329         if (ecc_status & ATMEL_ECC_ECCERR) {
 330                 /* there's nothing much to do here.
 331                  * the bit error is on the ECC itself.
 332                  */
 333                 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
 334                                 " Nothing to correct\n");
 335                 return 0;
 336         }
 337
 338         dev_dbg(host->dev, "atmel_nand : one bit error on data."
 339                         " (word offset in the page :"
 340                         " 0x%x bit offset : 0x%x)\n",
 341                         ecc_word, ecc_bit);
 342         /* correct the error */
 343         if (nand_chip->options & NAND_BUSWIDTH_16) {
 344                 /* 16 bits words */
 345                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
 346         } else {
 347                 /* 8 bits words */
 348                 dat[ecc_word] ^= (1 << ecc_bit);
 349         }
 350         dev_dbg(host->dev, "atmel_nand : error corrected\n");
 351         return 1;
 352 }
 353
 354 /*
 355  * Enable HW ECC : unused on most chips
 356  */
 357 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
 358 {
 359 #if 0
 360         if (cpu_is_at32ap7000()) {
 361                 struct nand_chip *nand_chip = mtd->priv;
 362                 struct atmel_nand_host *host = nand_chip->priv;
 363                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
 364         }
 365 #endif
 366 }
 367
 368 /*
 369  * Probe for the NAND device.
 370  */
 371 static int __init atmel_nand_probe(struct device_d *dev)
 372 {
 373         struct atmel_nand_data *pdata = dev->platform_data;
 374         struct atmel_nand_host *host;
 375         struct mtd_info *mtd;
 376         struct nand_chip *nand_chip;
 377         int res = 0;
 378
 379         /* Allocate memory for the device structure (and zero it) */
 380         host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
 381         if (!host)
 382                 return -ENOMEM;
 383
 384         host->io_base = (void __iomem *)dev->map_base;
 385
 386         mtd = &host->mtd;
 387         nand_chip = &host->nand_chip;
 388         host->board = pdata;
 389         host->dev = dev;
 390
 391         nand_chip->priv = host;         /* link the private data structures */
 392         mtd->priv = nand_chip;
 393
 394         /* Set address of NAND IO lines */
 395         nand_chip->IO_ADDR_R = host->io_base;
 396         nand_chip->IO_ADDR_W = host->io_base;
 397         nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
 398
 399         if (host->board->rdy_pin)
 400                 nand_chip->dev_ready = atmel_nand_device_ready;
 401
 402         nand_chip->ecc.mode = pdata->ecc_mode;
 403
 404         if (pdata->ecc_mode == NAND_ECC_HW) {
 405                 if (!pdata->ecc_base)
 406                         return -ENODEV;
 407
 408                 host->ecc = pdata->ecc_base;
 409
 410                 nand_chip->ecc.mode = NAND_ECC_HW;
 411                 nand_chip->ecc.calculate = atmel_nand_calculate;
 412                 nand_chip->ecc.correct = atmel_nand_correct;
 413                 nand_chip->ecc.hwctl = atmel_nand_hwctl;
 414                 nand_chip->ecc.read_page = atmel_nand_read_page;
 415                 nand_chip->ecc.bytes = 4;
 416         }
 417
 418         nand_chip->chip_delay = 20;             /* 20us command delay time */
 419
 420         if (host->board->bus_width_16) {        /* 16-bit bus width */
 421                 nand_chip->options |= NAND_BUSWIDTH_16;
 422                 nand_chip->read_buf = atmel_read_buf16;
 423                 nand_chip->write_buf = atmel_write_buf16;
 424         } else {
 425                 nand_chip->read_buf = atmel_read_buf;
 426                 nand_chip->write_buf = atmel_write_buf;
 427         }
 428
 429         atmel_nand_enable(host);
 430
 431         if (host->board->det_pin) {
 432                 if (gpio_get_value(host->board->det_pin)) {
 433                         printk("No SmartMedia card inserted.\n");
 434                         res = ENXIO;
 435                         goto err_no_card;
 436                 }
 437         }
 438
 439         /* first scan to find the device and get the page size */
 440         if (nand_scan_ident(mtd, 1)) {
 441                 res = -ENXIO;
 442                 goto err_scan_ident;
 443         }
 444
 445         if (nand_chip->ecc.mode == NAND_ECC_HW) {
 446                 /* ECC is calculated for the whole page (1 step) */
 447                 nand_chip->ecc.size = mtd->writesize;
 448
 449                 /* set ECC page size and oob layout */
 450                 switch (mtd->writesize) {
 451                 case 512:
 452                         nand_chip->ecc.layout = &atmel_oobinfo_small;
 453                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
 454                         break;
 455                 case 1024:
 456                         nand_chip->ecc.layout = &atmel_oobinfo_large;
 457                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
 458                         break;
 459                 case 2048:
 460                         nand_chip->ecc.layout = &atmel_oobinfo_large;
 461                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
 462                         break;
 463                 case 4096:
 464                         nand_chip->ecc.layout = &atmel_oobinfo_large;
 465                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
 466                         break;
 467                 default:
 468                         /* page size not handled by HW ECC */
 469                         /* switching back to soft ECC */
 470                         nand_chip->ecc.mode = NAND_ECC_SOFT;
 471                         nand_chip->ecc.calculate = NULL;
 472                         nand_chip->ecc.correct = NULL;
 473                         nand_chip->ecc.hwctl = NULL;
 474                         nand_chip->ecc.read_page = NULL;
 475                         nand_chip->ecc.postpad = 0;
 476                         nand_chip->ecc.prepad = 0;
 477                         nand_chip->ecc.bytes = 0;
 478                         break;
 479                 }
 480         }
 481
 482         /* second phase scan */
 483         if (nand_scan_tail(mtd)) {
 484                 res = -ENXIO;
 485                 goto err_scan_tail;
 486         }
 487
 488         add_mtd_device(mtd);
 489
 490         if (!res)
 491                 return res;
 492
 493         nand_release(mtd);
 494 err_scan_tail:
 495 err_scan_ident:
 496 err_no_card:
 497         atmel_nand_disable(host);
 498         kfree(host);
 499         return res;
 500 }
 501
 502 static struct driver_d atmel_nand_driver = {
 503         .name   = "atmel_nand",
 504         .probe  = atmel_nand_probe,
 505 };
 506
 507 static int __init atmel_nand_init(void)
 508 {
 509         return register_driver(&atmel_nand_driver);
 510 }
 511
 512 device_initcall(atmel_nand_init);
 513
 514 MODULE_LICENSE("GPL");
 515 MODULE_AUTHOR("Rick Bronson");
 516 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");