3 * @brief SDP3430 Specific Board Initialization routines
5 * FileName: board/omap/board-sdp343x.c
7 * SDP3430 from Texas Instruments as described here:
8 * http://www.ti.com/omap3430_devplatform
9 * This file provides initialization in two stages:
10 * @li boot time initialization - do basics required to get SDRAM working.
11 * This is run from SRAM - so no case constructs and global vars can be used.
12 * @li run time initialization - this is for the rest of the initializations
13 * such as flash, uart etc.
15 * Boot time initialization includes:
16 * @li SDRAM initialization.
17 * @li Pin Muxing relevant for SDP3430.
19 * Run time initialization includes
20 * @li serial @ref serial_ns16550.c driver device definition
22 * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
25 * (C) Copyright 2006-2008
26 * Texas Instruments, <www.ti.com>
27 * Nishanth Menon <x0nishan@ti.com>
29 * This program is free software; you can redistribute it and/or
30 * modify it under the terms of the GNU General Public License as
31 * published by the Free Software Foundation; either version 2 of
32 * the License, or (at your option) any later version.
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
51 #include <asm/arch/silicon.h>
52 #include <asm/arch/sdrc.h>
53 #include <asm/arch/sys_info.h>
54 #include <asm/arch/syslib.h>
55 #include <asm/arch/control.h>
56 #include <asm/arch/omap3-mux.h>
57 #include <asm/arch/gpmc.h>
60 /******************** Board Boot Time *******************/
61 static void sdrc_init(void);
62 static void mux_config(void);
65 * @brief The basic entry point for board initialization.
67 * This is called as part of machine init (after arch init).
68 * This is again called with stack in SRAM, so not too many
69 * constructs possible here.
75 int in_sdram
= running_in_sdram();
82 * @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0
86 static void sdrc_init(void)
88 /* Issue SDRC Soft reset */
89 writel(0x12, SDRC_REG(SYSCONFIG
));
90 /* Wait until Reset complete */
91 while ((readl(SDRC_REG(STATUS
)) & 0x1) == 0);
92 /* SDRC to normal mode */
93 writel(0x10, SDRC_REG(SYSCONFIG
));
94 /* SDRC Sharing register */
95 /* 32-bit SDRAM on data lane [31:0] - CS0 */
96 /* pin tri-stated = 1 */
97 writel(0x00000100, SDRC_REG(SHARING
));
99 /* ----- SDRC_REG(CS0 Configuration --------- */
100 /* SDRC_REG(MCFG0 register */
101 writel(0x02584019, SDRC_REG(MCFG_0
));
103 /* SDRC_REG(RFR_CTRL0 register */
104 writel(0x0003DE01, SDRC_REG(RFR_CTRL_0
));
106 /* SDRC_REG(ACTIM_CTRLA0 register */
107 writel(0X5A9A4486, SDRC_REG(ACTIM_CTRLA_0
));
109 /* SDRC_REG(ACTIM_CTRLB0 register */
110 writel(0x00000010, SDRC_REG(ACTIM_CTRLB_0
));
112 /* Disble Power Down of CKE cuz of 1 CKE on combo part */
113 writel(0x00000081, SDRC_REG(POWER
));
115 /* SDRC_REG(Manual command register */
117 writel(0x00000000, SDRC_REG(MANUAL_0
));
118 /* Precharge command */
119 writel(0x00000001, SDRC_REG(MANUAL_0
));
120 /* Auto-refresh command */
121 writel(0x00000002, SDRC_REG(MANUAL_0
));
122 /* Auto-refresh command */
123 writel(0x00000002, SDRC_REG(MANUAL_0
));
125 /* SDRC MR0 register */
126 /* CAS latency = 3 */
127 /* Write Burst = Read Burst */
129 writel(0x00000032, SDRC_REG(MR_0
)); /* Burst length =4 */
131 /* SDRC DLLA control register */
133 writel(0x0000000A, SDRC_REG(DLLA_CTRL
));
135 /* wait until DLL is locked */
136 while ((readl(SDRC_REG(DLLA_STATUS
)) & 0x4) == 0);
141 * @brief Do the pin muxing required for Board operation.
143 * See @ref MUX_VAL for description of the muxing mode. Since some versions
144 * of Linux depend on all pin muxing being done at U-Boot level, we may need to
145 * enable CONFIG_MACH_OMAP_ADVANCED_MUX to enable the full fledged pin muxing.
149 static void mux_config(void)
151 /* Essential MUX Settings */
152 MUX_VAL(CP(SDRC_D0
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D0 */
153 MUX_VAL(CP(SDRC_D1
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D1 */
154 MUX_VAL(CP(SDRC_D2
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D2 */
155 MUX_VAL(CP(SDRC_D3
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D3 */
156 MUX_VAL(CP(SDRC_D4
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D4 */
157 MUX_VAL(CP(SDRC_D5
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D5 */
158 MUX_VAL(CP(SDRC_D6
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D6 */
159 MUX_VAL(CP(SDRC_D7
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D7 */
160 MUX_VAL(CP(SDRC_D8
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D8 */
161 MUX_VAL(CP(SDRC_D9
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D9 */
162 MUX_VAL(CP(SDRC_D10
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D10 */
163 MUX_VAL(CP(SDRC_D11
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D11 */
164 MUX_VAL(CP(SDRC_D12
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D12 */
165 MUX_VAL(CP(SDRC_D13
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D13 */
166 MUX_VAL(CP(SDRC_D14
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D14 */
167 MUX_VAL(CP(SDRC_D15
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D15 */
168 MUX_VAL(CP(SDRC_D16
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D16 */
169 MUX_VAL(CP(SDRC_D17
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D17 */
170 MUX_VAL(CP(SDRC_D18
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D18 */
171 MUX_VAL(CP(SDRC_D19
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D19 */
172 MUX_VAL(CP(SDRC_D20
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D20 */
173 MUX_VAL(CP(SDRC_D21
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D21 */
174 MUX_VAL(CP(SDRC_D22
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D22 */
175 MUX_VAL(CP(SDRC_D23
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D23 */
176 MUX_VAL(CP(SDRC_D24
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D24 */
177 MUX_VAL(CP(SDRC_D25
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D25 */
178 MUX_VAL(CP(SDRC_D26
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D26 */
179 MUX_VAL(CP(SDRC_D27
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D27 */
180 MUX_VAL(CP(SDRC_D28
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D28 */
181 MUX_VAL(CP(SDRC_D29
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D29 */
182 MUX_VAL(CP(SDRC_D30
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D30 */
183 MUX_VAL(CP(SDRC_D31
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_D31 */
184 MUX_VAL(CP(SDRC_CLK
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_CLK */
185 MUX_VAL(CP(SDRC_DQS0
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_DQS0 */
186 MUX_VAL(CP(SDRC_DQS1
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_DQS1 */
187 MUX_VAL(CP(SDRC_DQS2
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_DQS2 */
188 MUX_VAL(CP(SDRC_DQS3
), (IEN
| PTD
| DIS
| M0
)); /* SDRC_DQS3 */
190 MUX_VAL(CP(GPMC_A1
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_A1 */
191 MUX_VAL(CP(GPMC_A2
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_A2 */
192 MUX_VAL(CP(GPMC_A3
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_A3 */
193 MUX_VAL(CP(GPMC_A4
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_A4 */
194 MUX_VAL(CP(GPMC_A5
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_A5 */
195 MUX_VAL(CP(GPMC_A6
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_A6 */
196 MUX_VAL(CP(GPMC_A7
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_A7 */
197 MUX_VAL(CP(GPMC_A8
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_A8 */
198 MUX_VAL(CP(GPMC_A9
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_A9 */
199 MUX_VAL(CP(GPMC_A10
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_A10 */
200 MUX_VAL(CP(GPMC_D0
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D0 */
201 MUX_VAL(CP(GPMC_D1
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D1 */
202 MUX_VAL(CP(GPMC_D2
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D2 */
203 MUX_VAL(CP(GPMC_D3
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D3 */
204 MUX_VAL(CP(GPMC_D4
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D4 */
205 MUX_VAL(CP(GPMC_D5
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D5 */
206 MUX_VAL(CP(GPMC_D6
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D6 */
207 MUX_VAL(CP(GPMC_D7
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D7 */
208 MUX_VAL(CP(GPMC_D8
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D8 */
209 MUX_VAL(CP(GPMC_D9
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D9 */
210 MUX_VAL(CP(GPMC_D10
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D10 */
211 MUX_VAL(CP(GPMC_D11
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D11 */
212 MUX_VAL(CP(GPMC_D12
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D12 */
213 MUX_VAL(CP(GPMC_D13
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D13 */
214 MUX_VAL(CP(GPMC_D14
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D14 */
215 MUX_VAL(CP(GPMC_D15
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_D15 */
216 MUX_VAL(CP(GPMC_NCS0
), (IDIS
| PTU
| EN
| M0
)); /* GPMC_NCS0 */
217 MUX_VAL(CP(GPMC_NCS1
), (IDIS
| PTU
| EN
| M0
)); /* GPMC_NCS1 */
218 MUX_VAL(CP(GPMC_NCS2
), (IDIS
| PTU
| EN
| M0
)); /* GPMC_NCS2 */
219 MUX_VAL(CP(GPMC_NCS3
), (IDIS
| PTU
| EN
| M0
)); /* GPMC_NCS3 */
220 /* GPIO_55 - FLASH_DIS */
221 MUX_VAL(CP(GPMC_NCS4
), (IEN
| PTU
| EN
| M4
));
222 /* GPIO_56 - TORCH_EN */
223 MUX_VAL(CP(GPMC_NCS5
), (IDIS
| PTD
| DIS
| M4
));
224 /* GPIO_57 - AGPS SLP */
225 MUX_VAL(CP(GPMC_NCS6
), (IEN
| PTD
| DIS
| M4
));
226 /* GPMC_58 - WLAN_IRQ */
227 MUX_VAL(CP(GPMC_NCS7
), (IEN
| PTU
| EN
| M4
));
228 MUX_VAL(CP(GPMC_CLK
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_CLK */
230 MUX_VAL(CP(GPMC_NADV_ALE
), (IDIS
| PTD
| DIS
| M0
));
231 MUX_VAL(CP(GPMC_NOE
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_NOE */
232 MUX_VAL(CP(GPMC_NWE
), (IDIS
| PTD
| DIS
| M0
)); /* GPMC_NWE */
234 MUX_VAL(CP(GPMC_NBE0_CLE
), (IDIS
| PTD
| DIS
| M0
));
235 MUX_VAL(CP(GPMC_NBE1
), (IEN
| PTD
| DIS
| M4
)); /* GPIO_61 -BT_SHUTDN */
236 MUX_VAL(CP(GPMC_NWP
), (IEN
| PTD
| DIS
| M0
)); /* GPMC_NWP */
237 MUX_VAL(CP(GPMC_WAIT0
), (IEN
| PTU
| EN
| M0
)); /* GPMC_WAIT0 */
238 MUX_VAL(CP(GPMC_WAIT1
), (IEN
| PTU
| EN
| M0
)); /* GPMC_WAIT1 */
239 MUX_VAL(CP(GPMC_WAIT2
), (IEN
| PTU
| EN
| M4
)); /* GPIO_64 */
240 MUX_VAL(CP(GPMC_WAIT3
), (IEN
| PTU
| EN
| M4
)); /* GPIO_65 */
242 /* SERIAL INTERFACE */
244 MUX_VAL(CP(UART3_CTS_RCTX
), (IEN
| PTD
| EN
| M0
));
246 MUX_VAL(CP(UART3_RTS_SD
), (IDIS
| PTD
| DIS
| M0
));
248 MUX_VAL(CP(UART3_RX_IRRX
), (IEN
| PTD
| DIS
| M0
));
250 MUX_VAL(CP(UART3_TX_IRTX
), (IDIS
| PTD
| DIS
| M0
));
252 MUX_VAL(CP(HSUSB0_CLK
), (IEN
| PTD
| DIS
| M0
));
254 MUX_VAL(CP(HSUSB0_STP
), (IDIS
| PTU
| EN
| M0
));
256 MUX_VAL(CP(HSUSB0_DIR
), (IEN
| PTD
| DIS
| M0
));
258 MUX_VAL(CP(HSUSB0_NXT
), (IEN
| PTD
| DIS
| M0
));
260 MUX_VAL(CP(HSUSB0_DATA0
), (IEN
| PTD
| DIS
| M0
));
262 MUX_VAL(CP(HSUSB0_DATA1
), (IEN
| PTD
| DIS
| M0
));
264 MUX_VAL(CP(HSUSB0_DATA2
), (IEN
| PTD
| DIS
| M0
));
266 MUX_VAL(CP(HSUSB0_DATA3
), (IEN
| PTD
| DIS
| M0
));
268 MUX_VAL(CP(HSUSB0_DATA4
), (IEN
| PTD
| DIS
| M0
));
270 MUX_VAL(CP(HSUSB0_DATA5
), (IEN
| PTD
| DIS
| M0
));
272 MUX_VAL(CP(HSUSB0_DATA6
), (IEN
| PTD
| DIS
| M0
));
274 MUX_VAL(CP(HSUSB0_DATA7
), (IEN
| PTD
| DIS
| M0
));
275 MUX_VAL(CP(I2C1_SCL
), (IEN
| PTU
| EN
| M0
)); /* I2C1_SCL */
276 MUX_VAL(CP(I2C1_SDA
), (IEN
| PTU
| EN
| M0
)); /* I2C1_SDA */
277 #ifdef CONFIG_MACH_OMAP_ADVANCED_MUX
279 MUX_VAL(CP(DSS_PCLK
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_PCLK */
280 MUX_VAL(CP(DSS_HSYNC
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_HSYNC */
281 MUX_VAL(CP(DSS_VSYNC
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_VSYNC */
282 MUX_VAL(CP(DSS_ACBIAS
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_ACBIAS */
283 MUX_VAL(CP(DSS_DATA0
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA0 */
284 MUX_VAL(CP(DSS_DATA1
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA1 */
285 MUX_VAL(CP(DSS_DATA2
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA2 */
286 MUX_VAL(CP(DSS_DATA3
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA3 */
287 MUX_VAL(CP(DSS_DATA4
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA4 */
288 MUX_VAL(CP(DSS_DATA5
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA5 */
289 MUX_VAL(CP(DSS_DATA6
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA6 */
290 MUX_VAL(CP(DSS_DATA7
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA7 */
291 MUX_VAL(CP(DSS_DATA8
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA8 */
292 MUX_VAL(CP(DSS_DATA9
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA9 */
293 MUX_VAL(CP(DSS_DATA10
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA10 */
294 MUX_VAL(CP(DSS_DATA11
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA11 */
295 MUX_VAL(CP(DSS_DATA12
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA12 */
296 MUX_VAL(CP(DSS_DATA13
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA13 */
297 MUX_VAL(CP(DSS_DATA14
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA14 */
298 MUX_VAL(CP(DSS_DATA15
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA15 */
299 MUX_VAL(CP(DSS_DATA16
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA16 */
300 MUX_VAL(CP(DSS_DATA17
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA17 */
301 MUX_VAL(CP(DSS_DATA18
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA18 */
302 MUX_VAL(CP(DSS_DATA19
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA19 */
303 MUX_VAL(CP(DSS_DATA20
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA20 */
304 MUX_VAL(CP(DSS_DATA21
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA21 */
305 MUX_VAL(CP(DSS_DATA22
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA22 */
306 MUX_VAL(CP(DSS_DATA23
), (IDIS
| PTD
| DIS
| M0
)); /* DSS_DATA23 */
308 MUX_VAL(CP(CAM_HS
), (IEN
| PTU
| EN
| M0
)); /* CAM_HS */
309 MUX_VAL(CP(CAM_VS
), (IEN
| PTU
| EN
| M0
)); /* CAM_VS */
310 MUX_VAL(CP(CAM_XCLKA
), (IDIS
| PTD
| DIS
| M0
)); /* CAM_XCLKA */
311 MUX_VAL(CP(CAM_PCLK
), (IEN
| PTU
| EN
| M0
)); /* CAM_PCLK */
312 /* GPIO_98 - CAM_RESET */
313 MUX_VAL(CP(CAM_FLD
), (IDIS
| PTD
| DIS
| M4
));
314 MUX_VAL(CP(CAM_D0
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D0 */
315 MUX_VAL(CP(CAM_D1
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D1 */
316 MUX_VAL(CP(CAM_D2
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D2 */
317 MUX_VAL(CP(CAM_D3
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D3 */
318 MUX_VAL(CP(CAM_D4
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D4 */
319 MUX_VAL(CP(CAM_D5
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D5 */
320 MUX_VAL(CP(CAM_D6
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D6 */
321 MUX_VAL(CP(CAM_D7
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D7 */
322 MUX_VAL(CP(CAM_D8
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D8 */
323 MUX_VAL(CP(CAM_D9
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D9 */
324 MUX_VAL(CP(CAM_D10
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D10 */
325 MUX_VAL(CP(CAM_D11
), (IEN
| PTD
| DIS
| M0
)); /* CAM_D11 */
326 MUX_VAL(CP(CAM_XCLKB
), (IDIS
| PTD
| DIS
| M0
)); /* CAM_XCLKB */
327 MUX_VAL(CP(CAM_WEN
), (IEN
| PTD
| DIS
| M4
)); /* GPIO_167 */
328 MUX_VAL(CP(CAM_STROBE
), (IDIS
| PTD
| DIS
| M0
)); /* CAM_STROBE */
329 MUX_VAL(CP(CSI2_DX0
), (IEN
| PTD
| DIS
| M0
)); /* CSI2_DX0 */
330 MUX_VAL(CP(CSI2_DY0
), (IEN
| PTD
| DIS
| M0
)); /* CSI2_DY0 */
331 MUX_VAL(CP(CSI2_DX1
), (IEN
| PTD
| DIS
| M0
)); /* CSI2_DX1 */
332 MUX_VAL(CP(CSI2_DY1
), (IEN
| PTD
| DIS
| M0
)); /* CSI2_DY1 */
333 /* AUDIO INTERFACE */
334 MUX_VAL(CP(MCBSP2_FSX
), (IEN
| PTD
| DIS
| M0
)); /* MCBSP2_FSX */
336 MUX_VAL(CP(MCBSP2_CLKX
), (IEN
| PTD
| DIS
| M0
));
337 MUX_VAL(CP(MCBSP2_DR
), (IEN
| PTD
| DIS
| M0
)); /* MCBSP2_DR */
338 MUX_VAL(CP(MCBSP2_DX
), (IDIS
| PTD
| DIS
| M0
)); /* MCBSP2_DX */
340 MUX_VAL(CP(MMC1_CLK
), (IDIS
| PTU
| EN
| M0
)); /* MMC1_CLK */
341 MUX_VAL(CP(MMC1_CMD
), (IEN
| PTU
| EN
| M0
)); /* MMC1_CMD */
342 MUX_VAL(CP(MMC1_DAT0
), (IEN
| PTU
| EN
| M0
)); /* MMC1_DAT0 */
343 MUX_VAL(CP(MMC1_DAT1
), (IEN
| PTU
| EN
| M0
)); /* MMC1_DAT1 */
344 MUX_VAL(CP(MMC1_DAT2
), (IEN
| PTU
| EN
| M0
)); /* MMC1_DAT2 */
345 MUX_VAL(CP(MMC1_DAT3
), (IEN
| PTU
| EN
| M0
)); /* MMC1_DAT3 */
346 MUX_VAL(CP(MMC1_DAT4
), (IEN
| PTU
| EN
| M0
)); /* MMC1_DAT4 */
347 MUX_VAL(CP(MMC1_DAT5
), (IEN
| PTU
| EN
| M0
)); /* MMC1_DAT5 */
348 MUX_VAL(CP(MMC1_DAT6
), (IEN
| PTU
| EN
| M0
)); /* MMC1_DAT6 */
349 MUX_VAL(CP(MMC1_DAT7
), (IEN
| PTU
| EN
| M0
)); /* MMC1_DAT7 */
351 MUX_VAL(CP(MMC2_CLK
), (IEN
| PTD
| DIS
| M0
)); /* MMC2_CLK */
352 MUX_VAL(CP(MMC2_CMD
), (IEN
| PTU
| EN
| M0
)); /* MMC2_CMD */
353 MUX_VAL(CP(MMC2_DAT0
), (IEN
| PTU
| EN
| M0
)); /* MMC2_DAT0 */
354 MUX_VAL(CP(MMC2_DAT1
), (IEN
| PTU
| EN
| M0
)); /* MMC2_DAT1 */
355 MUX_VAL(CP(MMC2_DAT2
), (IEN
| PTU
| EN
| M0
)); /* MMC2_DAT2 */
356 MUX_VAL(CP(MMC2_DAT3
), (IEN
| PTU
| EN
| M0
)); /* MMC2_DAT3 */
358 MUX_VAL(CP(MMC2_DAT4
), (IDIS
| PTD
| DIS
| M1
));
360 MUX_VAL(CP(MMC2_DAT5
), (IDIS
| PTD
| DIS
| M1
));
362 MUX_VAL(CP(MMC2_DAT6
), (IDIS
| PTD
| DIS
| M1
));
364 MUX_VAL(CP(MMC2_DAT7
), (IEN
| PTU
| EN
| M1
));
367 MUX_VAL(CP(MCBSP3_DX
), (IDIS
| PTD
| DIS
| M0
));
369 MUX_VAL(CP(MCBSP3_DR
), (IEN
| PTD
| DIS
| M0
));
371 MUX_VAL(CP(MCBSP3_CLKX
), (IEN
| PTD
| DIS
| M0
));
373 MUX_VAL(CP(MCBSP3_FSX
), (IEN
| PTD
| DIS
| M0
));
374 MUX_VAL(CP(UART2_CTS
), (IEN
| PTU
| EN
| M0
)); /* UART2_CTS */
375 MUX_VAL(CP(UART2_RTS
), (IDIS
| PTD
| DIS
| M0
)); /* UART2_RTS */
376 MUX_VAL(CP(UART2_TX
), (IDIS
| PTD
| DIS
| M0
)); /* UART2_TX */
377 MUX_VAL(CP(UART2_RX
), (IEN
| PTD
| DIS
| M0
)); /* UART2_RX */
378 /* MODEM INTERFACE */
379 MUX_VAL(CP(UART1_TX
), (IDIS
| PTD
| DIS
| M0
)); /* UART1_TX */
380 MUX_VAL(CP(UART1_RTS
), (IDIS
| PTD
| DIS
| M0
)); /* UART1_RTS */
381 MUX_VAL(CP(UART1_CTS
), (IEN
| PTU
| DIS
| M0
)); /* UART1_CTS */
382 MUX_VAL(CP(UART1_RX
), (IEN
| PTD
| DIS
| M0
)); /* UART1_RX */
384 MUX_VAL(CP(MCBSP4_CLKX
), (IEN
| PTD
| DIS
| M1
));
385 MUX_VAL(CP(MCBSP4_DR
), (IEN
| PTD
| DIS
| M1
)); /* SSI1_FLAG_RX */
386 MUX_VAL(CP(MCBSP4_DX
), (IEN
| PTD
| DIS
| M1
)); /* SSI1_RDY_RX */
387 MUX_VAL(CP(MCBSP4_FSX
), (IEN
| PTD
| DIS
| M1
)); /* SSI1_WAKE */
389 MUX_VAL(CP(MCBSP1_CLKR
), (IEN
| PTD
| DIS
| M0
));
390 /* GPIO_157 - BT_WKUP */
391 MUX_VAL(CP(MCBSP1_FSR
), (IDIS
| PTU
| EN
| M4
));
393 MUX_VAL(CP(MCBSP1_DX
), (IDIS
| PTD
| DIS
| M0
));
394 MUX_VAL(CP(MCBSP1_DR
), (IEN
| PTD
| DIS
| M0
)); /* MCBSP1_DR */
396 MUX_VAL(CP(MCBSP_CLKS
), (IEN
| PTU
| DIS
| M0
));
398 MUX_VAL(CP(MCBSP1_FSX
), (IEN
| PTD
| DIS
| M0
));
400 MUX_VAL(CP(MCBSP1_CLKX
), (IEN
| PTD
| DIS
| M0
));
401 /* SERIAL INTERFACE */
402 MUX_VAL(CP(I2C2_SCL
), (IEN
| PTU
| EN
| M0
)); /* I2C2_SCL */
403 MUX_VAL(CP(I2C2_SDA
), (IEN
| PTU
| EN
| M0
)); /* I2C2_SDA */
404 MUX_VAL(CP(I2C3_SCL
), (IEN
| PTU
| EN
| M0
)); /* I2C3_SCL */
405 MUX_VAL(CP(I2C3_SDA
), (IEN
| PTU
| EN
| M0
)); /* I2C3_SDA */
406 MUX_VAL(CP(I2C4_SCL
), (IEN
| PTU
| EN
| M0
)); /* I2C4_SCL */
407 MUX_VAL(CP(I2C4_SDA
), (IEN
| PTU
| EN
| M0
)); /* I2C4_SDA */
408 MUX_VAL(CP(HDQ_SIO
), (IEN
| PTU
| EN
| M0
)); /* HDQ_SIO */
410 MUX_VAL(CP(MCSPI1_CLK
), (IEN
| PTD
| DIS
| M0
));
412 MUX_VAL(CP(MCSPI1_SIMO
), (IEN
| PTD
| DIS
| M0
));
414 MUX_VAL(CP(MCSPI1_SOMI
), (IEN
| PTD
| DIS
| M0
));
416 MUX_VAL(CP(MCSPI1_CS0
), (IEN
| PTD
| EN
| M0
));
418 MUX_VAL(CP(MCSPI1_CS1
), (IDIS
| PTD
| EN
| M0
));
419 /* GPIO_176-NOR_DPD */
420 MUX_VAL(CP(MCSPI1_CS2
), (IDIS
| PTD
| DIS
| M4
));
422 MUX_VAL(CP(MCSPI1_CS3
), (IEN
| PTD
| EN
| M0
));
424 MUX_VAL(CP(MCSPI2_CLK
), (IEN
| PTD
| DIS
| M0
));
426 MUX_VAL(CP(MCSPI2_SIMO
), (IEN
| PTD
| DIS
| M0
));
428 MUX_VAL(CP(MCSPI2_SOMI
), (IEN
| PTD
| DIS
| M0
));
430 MUX_VAL(CP(MCSPI2_CS0
), (IEN
| PTD
| EN
| M0
));
432 MUX_VAL(CP(MCSPI2_CS1
), (IEN
| PTD
| EN
| M0
));
434 /* CONTROL AND DEBUG */
435 MUX_VAL(CP(SYS_32K
), (IEN
| PTD
| DIS
| M0
)); /* SYS_32K */
436 MUX_VAL(CP(SYS_CLKREQ
), (IEN
| PTD
| DIS
| M0
)); /* SYS_CLKREQ */
437 MUX_VAL(CP(SYS_NIRQ
), (IEN
| PTU
| EN
| M0
)); /* SYS_NIRQ */
438 MUX_VAL(CP(SYS_BOOT0
), (IEN
| PTD
| DIS
| M4
)); /* GPIO_2 - PEN_IRQ */
439 MUX_VAL(CP(SYS_BOOT1
), (IEN
| PTD
| DIS
| M4
)); /* GPIO_3 */
440 MUX_VAL(CP(SYS_BOOT2
), (IEN
| PTD
| DIS
| M4
)); /* GPIO_4 - MMC1_WP */
441 MUX_VAL(CP(SYS_BOOT3
), (IEN
| PTD
| DIS
| M4
)); /* GPIO_5 - LCD_ENVDD */
442 MUX_VAL(CP(SYS_BOOT4
), (IEN
| PTD
| DIS
| M4
)); /* GPIO_6 - LAN_INTR0 */
443 MUX_VAL(CP(SYS_BOOT5
), (IEN
| PTD
| DIS
| M4
)); /* GPIO_7 - MMC2_WP */
444 /* GPIO_8-LCD_ENBKL */
445 MUX_VAL(CP(SYS_BOOT6
), (IDIS
| PTD
| DIS
| M4
));
447 MUX_VAL(CP(SYS_OFF_MODE
), (IEN
| PTD
| DIS
| M0
));
449 MUX_VAL(CP(SYS_CLKOUT1
), (IEN
| PTD
| DIS
| M0
));
450 MUX_VAL(CP(SYS_CLKOUT2
), (IEN
| PTU
| EN
| M4
)); /* GPIO_186 */
451 MUX_VAL(CP(JTAG_NTRST
), (IEN
| PTD
| DIS
| M0
)); /* JTAG_NTRST */
452 MUX_VAL(CP(JTAG_TCK
), (IEN
| PTD
| DIS
| M0
)); /* JTAG_TCK */
453 MUX_VAL(CP(JTAG_TMS
), (IEN
| PTD
| DIS
| M0
)); /* JTAG_TMS */
454 MUX_VAL(CP(JTAG_TDI
), (IEN
| PTD
| DIS
| M0
)); /* JTAG_TDI */
455 MUX_VAL(CP(JTAG_EMU0
), (IEN
| PTD
| DIS
| M0
)); /* JTAG_EMU0 */
456 MUX_VAL(CP(JTAG_EMU1
), (IEN
| PTD
| DIS
| M0
)); /* JTAG_EMU1 */
458 MUX_VAL(CP(ETK_CLK_ES2
), (IDIS
| PTU
| EN
| M0
));
460 MUX_VAL(CP(ETK_CTL_ES2
), (IDIS
| PTD
| DIS
| M0
));
461 /* HSUSB1_TLL_DATA0 */
462 MUX_VAL(CP(ETK_D0_ES2
), (IEN
| PTD
| DIS
| M1
));
464 MUX_VAL(CP(ETK_D1_ES2
), (IEN
| PTD
| DIS
| M1
));
465 /* HSUSB1_TLL_DATA2 */
466 MUX_VAL(CP(ETK_D2_ES2
), (IEN
| PTD
| EN
| M1
));
467 /* HSUSB1_TLL_DATA7 */
468 MUX_VAL(CP(ETK_D3_ES2
), (IEN
| PTD
| DIS
| M1
));
469 /* HSUSB1_TLL_DATA4 */
470 MUX_VAL(CP(ETK_D4_ES2
), (IEN
| PTD
| DIS
| M0
));
471 /* HSUSB1_TLL_DATA5 */
472 MUX_VAL(CP(ETK_D5_ES2
), (IEN
| PTD
| DIS
| M0
));
473 /* HSUSB1_TLL_DATA6 */
474 MUX_VAL(CP(ETK_D6_ES2
), (IEN
| PTD
| DIS
| M0
));
475 /* HSUSB1_TLL_DATA3 */
476 MUX_VAL(CP(ETK_D7_ES2
), (IEN
| PTD
| DIS
| M0
));
478 MUX_VAL(CP(ETK_D8_ES2
), (IEN
| PTD
| DIS
| M0
));
480 MUX_VAL(CP(ETK_D9_ES2
), (IEN
| PTD
| DIS
| M0
));
482 MUX_VAL(CP(ETK_D10_ES2
), (IEN
| PTD
| DIS
| M0
));
484 MUX_VAL(CP(ETK_D11_ES2
), (IEN
| PTD
| DIS
| M0
));
486 MUX_VAL(CP(ETK_D12_ES2
), (IEN
| PTD
| DIS
| M0
));
488 MUX_VAL(CP(ETK_D13_ES2
), (IEN
| PTD
| DIS
| M0
));
489 /* HSUSB2_TLL_DATA0 */
490 MUX_VAL(CP(ETK_D14_ES2
), (IEN
| PTD
| DIS
| M0
));
491 /* HSUSB2_TLL_DATA1 */
492 MUX_VAL(CP(ETK_D15_ES2
), (IEN
| PTD
| DIS
| M0
));
495 MUX_VAL(CP(D2D_MCAD0
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD0 */
496 MUX_VAL(CP(D2D_MCAD1
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD1 */
497 MUX_VAL(CP(D2D_MCAD2
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD2 */
498 MUX_VAL(CP(D2D_MCAD3
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD3 */
499 MUX_VAL(CP(D2D_MCAD4
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD4 */
500 MUX_VAL(CP(D2D_MCAD5
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD5 */
501 MUX_VAL(CP(D2D_MCAD6
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD6 */
502 MUX_VAL(CP(D2D_MCAD7
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD7 */
503 MUX_VAL(CP(D2D_MCAD8
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD8 */
504 MUX_VAL(CP(D2D_MCAD9
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD9 */
505 MUX_VAL(CP(D2D_MCAD10
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD10 */
506 MUX_VAL(CP(D2D_MCAD11
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD11 */
507 MUX_VAL(CP(D2D_MCAD12
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD12 */
508 MUX_VAL(CP(D2D_MCAD13
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD13 */
509 MUX_VAL(CP(D2D_MCAD14
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD14 */
510 MUX_VAL(CP(D2D_MCAD15
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD15 */
511 MUX_VAL(CP(D2D_MCAD16
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD16 */
512 MUX_VAL(CP(D2D_MCAD17
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD17 */
513 MUX_VAL(CP(D2D_MCAD18
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD18 */
514 MUX_VAL(CP(D2D_MCAD19
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD19 */
515 MUX_VAL(CP(D2D_MCAD20
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD20 */
516 MUX_VAL(CP(D2D_MCAD21
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD21 */
517 MUX_VAL(CP(D2D_MCAD22
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD22 */
518 MUX_VAL(CP(D2D_MCAD23
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD23 */
519 MUX_VAL(CP(D2D_MCAD24
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD24 */
520 MUX_VAL(CP(D2D_MCAD25
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD25 */
521 MUX_VAL(CP(D2D_MCAD26
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD26 */
522 MUX_VAL(CP(D2D_MCAD27
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD27 */
523 MUX_VAL(CP(D2D_MCAD28
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD28 */
524 MUX_VAL(CP(D2D_MCAD29
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD29 */
525 MUX_VAL(CP(D2D_MCAD30
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD30 */
526 MUX_VAL(CP(D2D_MCAD31
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD31 */
527 MUX_VAL(CP(D2D_MCAD32
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD32 */
528 MUX_VAL(CP(D2D_MCAD33
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD33 */
529 MUX_VAL(CP(D2D_MCAD34
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD34 */
530 MUX_VAL(CP(D2D_MCAD35
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD35 */
531 MUX_VAL(CP(D2D_MCAD36
), (IEN
| PTD
| EN
| M0
)); /* D2D_MCAD36 */
533 MUX_VAL(CP(D2D_CLK26MI
), (IEN
| PTD
| DIS
| M0
));
535 MUX_VAL(CP(D2D_NRESPWRON
), (IEN
| PTD
| EN
| M0
));
537 MUX_VAL(CP(D2D_NRESWARM
), (IEN
| PTU
| EN
| M0
));
539 MUX_VAL(CP(D2D_ARM9NIRQ
), (IEN
| PTD
| DIS
| M0
));
541 MUX_VAL(CP(D2D_UMA2P6FIQ
), (IEN
| PTD
| DIS
| M0
));
543 MUX_VAL(CP(D2D_SPINT
), (IEN
| PTD
| EN
| M0
));
545 MUX_VAL(CP(D2D_FRINT
), (IEN
| PTD
| EN
| M0
));
547 MUX_VAL(CP(D2D_DMAREQ0
), (IEN
| PTD
| DIS
| M0
));
549 MUX_VAL(CP(D2D_DMAREQ1
), (IEN
| PTD
| DIS
| M0
));
551 MUX_VAL(CP(D2D_DMAREQ2
), (IEN
| PTD
| DIS
| M0
));
553 MUX_VAL(CP(D2D_DMAREQ3
), (IEN
| PTD
| DIS
| M0
));
555 MUX_VAL(CP(D2D_N3GTRST
), (IEN
| PTD
| DIS
| M0
));
557 MUX_VAL(CP(D2D_N3GTDI
), (IEN
| PTD
| DIS
| M0
));
559 MUX_VAL(CP(D2D_N3GTDO
), (IEN
| PTD
| DIS
| M0
));
561 MUX_VAL(CP(D2D_N3GTMS
), (IEN
| PTD
| DIS
| M0
));
563 MUX_VAL(CP(D2D_N3GTCK
), (IEN
| PTD
| DIS
| M0
));
565 MUX_VAL(CP(D2D_N3GRTCK
), (IEN
| PTD
| DIS
| M0
));
567 MUX_VAL(CP(D2D_MSTDBY
), (IEN
| PTU
| EN
| M0
));
569 MUX_VAL(CP(D2D_SWAKEUP
), (IEN
| PTD
| EN
| M0
));
571 MUX_VAL(CP(D2D_IDLEREQ
), (IEN
| PTD
| DIS
| M0
));
573 MUX_VAL(CP(D2D_IDLEACK
), (IEN
| PTU
| EN
| M0
));
575 MUX_VAL(CP(D2D_MWRITE
), (IEN
| PTD
| DIS
| M0
));
577 MUX_VAL(CP(D2D_SWRITE
), (IEN
| PTD
| DIS
| M0
));
579 MUX_VAL(CP(D2D_MREAD
), (IEN
| PTD
| DIS
| M0
));
581 MUX_VAL(CP(D2D_SREAD
), (IEN
| PTD
| DIS
| M0
));
583 MUX_VAL(CP(D2D_MBUSFLAG
), (IEN
| PTD
| DIS
| M0
));
585 MUX_VAL(CP(D2D_SBUSFLAG
), (IEN
| PTD
| DIS
| M0
));
587 MUX_VAL(CP(SDRC_CKE0
), (IDIS
| PTU
| EN
| M0
));
588 /* SDRC_CKE1 NOT USED */
589 MUX_VAL(CP(SDRC_CKE1
), (IDIS
| PTD
| DIS
| M7
));
590 #endif /* CONFIG_MACH_OMAP_ADVANCED_MUX */
593 /******************** Board Run Time *******************/
595 /*-----------------------CONSOLE Devices -----------------------------------*/
597 #ifdef CONFIG_DRIVER_SERIAL_NS16550
599 static struct NS16550_plat serial_plat
= {
600 .clock
= 48000000, /* 48MHz (APLL96/2) */
601 .f_caps
= CONSOLE_STDIN
| CONSOLE_STDOUT
| CONSOLE_STDERR
,
602 .reg_read
= omap_uart_read
,
603 .reg_write
= omap_uart_write
,
606 static struct device_d sdp3430_serial_device
= {
607 .name
= "serial_ns16550",
609 .map_base
= OMAP_UART3_BASE
,
611 .platform_data
= (void *)&serial_plat
,
612 .type
= DEVICE_TYPE_CONSOLE
,
616 * @brief UART serial port initialization - remember to enable COM clocks in arch
618 * @return result of device registration
620 static int sdp3430_console_init(void)
622 /* Register the serial port */
623 return register_device(&sdp3430_serial_device
);
626 console_initcall(sdp3430_console_init
);
627 #endif /* CONFIG_DRIVER_SERIAL_NS16550 */
629 /*------------------------- FLASH Devices -----------------------------------*/
630 static int sdp3430_flash_init(void)
633 /* WP is made high and WAIT1 active Low */
634 gpmc_generic_init(0x10);
638 struct device_d sdram_dev
= {
642 .map_base
= 0x80000000,
643 .size
= 128 * 1024 * 1024,
645 .type
= DEVICE_TYPE_DRAM
,
648 /*------------------------- RAM Devices -------------------------------------*/
649 #ifndef CONFIG_CMD_MEMORY
651 static struct driver_d ram_drv
= {
653 .probe
= dummy_probe
,
654 .open
= dev_open_default
,
655 .close
= dev_close_default
,
658 .lseek
= dev_lseek_default
,
659 .type
= DEVICE_TYPE_DRAM
,
663 /*-----------------------Generic Devices Initialization ---------------------*/
665 static int sdp3430_devices_init(void)
668 ret
= register_device(&sdram_dev
);
671 #ifndef CONFIG_CMD_MEMORY
672 ret
= register_driver(&ram_drv
);
676 ret
= sdp3430_flash_init();
684 device_initcall(sdp3430_devices_init
);