board/a9m2410/config.h

   1 /**
   2  * @file
   3  * @brief Global defintions for the ARM S3C2410 based a9m2410 CPU card
   4  */
   5 /* This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #ifndef __CONFIG_H
  22 #define __CONFIG_H
  23
  24 /**
  25  * The external clock reference is a 12.0MHz crystal
  26  */
  27 #define S3C24XX_CLOCK_REFERENCE 12000000
  28
  29 /**
  30  * Define the main clock configuration to be used in register CLKDIVN
  31  *
  32  * We must limit the frequency of the connected SDRAMs with the clock ratio
  33  * setup to 1:2:4. This will result into FCLK:HCLK:PCLK = 200Mhz:100MHz:50MHz
  34  */
  35 #define BOARD_SPECIFIC_CLKDIVN 0x003
  36
  37 /**
  38  * Define the MPLL configuration to be used in register MPLLCON
  39  *
  40  * We want the MPLL to run at 202.80MHz
  41  */
  42 #define BOARD_SPECIFIC_MPLL ((0xA1 << 12) + (3 << 4) + 1)
  43
  44 /**
  45  * Define the UPLL configuration to be used in register UPLLCON
  46  *
  47  * We want the UPLL to run at 48.0MHz
  48  */
  49 #define BOARD_SPECIFIC_UPLL ((0x78 << 12) + (2 << 4) + 3)
  50
  51 /*
  52  * SDRAM configuration for Samsung K4M563233E
  53  *  - 2M x 32Bit x 4 Banks Mobile SDRAM
  54  *  - 90 pin FBGA
  55  *  - CL2@100MHz
  56  */
  57 /*
  58  * SDRAM uses 32bit width
  59  */
  60 #define BOARD_SPECIFIC_BWSCON ((0x02 << 24) + (0x02 << 28))
  61 /*
  62  * 32MiB SDRAM in bank6
  63  *  - MT = 11 (= sync dram type)
  64  *  - Trcd = 00 (= CL2)
  65  *  - SCAN = 01 (= 9 bit collumns)
  66  */
  67 #define BOARD_SPECIFIC_BANKCON6 ((0x3 << 15) + (0x0 << 2) + 0x1)
  68 /*
  69  * No memory in bank7
  70  */
  71 #define BOARD_SPECIFIC_BANKCON7 ((0x3 << 15) + (0x0 << 2) + 0x1)
  72 /*
  73  * SDRAM refresh settings
  74  *  - REFEN = 1 (= refresh enabled)
  75  *  - TREFMD = 0 (= auto refresh)
  76  *  - Trp = 00 (= 2 RAS precharge clocks)
  77  *  - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
  78  *  - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489
  79  */
  80 #define BOARD_SPECIFIC_REFRESH ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489)
  81 /*
  82  * SDRAM banksize
  83  *  - BURST_EN = 1 (= burst mode enabled)
  84  *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
  85  *  - SCLK_EN = 1 (= clock active only during accesses)
  86  *  - BK67MAP = 000 (= 32MiB)
  87  */
  88 #define BOARD_SPECIFIC_BANKSIZE ((1 << 7) + (1 << 5) + (0 << 4) + 0)
  89 /*
  90  * SDRAM mode register bank6
  91  * CL = 010 (= 2 clocks)
  92  */
  93 #define BOARD_SPECIFIC_MRSRB6 (0x2 << 4)
  94 /*
  95  * SDRAM mode register bank7
  96  * CL = 010 (= 2 clocks)
  97  */
  98 #define BOARD_SPECIFIC_MRSRB7 (0x2 << 4)
  99
 100 /*
 101  * Flash access timings
 102  * Tacls  = 0ns (but 20ns data setup time)
 103  * Twrph0 = 25ns (write) 35ns (read)
 104  * Twrph1 = 10ns (10ns data hold time)
 105  * Read cycle time = 50ns
 106  *
 107  * Assumed HCLK is 100MHz
 108  * Tacls = 1 (-> 20ns)
 109  * Twrph0 = 3 (-> 40ns)
 110  * Twrph1 = 1 (-> 20ns)
 111  * Cycle time = 80ns
 112  */
 113 #define A9M2410_TACLS 1
 114 #define A9M2410_TWRPH0 3
 115 #define A9M2410_TWRPH1 1
 116
 117 /* needed in the generic NAND boot code only */
 118 #ifdef CONFIG_S3C24XX_NAND_BOOT
 119 # define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1)
 120 #endif
 121
 122 #endif /* __CONFIG_H */