board/a9m2440/config.h

   1 /**
   2  * @file
   3  * @brief Global defintions for the ARM S3C2440 based a9m2440 CPU card
   4  */
   5 /* This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #ifndef __CONFIG_H
  22 #define __CONFIG_H
  23
  24 /**
  25  * The external clock reference is a 16.9344 MHz crystal
  26  */
  27 #define S3C24XX_CLOCK_REFERENCE 16934400
  28
  29 /**
  30  * Define the main clock configuration to be used in register CLKDIVN
  31  *
  32  * We must limit the frequency of the connected SDRAMs with the clock ratio
  33  * setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 400Mhz:100MHz:50MHz
  34  */
  35 #define BOARD_SPECIFIC_CLKDIVN 0x05
  36
  37 /**
  38  * Define the MPLL configuration to be used in register MPLLCON
  39  *
  40  * We want the MPLL to run at 399.65 MHz
  41  */
  42 #define BOARD_SPECIFIC_MPLL ((0x6e << 12) + (3 << 4) + 1)
  43
  44 /**
  45  * Define the UPLL configuration to be used in register UPLLCON
  46  *
  47  * We want the UPLL to run at 47.98 MHz
  48  */
  49 #define BOARD_SPECIFIC_UPLL ((0x3c << 12) + (4 << 4) + 2)
  50
  51 /*
  52  * Flash access timings
  53  * Tacls  = 0ns (but 20ns data setup time)
  54  * Twrph0 = 25ns (write) 35ns (read)
  55  * Twrph1 = 10ns (10ns data hold time)
  56  * Read cycle time = 50ns
  57  *
  58  * Assumed HCLK is 100MHz
  59  * Tacls = 1 (-> 20ns)
  60  * Twrph0 = 3 (-> 40ns)
  61  * Twrph1 = 1 (-> 20ns)
  62  * Cycle time = 80ns
  63  */
  64 #define A9M2440_TACLS 1
  65 #define A9M2440_TWRPH0 3
  66 #define A9M2440_TWRPH1 1
  67
  68 /* needed in the generic NAND boot code only */
  69 #ifdef CONFIG_S3C24XX_NAND_BOOT
  70 # define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
  71 #endif
  72
  73 #endif /* __CONFIG_H */