1 /* ----------------------------------------------------------------------------
2 * ATMEL Microcontroller Software Support - ROUSSET -
3 * ----------------------------------------------------------------------------
4 * Copyright (c) 2006, Atmel Corporation
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * - Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the disclaimer below.
14 * - Redistributions in binary form must reproduce the above copyright notice,
15 * this list of conditions and the disclaimer below in the documentation and/or
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32 // File Name : AT91SAM9260.h
33 // Object : AT91SAM9260 definitions
34 // Generated : AT91 SW Application Group 09/30/2005 (14:09:32)
36 // CVS Reference : /AT91SAM9260.pl/1.8/Fri Sep 30 08:12:29 2005//
37 // CVS Reference : /SYS_SAM9260.pl/1.1/Mon Jul 04 09:07:10 2005//
38 // CVS Reference : /HMATRIX1_SAM9260.pl/0/dummy timestamp//
39 // CVS Reference : /CCR_SAM9260.pl/0/dummy timestamp//
40 // CVS Reference : /PMC_SAM9260.pl/0/dummy timestamp//
41 // CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
42 // CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 09 10:52:25 2004//
43 // CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
44 // CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
45 // CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 03 09:02:11 2005//
46 // CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
47 // CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 03 10:29:42 2005//
48 // CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 04 13:57:00 2004//
49 // CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 06 14:16:58 2004//
50 // CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 04 13:57:22 2004//
51 // CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 04 13:56:22 2004//
52 // CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 04 13:58:52 2004//
53 // CVS Reference : /TC_6082A.pl/1.7/Wed Mar 09 16:31:51 2005//
54 // CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 03 13:20:23 2005//
55 // CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 06:38:23 2004//
56 // CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
57 // CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
58 // CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
59 // CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
60 // CVS Reference : /UDP_6083C.pl/1.2/Tue May 10 12:40:17 2005//
61 // CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
62 // CVS Reference : /TBOX_XXXX.pl/1.15/Thu Jun 09 07:05:57 2005//
63 // CVS Reference : /EBI_SAM9260.pl/0/dummy timestamp//
64 // CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 09 17:16:57 2005//
65 // CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 03 11:11:48 2005//
66 // ----------------------------------------------------------------------------
68 #ifndef AT91SAM9260_INC_H
69 #define AT91SAM9260_INC_H
71 // Hardware register definition
73 // *****************************************************************************
74 // SOFTWARE API DEFINITION FOR System Peripherals
75 // *****************************************************************************
76 // -------- GPBR : (SYS Offset: 0x1350) GPBR General Purpose Register --------
77 // -------- GPBR : (SYS Offset: 0x1354) GPBR General Purpose Register --------
78 // -------- GPBR : (SYS Offset: 0x1358) GPBR General Purpose Register --------
79 // -------- GPBR : (SYS Offset: 0x135c) GPBR General Purpose Register --------
81 // *****************************************************************************
82 // SOFTWARE API DEFINITION FOR External Bus Interface
83 // *****************************************************************************
84 // *** Register offset in AT91S_EBI structure ***
85 #define EBI_DUMMY ( 0) // Dummy register - Do not use
87 // *****************************************************************************
88 // SOFTWARE API DEFINITION FOR Error Correction Code controller
89 // *****************************************************************************
90 // *** Register offset in AT91S_ECC structure ***
91 #define ECC_CR ( 0) // ECC reset register
92 #define ECC_MR ( 4) // ECC Page size register
93 #define ECC_SR ( 8) // ECC Status register
94 #define ECC_PR (12) // ECC Parity register
95 #define ECC_NPR (16) // ECC Parity N register
96 #define ECC_VR (252) // ECC Version register
97 // -------- ECC_CR : (ECC Offset: 0x0) ECC reset register --------
98 #define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity
99 // -------- ECC_MR : (ECC Offset: 0x4) ECC page size register --------
100 #define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size
101 // -------- ECC_SR : (ECC Offset: 0x8) ECC status register --------
102 #define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error
103 #define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error
104 #define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR
105 // -------- ECC_PR : (ECC Offset: 0xc) ECC parity register --------
106 #define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error
107 #define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit
108 // -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register --------
109 #define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N
110 // -------- ECC_VR : (ECC Offset: 0xfc) ECC version register --------
111 #define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register
113 // *****************************************************************************
114 // SOFTWARE API DEFINITION FOR SDRAM Controller Interface
115 // *****************************************************************************
116 // *** Register offset in AT91S_SDRAMC structure ***
117 #define SDRAMC_MR ( 0) // SDRAM Controller Mode Register
118 #define SDRAMC_TR ( 4) // SDRAM Controller Refresh Timer Register
119 #define SDRAMC_CR ( 8) // SDRAM Controller Configuration Register
120 #define SDRAMC_HSR (12) // SDRAM Controller High Speed Register
121 #define SDRAMC_LPR (16) // SDRAM Controller Low Power Register
122 #define SDRAMC_IER (20) // SDRAM Controller Interrupt Enable Register
123 #define SDRAMC_IDR (24) // SDRAM Controller Interrupt Disable Register
124 #define SDRAMC_IMR (28) // SDRAM Controller Interrupt Mask Register
125 #define SDRAMC_ISR (32) // SDRAM Controller Interrupt Mask Register
126 #define SDRAMC_MDR (36) // SDRAM Memory Device Register
127 // -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
128 #define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode
129 #define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode
130 #define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access
131 #define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
132 #define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access
133 #define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh
134 #define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register
135 #define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode
136 // -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
137 #define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter
138 // -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
139 #define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits
140 #define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits
141 #define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits
142 #define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits
143 #define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits
144 #define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits
145 #define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits
146 #define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits
147 #define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits
148 #define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks
149 #define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks
150 #define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks
151 #define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency
152 #define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles
153 #define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles
154 #define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width
155 #define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus
156 #define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus
157 #define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles
158 #define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0
159 #define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1
160 #define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2
161 #define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3
162 #define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4
163 #define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5
164 #define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6
165 #define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7
166 #define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8
167 #define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9
168 #define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10
169 #define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11
170 #define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12
171 #define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13
172 #define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14
173 #define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15
174 #define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
175 #define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0
176 #define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1
177 #define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2
178 #define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3
179 #define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4
180 #define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5
181 #define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6
182 #define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7
183 #define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8
184 #define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9
185 #define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10
186 #define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11
187 #define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12
188 #define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13
189 #define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14
190 #define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15
191 #define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
192 #define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0
193 #define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1
194 #define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2
195 #define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3
196 #define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4
197 #define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5
198 #define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6
199 #define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7
200 #define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8
201 #define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9
202 #define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10
203 #define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11
204 #define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12
205 #define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13
206 #define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14
207 #define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15
208 #define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
209 #define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0
210 #define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1
211 #define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2
212 #define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3
213 #define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4
214 #define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5
215 #define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6
216 #define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7
217 #define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8
218 #define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9
219 #define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10
220 #define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11
221 #define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12
222 #define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13
223 #define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14
224 #define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15
225 #define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
226 #define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0
227 #define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1
228 #define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2
229 #define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3
230 #define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4
231 #define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5
232 #define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6
233 #define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7
234 #define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8
235 #define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9
236 #define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10
237 #define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11
238 #define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12
239 #define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13
240 #define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14
241 #define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15
242 #define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
243 #define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0
244 #define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1
245 #define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2
246 #define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3
247 #define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4
248 #define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5
249 #define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6
250 #define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7
251 #define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8
252 #define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9
253 #define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10
254 #define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11
255 #define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12
256 #define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13
257 #define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14
258 #define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15
259 // -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------
260 #define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit
261 #define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle
262 #define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle
263 // -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------
264 #define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations
265 #define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features
266 #define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH
267 #define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN
268 #define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
269 #define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
270 #define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
271 #define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
272 #define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
273 #define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
274 #define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
275 #define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
276 // -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
277 #define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status
278 // -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
279 // -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
280 // -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
281 // -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
282 #define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type
283 #define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode
284 #define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode
286 // *****************************************************************************
287 // SOFTWARE API DEFINITION FOR Static Memory Controller Interface
288 // *****************************************************************************
289 // *** Register offset in AT91S_SMC structure ***
290 #define SMC_SETUP0 ( 0) // Setup Register for CS 0
291 #define SMC_PULSE0 ( 4) // Pulse Register for CS 0
292 #define SMC_CYCLE0 ( 8) // Cycle Register for CS 0
293 #define SMC_CTRL0 (12) // Control Register for CS 0
294 #define SMC_SETUP1 (16) // Setup Register for CS 1
295 #define SMC_PULSE1 (20) // Pulse Register for CS 1
296 #define SMC_CYCLE1 (24) // Cycle Register for CS 1
297 #define SMC_CTRL1 (28) // Control Register for CS 1
298 #define SMC_SETUP2 (32) // Setup Register for CS 2
299 #define SMC_PULSE2 (36) // Pulse Register for CS 2
300 #define SMC_CYCLE2 (40) // Cycle Register for CS 2
301 #define SMC_CTRL2 (44) // Control Register for CS 2
302 #define SMC_SETUP3 (48) // Setup Register for CS 3
303 #define SMC_PULSE3 (52) // Pulse Register for CS 3
304 #define SMC_CYCLE3 (56) // Cycle Register for CS 3
305 #define SMC_CTRL3 (60) // Control Register for CS 3
306 #define SMC_SETUP4 (64) // Setup Register for CS 4
307 #define SMC_PULSE4 (68) // Pulse Register for CS 4
308 #define SMC_CYCLE4 (72) // Cycle Register for CS 4
309 #define SMC_CTRL4 (76) // Control Register for CS 4
310 #define SMC_SETUP5 (80) // Setup Register for CS 5
311 #define SMC_PULSE5 (84) // Pulse Register for CS 5
312 #define SMC_CYCLE5 (88) // Cycle Register for CS 5
313 #define SMC_CTRL5 (92) // Control Register for CS 5
314 #define SMC_SETUP6 (96) // Setup Register for CS 6
315 #define SMC_PULSE6 (100) // Pulse Register for CS 6
316 #define SMC_CYCLE6 (104) // Cycle Register for CS 6
317 #define SMC_CTRL6 (108) // Control Register for CS 6
318 #define SMC_SETUP7 (112) // Setup Register for CS 7
319 #define SMC_PULSE7 (116) // Pulse Register for CS 7
320 #define SMC_CYCLE7 (120) // Cycle Register for CS 7
321 #define SMC_CTRL7 (124) // Control Register for CS 7
322 // -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------
323 #define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length
324 #define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access
325 #define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length
326 #define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
327 // -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------
328 #define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length
329 #define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access
330 #define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length
331 #define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
332 // -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------
333 #define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length
334 #define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length
335 // -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
336 #define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode
337 #define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode
338 #define AT91C_SMC_NWAITM (0x3 << 5) // (SMC) NWAIT Mode
339 #define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) // (SMC) External NWAIT disabled.
340 #define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) // (SMC) External NWAIT enabled in frozen mode.
341 #define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) // (SMC) External NWAIT enabled in ready mode.
342 #define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type
343 #define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
344 #define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
345 #define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width
346 #define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.
347 #define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.
348 #define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
349 #define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.
350 #define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.
351 #define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.
352 #define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size
353 #define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.
354 #define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.
355 #define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.
356 #define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
357 // -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
358 // -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
359 // -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
360 // -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
361 // -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
362 // -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
363 // -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
364 // -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
365 // -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
366 // -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
367 // -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
368 // -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
369 // -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
370 // -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
371 // -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
372 // -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
373 // -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
374 // -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
375 // -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
376 // -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
377 // -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
378 // -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
379 // -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
380 // -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
381 // -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
382 // -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
383 // -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
384 // -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
386 // *****************************************************************************
387 // SOFTWARE API DEFINITION FOR AHB Matrix Interface
388 // *****************************************************************************
389 // *** Register offset in AT91S_MATRIX structure ***
390 #define MATRIX_MCFG0 ( 0) // Master Configuration Register 0 (ram96k)
391 #define MATRIX_MCFG1 ( 4) // Master Configuration Register 1 (rom)
392 #define MATRIX_MCFG2 ( 8) // Master Configuration Register 2 (hperiphs)
393 #define MATRIX_MCFG3 (12) // Master Configuration Register 3 (ebi)
394 #define MATRIX_MCFG4 (16) // Master Configuration Register 4 (bridge)
395 #define MATRIX_MCFG5 (20) // Master Configuration Register 5 (mailbox)
396 #define MATRIX_SCFG0 (64) // Slave Configuration Register 0 (ram96k)
397 #define MATRIX_SCFG1 (68) // Slave Configuration Register 1 (rom)
398 #define MATRIX_SCFG2 (72) // Slave Configuration Register 2 (hperiphs)
399 #define MATRIX_SCFG3 (76) // Slave Configuration Register 3 (ebi)
400 #define MATRIX_SCFG4 (80) // Slave Configuration Register 4 (bridge)
401 #define MATRIX_PRAS0 (128) // PRAS0 (ram0)
402 #define MATRIX_PRAS1 (136) // PRAS1 (ram1)
403 #define MATRIX_PRAS2 (144) // PRAS2 (ram2)
404 #define MATRIX_PRAS3 (152) // PRAS3 (ebi)
405 #define MATRIX_PRAS4 (160) // PRAS4 (periph)
406 #define MATRIX_MRCR (256) // Master Remp Control Register
407 // -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 --------
408 #define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
409 #define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
410 #define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
411 #define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
412 #define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
413 #define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
414 #define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
415 #define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
416 #define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
417 #define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
418 #define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
419 // -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 --------
420 #define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
421 #define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
422 #define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
423 #define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
424 #define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
425 #define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
426 // -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 --------
427 #define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
428 #define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
429 #define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
430 // -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 --------
431 #define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
432 #define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
433 #define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
434 #define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
435 #define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
436 #define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
437 // -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 --------
438 #define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
439 #define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
440 #define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
441 #define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
442 // -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register --------
443 #define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master
444 #define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master
446 // *****************************************************************************
447 // SOFTWARE API DEFINITION FOR Chip Configuration Registers
448 // *****************************************************************************
449 // *** Register offset in AT91S_CCFG structure ***
450 #define CCFG_EBICSA (12) // EBI Chip Select Assignement Register
451 #define CCFG_MATRIXVERSION (236) // Version Register
452 // -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register --------
453 #define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment
454 #define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
455 #define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
456 #define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment
457 #define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
458 #define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
459 #define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment
460 #define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
461 #define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
462 #define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment
463 #define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
464 #define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
465 #define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration
467 // *****************************************************************************
468 // SOFTWARE API DEFINITION FOR Peripheral DMA Controller
469 // *****************************************************************************
470 // *** Register offset in AT91S_PDC structure ***
471 #define PDC_RPR ( 0) // Receive Pointer Register
472 #define PDC_RCR ( 4) // Receive Counter Register
473 #define PDC_TPR ( 8) // Transmit Pointer Register
474 #define PDC_TCR (12) // Transmit Counter Register
475 #define PDC_RNPR (16) // Receive Next Pointer Register
476 #define PDC_RNCR (20) // Receive Next Counter Register
477 #define PDC_TNPR (24) // Transmit Next Pointer Register
478 #define PDC_TNCR (28) // Transmit Next Counter Register
479 #define PDC_PTCR (32) // PDC Transfer Control Register
480 #define PDC_PTSR (36) // PDC Transfer Status Register
481 // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
482 #define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
483 #define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
484 #define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
485 #define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
486 // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
488 // *****************************************************************************
489 // SOFTWARE API DEFINITION FOR Debug Unit
490 // *****************************************************************************
491 // *** Register offset in AT91S_DBGU structure ***
492 #define DBGU_CR ( 0) // Control Register
493 #define DBGU_MR ( 4) // Mode Register
494 #define DBGU_IER ( 8) // Interrupt Enable Register
495 #define DBGU_IDR (12) // Interrupt Disable Register
496 #define DBGU_IMR (16) // Interrupt Mask Register
497 #define DBGU_CSR (20) // Channel Status Register
498 #define DBGU_RHR (24) // Receiver Holding Register
499 #define DBGU_THR (28) // Transmitter Holding Register
500 #define DBGU_BRGR (32) // Baud Rate Generator Register
501 #define DBGU_CIDR (64) // Chip ID Register
502 #define DBGU_EXID (68) // Chip ID Extension Register
503 #define DBGU_FNTR (72) // Force NTRST Register
504 #define DBGU_RPR (256) // Receive Pointer Register
505 #define DBGU_RCR (260) // Receive Counter Register
506 #define DBGU_TPR (264) // Transmit Pointer Register
507 #define DBGU_TCR (268) // Transmit Counter Register
508 #define DBGU_RNPR (272) // Receive Next Pointer Register
509 #define DBGU_RNCR (276) // Receive Next Counter Register
510 #define DBGU_TNPR (280) // Transmit Next Pointer Register
511 #define DBGU_TNCR (284) // Transmit Next Counter Register
512 #define DBGU_PTCR (288) // PDC Transfer Control Register
513 #define DBGU_PTSR (292) // PDC Transfer Status Register
514 // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
515 #define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
516 #define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
517 #define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
518 #define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
519 #define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
520 #define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
521 #define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
522 // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
523 #define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
524 #define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
525 #define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
526 #define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
527 #define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
528 #define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
529 #define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
530 #define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
531 #define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
532 #define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
533 #define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
534 #define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
535 // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
536 #define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
537 #define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
538 #define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
539 #define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
540 #define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
541 #define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
542 #define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
543 #define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
544 #define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
545 #define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
546 #define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
547 #define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
548 // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
549 // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
550 // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
551 // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
552 #define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
554 // *****************************************************************************
555 // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
556 // *****************************************************************************
557 // *** Register offset in AT91S_AIC structure ***
558 #define AIC_SMR ( 0) // Source Mode Register
559 #define AIC_SVR (128) // Source Vector Register
560 #define AIC_IVR (256) // IRQ Vector Register
561 #define AIC_FVR (260) // FIQ Vector Register
562 #define AIC_ISR (264) // Interrupt Status Register
563 #define AIC_IPR (268) // Interrupt Pending Register
564 #define AIC_IMR (272) // Interrupt Mask Register
565 #define AIC_CISR (276) // Core Interrupt Status Register
566 #define AIC_IECR (288) // Interrupt Enable Command Register
567 #define AIC_IDCR (292) // Interrupt Disable Command Register
568 #define AIC_ICCR (296) // Interrupt Clear Command Register
569 #define AIC_ISCR (300) // Interrupt Set Command Register
570 #define AIC_EOICR (304) // End of Interrupt Command Register
571 #define AIC_SPU (308) // Spurious Vector Register
572 #define AIC_DCR (312) // Debug Control Register (Protect)
573 #define AIC_FFER (320) // Fast Forcing Enable Register
574 #define AIC_FFDR (324) // Fast Forcing Disable Register
575 #define AIC_FFSR (328) // Fast Forcing Status Register
576 // -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
577 #define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
578 #define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
579 #define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
580 #define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
581 #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
582 #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
583 #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
584 #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
585 // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
586 #define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
587 #define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
588 // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
589 #define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
590 #define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
592 // *****************************************************************************
593 // SOFTWARE API DEFINITION FOR Parallel Input Output Controler
594 // *****************************************************************************
595 // *** Register offset in AT91S_PIO structure ***
596 #define PIO_PER(p) ( 0 + (p) * 0x200) // PIO Enable Register
597 #define PIO_PDR(p) ( 4 + (p) * 0x200) // PIO Disable Register
598 #define PIO_PSR(p) ( 8 + (p) * 0x200) // PIO Status Register
599 #define PIO_OER(p) (16 + (p) * 0x200) // Output Enable Register
600 #define PIO_ODR(p) (20 + (p) * 0x200) // Output Disable Registerr
601 #define PIO_OSR(p) (24 + (p) * 0x200) // Output Status Register
602 #define PIO_IFER(p) (32 + (p) * 0x200) // Input Filter Enable Register
603 #define PIO_IFDR(p) (36 + (p) * 0x200) // Input Filter Disable Register
604 #define PIO_IFSR(p) (40 + (p) * 0x200) // Input Filter Status Register
605 #define PIO_SODR(p) (48 + (p) * 0x200) // Set Output Data Register
606 #define PIO_CODR(p) (52 + (p) * 0x200) // Clear Output Data Register
607 #define PIO_ODSR(p) (56 + (p) * 0x200) // Output Data Status Register
608 #define PIO_PDSR(p) (60 + (p) * 0x200) // Pin Data Status Register
609 #define PIO_IER(p) (64 + (p) * 0x200) // Interrupt Enable Register
610 #define PIO_IDR(p) (68 + (p) * 0x200) // Interrupt Disable Register
611 #define PIO_IMR(p) (72 + (p) * 0x200) // Interrupt Mask Register
612 #define PIO_ISR(p) (76 + (p) * 0x200) // Interrupt Status Register
613 #define PIO_MDER(p) (80 + (p) * 0x200) // Multi-driver Enable Register
614 #define PIO_MDDR(p) (84 + (p) * 0x200) // Multi-driver Disable Register
615 #define PIO_MDSR(p) (88 + (p) * 0x200) // Multi-driver Status Register
616 #define PIO_PPUDR(p) (96 + (p) * 0x200) // Pull-up Disable Register
617 #define PIO_PPUER(p) (100 + (p) * 0x200) // Pull-up Enable Register
618 #define PIO_PPUSR(p) (104 + (p) * 0x200) // Pull-up Status Register
619 #define PIO_ASR(p) (112 + (p) * 0x200) // Select A Register
620 #define PIO_BSR(p) (116 + (p) * 0x200) // Select B Register
621 #define PIO_ABSR(p) (120 + (p) * 0x200) // AB Select Status Register
622 #define PIO_OWER(p) (160 + (p) * 0x200) // Output Write Enable Register
623 #define PIO_OWDR(p) (164 + (p) * 0x200) // Output Write Disable Register
624 #define PIO_OWSR(p) (168 + (p) * 0x200) // Output Write Status Register
626 // *****************************************************************************
627 // SOFTWARE API DEFINITION FOR Clock Generator Controler
628 // *****************************************************************************
629 // *** Register offset in AT91S_CKGR structure ***
630 #define CKGR_MOR ( 0) // Main Oscillator Register
631 #define CKGR_MCFR ( 4) // Main Clock Frequency Register
632 #define CKGR_PLLAR ( 8) // PLL A Register
633 #define CKGR_PLLBR (12) // PLL B Register
634 // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
635 #define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
636 #define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
637 #define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
638 // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
639 #define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
640 #define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
641 // -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
642 #define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected
643 #define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0
644 #define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed
645 #define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter
646 #define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range
647 #define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
648 #define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
649 #define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
650 #define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
651 #define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier
652 #define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR)
653 // -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
654 #define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected
655 #define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0
656 #define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed
657 #define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter
658 #define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range
659 #define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
660 #define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
661 #define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
662 #define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
663 #define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier
664 #define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
665 #define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
666 #define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
667 #define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
669 // *****************************************************************************
670 // SOFTWARE API DEFINITION FOR Power Management Controler
671 // *****************************************************************************
672 // *** Register offset in AT91S_PMC structure ***
673 #define PMC_SCER ( 0) // System Clock Enable Register
674 #define PMC_SCDR ( 4) // System Clock Disable Register
675 #define PMC_SCSR ( 8) // System Clock Status Register
676 #define PMC_PCER (16) // Peripheral Clock Enable Register
677 #define PMC_PCDR (20) // Peripheral Clock Disable Register
678 #define PMC_PCSR (24) // Peripheral Clock Status Register
679 #define PMC_MOR (32) // Main Oscillator Register
680 #define PMC_MCFR (36) // Main Clock Frequency Register
681 #define PMC_PLLAR (40) // PLL A Register
682 #define PMC_PLLBR (44) // PLL B Register
683 #define PMC_MCKR (48) // Master Clock Register
684 #define PMC_PCKR (64) // Programmable Clock Register
685 #define PMC_IER (96) // Interrupt Enable Register
686 #define PMC_IDR (100) // Interrupt Disable Register
687 #define PMC_SR (104) // Status Register
688 #define PMC_IMR (108) // Interrupt Mask Register
689 #define PMC_PLLICPR (128) // PLL Charge Pump Current Register (SAM9G20 only)
690 // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
691 #define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
692 #define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock
693 #define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
694 #define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
695 #define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
696 #define AT91C_PMC_HCK0 (0x1 << 16) // (PMC) AHB UHP Clock Output
697 #define AT91C_PMC_HCK1 (0x1 << 17) // (PMC) AHB LCDC Clock Output
698 // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
699 // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
700 // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
701 // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
702 // -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
703 // -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
704 // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
705 #define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
706 #define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
707 #define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
708 #define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected
709 #define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected
710 #define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
711 #define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
712 #define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
713 #define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
714 #define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
715 #define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
716 #define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
717 #define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
718 #define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division
719 #define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same
720 #define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
721 #define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock
722 // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
723 // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
724 #define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
725 #define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
726 #define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
727 #define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask
728 #define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
729 #define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
730 // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
731 // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
732 // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
734 // *****************************************************************************
735 // SOFTWARE API DEFINITION FOR Reset Controller Interface
736 // *****************************************************************************
737 // *** Register offset in AT91S_RSTC structure ***
738 #define RSTC_RCR ( 0) // Reset Control Register
739 #define RSTC_RSR ( 4) // Reset Status Register
740 #define RSTC_RMR ( 8) // Reset Mode Register
741 // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
742 #define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
743 #define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset
744 #define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
745 #define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
746 #define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
747 // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
748 #define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
749 #define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
750 #define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
751 #define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
752 #define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
753 #define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
754 #define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
755 #define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
756 #define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
757 // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
758 #define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
759 #define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
760 #define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
762 // *****************************************************************************
763 // SOFTWARE API DEFINITION FOR Shut Down Controller Interface
764 // *****************************************************************************
765 // *** Register offset in AT91S_SHDWC structure ***
766 #define SHDWC_SHCR ( 0) // Shut Down Control Register
767 #define SHDWC_SHMR ( 4) // Shut Down Mode Register
768 #define SHDWC_SHSR ( 8) // Shut Down Status Register
769 // -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------
770 #define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset
771 #define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password
772 // -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------
773 #define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection
774 #define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.
775 #define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level.
776 #define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level.
777 #define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.
778 #define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0
779 #define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection
780 #define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input.
781 #define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level.
782 #define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level.
783 #define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change.
784 #define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1
785 #define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
786 #define AT91C_SHDWC_RTCWKEN (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable
787 // -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------
788 #define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status
789 #define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status
790 #define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status
791 #define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up
792 #define AT91C_SHDWC_RTCWK (0x1 << 17) // (SHDWC) Real Time Clock wake Up
794 // *****************************************************************************
795 // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
796 // *****************************************************************************
797 // *** Register offset in AT91S_RTTC structure ***
798 #define RTTC_RTMR ( 0) // Real-time Mode Register
799 #define RTTC_RTAR ( 4) // Real-time Alarm Register
800 #define RTTC_RTVR ( 8) // Real-time Value Register
801 #define RTTC_RTSR (12) // Real-time Status Register
802 // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
803 #define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
804 #define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
805 #define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
806 #define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
807 // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
808 #define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
809 // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
810 #define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
811 // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
812 #define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
813 #define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
815 // *****************************************************************************
816 // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
817 // *****************************************************************************
818 // *** Register offset in AT91S_PITC structure ***
819 #define PITC_PIMR ( 0) // Period Interval Mode Register
820 #define PITC_PISR ( 4) // Period Interval Status Register
821 #define PITC_PIVR ( 8) // Period Interval Value Register
822 #define PITC_PIIR (12) // Period Interval Image Register
823 // -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
824 #define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
825 #define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
826 #define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
827 // -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
828 #define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
829 // -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
830 #define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
831 #define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
832 // -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
834 // *****************************************************************************
835 // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
836 // *****************************************************************************
837 // *** Register offset in AT91S_WDTC structure ***
838 #define WDTC_WDCR ( 0) // Watchdog Control Register
839 #define WDTC_WDMR ( 4) // Watchdog Mode Register
840 #define WDTC_WDSR ( 8) // Watchdog Status Register
841 // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
842 #define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
843 #define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
844 // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
845 #define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
846 #define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
847 #define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
848 #define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
849 #define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
850 #define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
851 #define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
852 #define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
853 // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
854 #define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
855 #define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
857 // *****************************************************************************
858 // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
859 // *****************************************************************************
860 // *** Register offset in AT91S_TC structure ***
861 #define TC_CCR ( 0) // Channel Control Register
862 #define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
863 #define TC_CV (16) // Counter Value
864 #define TC_RA (20) // Register A
865 #define TC_RB (24) // Register B
866 #define TC_RC (28) // Register C
867 #define TC_SR (32) // Status Register
868 #define TC_IER (36) // Interrupt Enable Register
869 #define TC_IDR (40) // Interrupt Disable Register
870 #define TC_IMR (44) // Interrupt Mask Register
871 // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
872 #define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
873 #define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
874 #define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
875 // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
876 #define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
877 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
878 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
879 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
880 #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
881 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
882 #define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
883 #define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
884 #define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
885 #define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
886 #define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
887 #define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
888 #define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
889 #define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
890 #define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
891 #define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
892 #define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
893 #define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
894 #define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
895 #define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
896 #define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
897 #define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
898 #define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
899 #define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
900 #define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
901 #define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
902 #define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
903 #define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
904 #define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
905 #define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
906 #define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
907 #define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
908 #define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
909 #define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
910 #define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
911 #define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
912 #define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
913 #define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
914 #define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
915 #define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
916 #define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
917 #define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
918 #define AT91C_TC_WAVE (0x1 << 15) // (TC)
919 #define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
920 #define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
921 #define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
922 #define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
923 #define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
924 #define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
925 #define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
926 #define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
927 #define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
928 #define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
929 #define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
930 #define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
931 #define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
932 #define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
933 #define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
934 #define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
935 #define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
936 #define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
937 #define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
938 #define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
939 #define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
940 #define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
941 #define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
942 #define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
943 #define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
944 #define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
945 #define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
946 #define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
947 #define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
948 #define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
949 #define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
950 #define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
951 #define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
952 #define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
953 #define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
954 #define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
955 #define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
956 #define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
957 #define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
958 #define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
959 #define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
960 #define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
961 #define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
962 #define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
963 #define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
964 #define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
965 #define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
966 #define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
967 #define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
968 #define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
969 // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
970 #define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
971 #define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
972 #define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
973 #define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
974 #define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
975 #define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
976 #define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
977 #define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
978 #define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
979 #define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
980 #define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
981 // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
982 // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
983 // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
985 // *****************************************************************************
986 // SOFTWARE API DEFINITION FOR Timer Counter Interface
987 // *****************************************************************************
988 // *** Register offset in AT91S_TCB structure ***
989 #define TCB_TC0 ( 0) // TC Channel 0
990 #define TCB_TC1 (64) // TC Channel 1
991 #define TCB_TC2 (128) // TC Channel 2
992 #define TCB_BCR (192) // TC Block Control Register
993 #define TCB_BMR (196) // TC Block Mode Register
994 // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
995 #define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
996 // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
997 #define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
998 #define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
999 #define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
1000 #define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
1001 #define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
1002 #define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
1003 #define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
1004 #define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
1005 #define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
1006 #define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
1007 #define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
1008 #define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
1009 #define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
1010 #define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
1011 #define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
1013 // *****************************************************************************
1014 // SOFTWARE API DEFINITION FOR Multimedia Card Interface
1015 // *****************************************************************************
1016 // *** Register offset in AT91S_MCI structure ***
1017 #define MCI_CR ( 0) // MCI Control Register
1018 #define MCI_MR ( 4) // MCI Mode Register
1019 #define MCI_DTOR ( 8) // MCI Data Timeout Register
1020 #define MCI_SDCR (12) // MCI SD Card Register
1021 #define MCI_ARGR (16) // MCI Argument Register
1022 #define MCI_CMDR (20) // MCI Command Register
1023 #define MCI_BLKR (24) // MCI Block Register
1024 #define MCI_RSPR (32) // MCI Response Register
1025 #define MCI_RDR (48) // MCI Receive Data Register
1026 #define MCI_TDR (52) // MCI Transmit Data Register
1027 #define MCI_SR (64) // MCI Status Register
1028 #define MCI_IER (68) // MCI Interrupt Enable Register
1029 #define MCI_IDR (72) // MCI Interrupt Disable Register
1030 #define MCI_IMR (76) // MCI Interrupt Mask Register
1031 #define MCI_VR (252) // MCI Version Register
1032 #define MCI_RPR (256) // Receive Pointer Register
1033 #define MCI_RCR (260) // Receive Counter Register
1034 #define MCI_TPR (264) // Transmit Pointer Register
1035 #define MCI_TCR (268) // Transmit Counter Register
1036 #define MCI_RNPR (272) // Receive Next Pointer Register
1037 #define MCI_RNCR (276) // Receive Next Counter Register
1038 #define MCI_TNPR (280) // Transmit Next Pointer Register
1039 #define MCI_TNCR (284) // Transmit Next Counter Register
1040 #define MCI_PTCR (288) // PDC Transfer Control Register
1041 #define MCI_PTSR (292) // PDC Transfer Status Register
1042 // -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
1043 #define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable
1044 #define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable
1045 #define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable
1046 #define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable
1047 #define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset
1048 // -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
1049 #define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider
1050 #define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider
1051 #define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable
1052 #define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable
1053 #define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer
1054 #define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value
1055 #define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode
1056 #define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length
1057 // -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
1058 #define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number
1059 #define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier
1060 #define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1
1061 #define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16
1062 #define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128
1063 #define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256
1064 #define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024
1065 #define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096
1066 #define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536
1067 #define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576
1068 // -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
1069 #define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector
1070 #define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width
1071 // -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
1072 #define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number
1073 #define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type
1074 #define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response
1075 #define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response
1076 #define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response
1077 #define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD
1078 #define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD
1079 #define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD
1080 #define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD
1081 #define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command
1082 #define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response
1083 #define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command
1084 #define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond
1085 #define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD
1086 #define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer
1087 #define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer
1088 #define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer
1089 #define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction
1090 #define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type
1091 #define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
1092 #define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
1093 #define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type
1094 #define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type
1095 #define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type
1096 #define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command
1097 #define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command
1098 #define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command
1099 #define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command
1100 // -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register --------
1101 #define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
1102 // -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
1103 #define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag
1104 #define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag
1105 #define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag
1106 #define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag
1107 #define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag
1108 #define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag
1109 #define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag
1110 #define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag
1111 #define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A
1112 #define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B
1113 #define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
1114 #define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
1115 #define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag
1116 #define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag
1117 #define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag
1118 #define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag
1119 #define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag
1120 #define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag
1121 #define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag
1122 #define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag
1123 #define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag
1124 #define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag
1125 #define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag
1126 // -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
1127 // -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
1128 // -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------
1130 // *****************************************************************************
1131 // SOFTWARE API DEFINITION FOR Two-wire Interface
1132 // *****************************************************************************
1133 // *** Register offset in AT91S_TWI structure ***
1134 #define TWI_CR ( 0) // Control Register
1135 #define TWI_MMR ( 4) // Master Mode Register
1136 #define TWI_IADR (12) // Internal Address Register
1137 #define TWI_CWGR (16) // Clock Waveform Generator Register
1138 #define TWI_SR (32) // Status Register
1139 #define TWI_IER (36) // Interrupt Enable Register
1140 #define TWI_IDR (40) // Interrupt Disable Register
1141 #define TWI_IMR (44) // Interrupt Mask Register
1142 #define TWI_RHR (48) // Receive Holding Register
1143 #define TWI_THR (52) // Transmit Holding Register
1144 // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
1145 #define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
1146 #define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
1147 #define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
1148 #define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
1149 #define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
1150 // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
1151 #define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
1152 #define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
1153 #define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
1154 #define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
1155 #define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
1156 #define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
1157 #define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
1158 // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
1159 #define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
1160 #define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
1161 #define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
1162 // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
1163 #define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
1164 #define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
1165 #define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
1166 #define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
1167 #define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
1168 #define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
1169 // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
1170 // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
1171 // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
1173 // *****************************************************************************
1174 // SOFTWARE API DEFINITION FOR Usart
1175 // *****************************************************************************
1176 // *** Register offset in AT91S_USART structure ***
1177 #define US_CR ( 0) // Control Register
1178 #define US_MR ( 4) // Mode Register
1179 #define US_IER ( 8) // Interrupt Enable Register
1180 #define US_IDR (12) // Interrupt Disable Register
1181 #define US_IMR (16) // Interrupt Mask Register
1182 #define US_CSR (20) // Channel Status Register
1183 #define US_RHR (24) // Receiver Holding Register
1184 #define US_THR (28) // Transmitter Holding Register
1185 #define US_BRGR (32) // Baud Rate Generator Register
1186 #define US_RTOR (36) // Receiver Time-out Register
1187 #define US_TTGR (40) // Transmitter Time-guard Register
1188 #define US_FIDI (64) // FI_DI_Ratio Register
1189 #define US_NER (68) // Nb Errors Register
1190 #define US_IF (76) // IRDA_FILTER Register
1191 #define US_RPR (256) // Receive Pointer Register
1192 #define US_RCR (260) // Receive Counter Register
1193 #define US_TPR (264) // Transmit Pointer Register
1194 #define US_TCR (268) // Transmit Counter Register
1195 #define US_RNPR (272) // Receive Next Pointer Register
1196 #define US_RNCR (276) // Receive Next Counter Register
1197 #define US_TNPR (280) // Transmit Next Pointer Register
1198 #define US_TNCR (284) // Transmit Next Counter Register
1199 #define US_PTCR (288) // PDC Transfer Control Register
1200 #define US_PTSR (292) // PDC Transfer Status Register
1201 // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
1202 #define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
1203 #define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
1204 #define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
1205 #define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
1206 #define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
1207 #define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
1208 #define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
1209 #define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
1210 #define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
1211 #define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
1212 #define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
1213 // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
1214 #define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
1215 #define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
1216 #define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
1217 #define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
1218 #define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
1219 #define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
1220 #define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
1221 #define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
1222 #define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
1223 #define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
1224 #define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
1225 #define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
1226 #define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
1227 #define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
1228 #define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
1229 #define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
1230 #define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
1231 #define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
1232 #define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
1233 #define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
1234 #define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
1235 #define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
1236 #define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
1237 #define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
1238 #define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
1239 #define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
1240 #define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
1241 #define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
1242 #define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
1243 #define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
1244 #define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
1245 #define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
1246 // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
1247 #define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
1248 #define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
1249 #define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
1250 #define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
1251 #define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
1252 #define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
1253 #define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
1254 #define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
1255 // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
1256 // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
1257 // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
1258 #define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
1259 #define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
1260 #define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
1261 #define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
1263 // *****************************************************************************
1264 // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
1265 // *****************************************************************************
1266 // *** Register offset in AT91S_SSC structure ***
1267 #define SSC_CR ( 0) // Control Register
1268 #define SSC_CMR ( 4) // Clock Mode Register
1269 #define SSC_RCMR (16) // Receive Clock ModeRegister
1270 #define SSC_RFMR (20) // Receive Frame Mode Register
1271 #define SSC_TCMR (24) // Transmit Clock Mode Register
1272 #define SSC_TFMR (28) // Transmit Frame Mode Register
1273 #define SSC_RHR (32) // Receive Holding Register
1274 #define SSC_THR (36) // Transmit Holding Register
1275 #define SSC_RSHR (48) // Receive Sync Holding Register
1276 #define SSC_TSHR (52) // Transmit Sync Holding Register
1277 #define SSC_SR (64) // Status Register
1278 #define SSC_IER (68) // Interrupt Enable Register
1279 #define SSC_IDR (72) // Interrupt Disable Register
1280 #define SSC_IMR (76) // Interrupt Mask Register
1281 #define SSC_RPR (256) // Receive Pointer Register
1282 #define SSC_RCR (260) // Receive Counter Register
1283 #define SSC_TPR (264) // Transmit Pointer Register
1284 #define SSC_TCR (268) // Transmit Counter Register
1285 #define SSC_RNPR (272) // Receive Next Pointer Register
1286 #define SSC_RNCR (276) // Receive Next Counter Register
1287 #define SSC_TNPR (280) // Transmit Next Pointer Register
1288 #define SSC_TNCR (284) // Transmit Next Counter Register
1289 #define SSC_PTCR (288) // PDC Transfer Control Register
1290 #define SSC_PTSR (292) // PDC Transfer Status Register
1291 // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
1292 #define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
1293 #define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
1294 #define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
1295 #define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
1296 #define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
1297 // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
1298 #define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
1299 #define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
1300 #define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
1301 #define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
1302 #define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
1303 #define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
1304 #define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
1305 #define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
1306 #define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
1307 #define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
1308 #define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
1309 #define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
1310 #define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
1311 #define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
1312 #define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
1313 #define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
1314 #define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
1315 #define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
1316 #define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
1317 #define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
1318 #define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
1319 // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
1320 #define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
1321 #define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
1322 #define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
1323 #define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
1324 #define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
1325 #define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
1326 #define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
1327 #define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
1328 #define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
1329 #define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
1330 #define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
1331 #define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
1332 #define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
1333 // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
1334 // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
1335 #define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
1336 #define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
1337 // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
1338 #define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
1339 #define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
1340 #define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
1341 #define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
1342 #define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
1343 #define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
1344 #define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
1345 #define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
1346 #define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
1347 #define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
1348 #define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
1349 #define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
1350 // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
1351 // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
1352 // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
1354 // *****************************************************************************
1355 // SOFTWARE API DEFINITION FOR Serial Parallel Interface
1356 // *****************************************************************************
1357 // *** Register offset in AT91S_SPI structure ***
1358 #define SPI_CR ( 0) // Control Register
1359 #define SPI_MR ( 4) // Mode Register
1360 #define SPI_RDR ( 8) // Receive Data Register
1361 #define SPI_TDR (12) // Transmit Data Register
1362 #define SPI_SR (16) // Status Register
1363 #define SPI_IER (20) // Interrupt Enable Register
1364 #define SPI_IDR (24) // Interrupt Disable Register
1365 #define SPI_IMR (28) // Interrupt Mask Register
1366 #define SPI_CSR (48) // Chip Select Register
1367 #define SPI_RPR (256) // Receive Pointer Register
1368 #define SPI_RCR (260) // Receive Counter Register
1369 #define SPI_TPR (264) // Transmit Pointer Register
1370 #define SPI_TCR (268) // Transmit Counter Register
1371 #define SPI_RNPR (272) // Receive Next Pointer Register
1372 #define SPI_RNCR (276) // Receive Next Counter Register
1373 #define SPI_TNPR (280) // Transmit Next Pointer Register
1374 #define SPI_TNCR (284) // Transmit Next Counter Register
1375 #define SPI_PTCR (288) // PDC Transfer Control Register
1376 #define SPI_PTSR (292) // PDC Transfer Status Register
1377 // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
1378 #define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
1379 #define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
1380 #define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
1381 #define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
1382 // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
1383 #define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
1384 #define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
1385 #define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
1386 #define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
1387 #define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
1388 #define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
1389 #define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
1390 #define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
1391 #define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
1392 #define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
1393 // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
1394 #define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
1395 #define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
1396 // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
1397 #define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
1398 #define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
1399 // -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
1400 #define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
1401 #define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
1402 #define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
1403 #define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
1404 #define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
1405 #define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
1406 #define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
1407 #define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
1408 #define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
1409 #define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
1410 #define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
1411 // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
1412 // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
1413 // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
1414 // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
1415 #define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
1416 #define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
1417 #define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
1418 #define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
1419 #define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
1420 #define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
1421 #define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
1422 #define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
1423 #define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
1424 #define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
1425 #define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
1426 #define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
1427 #define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
1428 #define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
1429 #define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
1430 #define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
1432 // *****************************************************************************
1433 // SOFTWARE API DEFINITION FOR Analog to Digital Convertor
1434 // *****************************************************************************
1435 // *** Register offset in AT91S_ADC structure ***
1436 #define ADC_CR ( 0) // ADC Control Register
1437 #define ADC_MR ( 4) // ADC Mode Register
1438 #define ADC_CHER (16) // ADC Channel Enable Register
1439 #define ADC_CHDR (20) // ADC Channel Disable Register
1440 #define ADC_CHSR (24) // ADC Channel Status Register
1441 #define ADC_SR (28) // ADC Status Register
1442 #define ADC_LCDR (32) // ADC Last Converted Data Register
1443 #define ADC_IER (36) // ADC Interrupt Enable Register
1444 #define ADC_IDR (40) // ADC Interrupt Disable Register
1445 #define ADC_IMR (44) // ADC Interrupt Mask Register
1446 #define ADC_CDR0 (48) // ADC Channel Data Register 0
1447 #define ADC_CDR1 (52) // ADC Channel Data Register 1
1448 #define ADC_CDR2 (56) // ADC Channel Data Register 2
1449 #define ADC_CDR3 (60) // ADC Channel Data Register 3
1450 #define ADC_CDR4 (64) // ADC Channel Data Register 4
1451 #define ADC_CDR5 (68) // ADC Channel Data Register 5
1452 #define ADC_CDR6 (72) // ADC Channel Data Register 6
1453 #define ADC_CDR7 (76) // ADC Channel Data Register 7
1454 #define ADC_RPR (256) // Receive Pointer Register
1455 #define ADC_RCR (260) // Receive Counter Register
1456 #define ADC_TPR (264) // Transmit Pointer Register
1457 #define ADC_TCR (268) // Transmit Counter Register
1458 #define ADC_RNPR (272) // Receive Next Pointer Register
1459 #define ADC_RNCR (276) // Receive Next Counter Register
1460 #define ADC_TNPR (280) // Transmit Next Pointer Register
1461 #define ADC_TNCR (284) // Transmit Next Counter Register
1462 #define ADC_PTCR (288) // PDC Transfer Control Register
1463 #define ADC_PTSR (292) // PDC Transfer Status Register
1464 // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
1465 #define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
1466 #define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
1467 // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
1468 #define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
1469 #define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
1470 #define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
1471 #define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
1472 #define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
1473 #define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
1474 #define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
1475 #define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
1476 #define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
1477 #define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
1478 #define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
1479 #define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
1480 #define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
1481 #define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
1482 #define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
1483 #define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
1484 #define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
1485 #define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
1486 #define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
1487 #define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
1488 // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
1489 #define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
1490 #define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
1491 #define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
1492 #define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
1493 #define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
1494 #define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
1495 #define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
1496 #define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
1497 // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
1498 // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
1499 // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
1500 #define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
1501 #define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
1502 #define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
1503 #define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
1504 #define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
1505 #define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
1506 #define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
1507 #define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
1508 #define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
1509 #define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
1510 #define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
1511 #define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
1512 #define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
1513 #define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
1514 #define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
1515 #define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
1516 #define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
1517 #define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
1518 #define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
1519 #define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
1520 // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
1521 #define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
1522 // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
1523 // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
1524 // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
1525 // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
1526 #define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
1527 // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
1528 // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
1529 // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
1530 // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
1531 // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
1532 // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
1533 // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
1535 // *****************************************************************************
1536 // SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
1537 // *****************************************************************************
1538 // *** Register offset in AT91S_EMAC structure ***
1539 #define EMAC_NCR ( 0) // Network Control Register
1540 #define EMAC_NCFGR ( 4) // Network Configuration Register
1541 #define EMAC_NSR ( 8) // Network Status Register
1542 #define EMAC_TSR (20) // Transmit Status Register
1543 #define EMAC_RBQP (24) // Receive Buffer Queue Pointer
1544 #define EMAC_TBQP (28) // Transmit Buffer Queue Pointer
1545 #define EMAC_RSR (32) // Receive Status Register
1546 #define EMAC_ISR (36) // Interrupt Status Register
1547 #define EMAC_IER (40) // Interrupt Enable Register
1548 #define EMAC_IDR (44) // Interrupt Disable Register
1549 #define EMAC_IMR (48) // Interrupt Mask Register
1550 #define EMAC_MAN (52) // PHY Maintenance Register
1551 #define EMAC_PTR (56) // Pause Time Register
1552 #define EMAC_PFR (60) // Pause Frames received Register
1553 #define EMAC_FTO (64) // Frames Transmitted OK Register
1554 #define EMAC_SCF (68) // Single Collision Frame Register
1555 #define EMAC_MCF (72) // Multiple Collision Frame Register
1556 #define EMAC_FRO (76) // Frames Received OK Register
1557 #define EMAC_FCSE (80) // Frame Check Sequence Error Register
1558 #define EMAC_ALE (84) // Alignment Error Register
1559 #define EMAC_DTF (88) // Deferred Transmission Frame Register
1560 #define EMAC_LCOL (92) // Late Collision Register
1561 #define EMAC_ECOL (96) // Excessive Collision Register
1562 #define EMAC_TUND (100) // Transmit Underrun Error Register
1563 #define EMAC_CSE (104) // Carrier Sense Error Register
1564 #define EMAC_RRE (108) // Receive Ressource Error Register
1565 #define EMAC_ROV (112) // Receive Overrun Errors Register
1566 #define EMAC_RSE (116) // Receive Symbol Errors Register
1567 #define EMAC_ELE (120) // Excessive Length Errors Register
1568 #define EMAC_RJA (124) // Receive Jabbers Register
1569 #define EMAC_USF (128) // Undersize Frames Register
1570 #define EMAC_STE (132) // SQE Test Error Register
1571 #define EMAC_RLE (136) // Receive Length Field Mismatch Register
1572 #define EMAC_TPF (140) // Transmitted Pause Frames Register
1573 #define EMAC_HRB (144) // Hash Address Bottom[31:0]
1574 #define EMAC_HRT (148) // Hash Address Top[63:32]
1575 #define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes
1576 #define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes
1577 #define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes
1578 #define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes
1579 #define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes
1580 #define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes
1581 #define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes
1582 #define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes
1583 #define EMAC_TID (184) // Type ID Checking Register
1584 #define EMAC_TPQ (188) // Transmit Pause Quantum Register
1585 #define EMAC_USRIO (192) // USER Input/Output Register
1586 #define EMAC_WOL (196) // Wake On LAN Register
1587 #define EMAC_REV (252) // Revision Register
1588 // -------- EMAC_NCR : (EMAC Offset: 0x0) --------
1589 #define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
1590 #define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
1591 #define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
1592 #define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
1593 #define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
1594 #define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
1595 #define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
1596 #define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
1597 #define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
1598 #define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
1599 #define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
1600 #define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
1601 #define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
1602 // -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
1603 #define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
1604 #define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
1605 #define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
1606 #define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
1607 #define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
1608 #define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
1609 #define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
1610 #define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
1611 #define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
1612 #define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
1613 #define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
1614 #define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
1615 #define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
1616 #define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
1617 #define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
1618 #define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
1619 #define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
1620 #define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
1621 #define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
1622 #define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
1623 #define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
1624 #define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
1625 #define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
1626 #define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
1627 #define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
1628 // -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
1629 #define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
1630 #define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
1631 #define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
1632 // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
1633 #define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
1634 #define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
1635 #define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
1636 #define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
1637 #define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
1638 #define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
1639 #define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
1640 // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
1641 #define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
1642 #define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
1643 #define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
1644 // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
1645 #define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
1646 #define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
1647 #define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
1648 #define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
1649 #define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
1650 #define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
1651 #define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
1652 #define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
1653 #define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
1654 #define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
1655 #define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
1656 #define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
1657 #define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
1658 // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
1659 // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
1660 // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
1661 // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
1662 #define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
1663 #define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
1664 #define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
1665 #define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
1666 #define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
1667 #define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
1668 // -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
1669 #define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
1670 #define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable
1671 // -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
1672 #define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
1673 #define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
1674 #define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
1675 #define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
1676 // -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
1677 #define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
1678 #define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
1680 // *****************************************************************************
1681 // SOFTWARE API DEFINITION FOR USB Device Interface
1682 // *****************************************************************************
1683 // *** Register offset in AT91S_UDP structure ***
1684 #define UDP_NUM ( 0) // Frame Number Register
1685 #define UDP_GLBSTATE ( 4) // Global State Register
1686 #define UDP_FADDR ( 8) // Function Address Register
1687 #define UDP_IER (16) // Interrupt Enable Register
1688 #define UDP_IDR (20) // Interrupt Disable Register
1689 #define UDP_IMR (24) // Interrupt Mask Register
1690 #define UDP_ISR (28) // Interrupt Status Register
1691 #define UDP_ICR (32) // Interrupt Clear Register
1692 #define UDP_RSTEP (40) // Reset Endpoint Register
1693 #define UDP_CSR (48) // Endpoint Control and Status Register
1694 #define UDP_FDR (80) // Endpoint FIFO Data Register
1695 #define UDP_TXVC (116) // Transceiver Control Register
1696 // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
1697 #define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
1698 #define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
1699 #define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
1700 // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
1701 #define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
1702 #define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
1703 #define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
1704 #define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
1705 #define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
1706 // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
1707 #define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
1708 #define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
1709 // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
1710 #define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
1711 #define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
1712 #define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
1713 #define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
1714 #define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
1715 #define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
1716 #define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
1717 #define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
1718 #define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
1719 #define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
1720 #define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
1721 // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
1722 // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
1723 // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
1724 #define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
1725 // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
1726 // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
1727 #define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
1728 #define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
1729 #define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
1730 #define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
1731 #define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
1732 #define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
1733 // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
1734 #define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
1735 #define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
1736 #define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
1737 #define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
1738 #define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
1739 #define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
1740 #define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
1741 #define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
1742 #define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
1743 #define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
1744 #define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
1745 #define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
1746 #define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
1747 #define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
1748 #define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
1749 #define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
1750 #define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
1751 #define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
1752 #define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
1753 // -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
1754 #define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
1755 #define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
1757 // *****************************************************************************
1758 // SOFTWARE API DEFINITION FOR USB Host Interface
1759 // *****************************************************************************
1760 // *** Register offset in AT91S_UHP structure ***
1761 #define UHP_HcRevision ( 0) // Revision
1762 #define UHP_HcControl ( 4) // Operating modes for the Host Controller
1763 #define UHP_HcCommandStatus ( 8) // Command & status Register
1764 #define UHP_HcInterruptStatus (12) // Interrupt Status Register
1765 #define UHP_HcInterruptEnable (16) // Interrupt Enable Register
1766 #define UHP_HcInterruptDisable (20) // Interrupt Disable Register
1767 #define UHP_HcHCCA (24) // Pointer to the Host Controller Communication Area
1768 #define UHP_HcPeriodCurrentED (28) // Current Isochronous or Interrupt Endpoint Descriptor
1769 #define UHP_HcControlHeadED (32) // First Endpoint Descriptor of the Control list
1770 #define UHP_HcControlCurrentED (36) // Endpoint Control and Status Register
1771 #define UHP_HcBulkHeadED (40) // First endpoint register of the Bulk list
1772 #define UHP_HcBulkCurrentED (44) // Current endpoint of the Bulk list
1773 #define UHP_HcBulkDoneHead (48) // Last completed transfer descriptor
1774 #define UHP_HcFmInterval (52) // Bit time between 2 consecutive SOFs
1775 #define UHP_HcFmRemaining (56) // Bit time remaining in the current Frame
1776 #define UHP_HcFmNumber (60) // Frame number
1777 #define UHP_HcPeriodicStart (64) // Periodic Start
1778 #define UHP_HcLSThreshold (68) // LS Threshold
1779 #define UHP_HcRhDescriptorA (72) // Root Hub characteristics A
1780 #define UHP_HcRhDescriptorB (76) // Root Hub characteristics B
1781 #define UHP_HcRhStatus (80) // Root Hub Status register
1782 #define UHP_HcRhPortStatus (84) // Root Hub Port Status Register
1784 // *****************************************************************************
1785 // SOFTWARE API DEFINITION FOR Image Sensor Interface
1786 // *****************************************************************************
1787 // *** Register offset in AT91S_ISI structure ***
1788 #define ISI_CR1 ( 0) // Control Register 1
1789 #define ISI_CR2 ( 4) // Control Register 2
1790 #define ISI_SR ( 8) // Status Register
1791 #define ISI_IER (12) // Interrupt Enable Register
1792 #define ISI_IDR (16) // Interrupt Disable Register
1793 #define ISI_IMR (20) // Interrupt Mask Register
1794 #define ISI_PSIZE (32) // Preview Size Register
1795 #define ISI_PDECF (36) // Preview Decimation Factor Register
1796 #define ISI_PFBD (40) // Preview Frame Buffer Address Register
1797 #define ISI_CDBA (44) // Codec Dma Address Register
1798 #define ISI_Y2RSET0 (48) // Color Space Conversion Register
1799 #define ISI_Y2RSET1 (52) // Color Space Conversion Register
1800 #define ISI_R2YSET0 (56) // Color Space Conversion Register
1801 #define ISI_R2YSET1 (60) // Color Space Conversion Register
1802 #define ISI_R2YSET2 (64) // Color Space Conversion Register
1803 // -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 --------
1804 #define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset
1805 #define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable.
1806 #define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity
1807 #define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity
1808 #define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation
1809 #define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction
1810 #define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed
1811 #define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask
1812 #define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed
1813 #define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed
1814 #define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed
1815 #define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path
1816 #define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay
1817 #define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay
1818 // -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 --------
1819 #define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047]
1820 #define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode
1821 #define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode
1822 #define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits
1823 #define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits
1824 #define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits
1825 #define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode
1826 #define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap
1827 #define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data
1828 #define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]
1829 #define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)
1830 #define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)
1831 #define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)
1832 #define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)
1833 #define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration
1834 #define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B
1835 #define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R
1836 #define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB)
1837 #define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB)
1838 // -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register --------
1839 #define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame
1840 #define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable
1841 #define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset
1842 #define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error
1843 #define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow
1844 #define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow
1845 #define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty
1846 #define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty
1847 #define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun
1848 // -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register --------
1849 // -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register --------
1850 // -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register --------
1851 // -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register --------
1852 #define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path
1853 #define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path
1854 // -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register --------
1855 #define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0
1856 #define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1
1857 #define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2
1858 #define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3
1859 // -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register --------
1860 #define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4
1861 #define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset
1862 #define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset
1863 #define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset
1864 // -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register --------
1865 #define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0
1866 #define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1
1867 #define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2
1868 #define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset
1869 // -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register --------
1870 #define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3
1871 #define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4
1872 #define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5
1873 #define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset
1874 // -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register --------
1875 #define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6
1876 #define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7
1877 #define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8
1878 #define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset
1880 // *****************************************************************************
1881 // REGISTER ADDRESS DEFINITION FOR AT91SAM9260
1882 // *****************************************************************************
1883 // ========== Register definition for SYS peripheral ==========
1884 #define AT91C_SYS_GPBR3 (0xFFFFFFFF) // (SYS) General Purpose Register 3
1885 #define AT91C_SYS_GPBR1 (0xFFFFFFFF) // (SYS) General Purpose Register 1
1886 #define AT91C_SYS_GPBR2 (0xFFFFFFFF) // (SYS) General Purpose Register 2
1887 #define AT91C_SYS_GPBR0 (0xFFFFFFFF) // (SYS) General Purpose Register 0
1888 // ========== Register definition for EBI peripheral ==========
1889 #define AT91C_EBI_DUMMY (0xFFFFEA00) // (EBI) Dummy register - Do not use
1890 // ========== Register definition for HECC peripheral ==========
1891 #define AT91C_HECC_PR (0xFFFFE80C) // (HECC) ECC Parity register
1892 #define AT91C_HECC_MR (0xFFFFE804) // (HECC) ECC Page size register
1893 #define AT91C_HECC_NPR (0xFFFFE810) // (HECC) ECC Parity N register
1894 #define AT91C_HECC_SR (0xFFFFE808) // (HECC) ECC Status register
1895 #define AT91C_HECC_CR (0xFFFFE800) // (HECC) ECC reset register
1896 #define AT91C_HECC_VR (0xFFFFE8FC) // (HECC) ECC Version register
1897 // ========== Register definition for SDRAMC peripheral ==========
1898 #define AT91C_SDRAMC_ISR (0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register
1899 #define AT91C_SDRAMC_IDR (0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register
1900 #define AT91C_SDRAMC_MR (0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register
1901 #define AT91C_SDRAMC_CR (0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register
1902 #define AT91C_SDRAMC_LPR (0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register
1903 #define AT91C_SDRAMC_MDR (0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register
1904 #define AT91C_SDRAMC_TR (0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register
1905 #define AT91C_SDRAMC_HSR (0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register
1906 #define AT91C_SDRAMC_IER (0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register
1907 #define AT91C_SDRAMC_IMR (0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register
1908 // ========== Register definition for SMC peripheral ==========
1909 #define AT91C_SMC_CYCLE1 (0xFFFFEC18) // (SMC) Cycle Register for CS 1
1910 #define AT91C_SMC_CTRL7 (0xFFFFEC7C) // (SMC) Control Register for CS 7
1911 #define AT91C_SMC_CTRL2 (0xFFFFEC2C) // (SMC) Control Register for CS 2
1912 #define AT91C_SMC_PULSE2 (0xFFFFEC24) // (SMC) Pulse Register for CS 2
1913 #define AT91C_SMC_CTRL1 (0xFFFFEC1C) // (SMC) Control Register for CS 1
1914 #define AT91C_SMC_SETUP4 (0xFFFFEC40) // (SMC) Setup Register for CS 4
1915 #define AT91C_SMC_CYCLE3 (0xFFFFEC38) // (SMC) Cycle Register for CS 3
1916 #define AT91C_SMC_SETUP3 (0xFFFFEC30) // (SMC) Setup Register for CS 3
1917 #define AT91C_SMC_CYCLE2 (0xFFFFEC28) // (SMC) Cycle Register for CS 2
1918 #define AT91C_SMC_SETUP2 (0xFFFFEC20) // (SMC) Setup Register for CS 2
1919 #define AT91C_SMC_PULSE5 (0xFFFFEC54) // (SMC) Pulse Register for CS 5
1920 #define AT91C_SMC_CTRL4 (0xFFFFEC4C) // (SMC) Control Register for CS 4
1921 #define AT91C_SMC_PULSE4 (0xFFFFEC44) // (SMC) Pulse Register for CS 4
1922 #define AT91C_SMC_CTRL3 (0xFFFFEC3C) // (SMC) Control Register for CS 3
1923 #define AT91C_SMC_PULSE3 (0xFFFFEC34) // (SMC) Pulse Register for CS 3
1924 #define AT91C_SMC_PULSE0 (0xFFFFEC04) // (SMC) Pulse Register for CS 0
1925 #define AT91C_SMC_CYCLE4 (0xFFFFEC48) // (SMC) Cycle Register for CS 4
1926 #define AT91C_SMC_SETUP5 (0xFFFFEC50) // (SMC) Setup Register for CS 5
1927 #define AT91C_SMC_CYCLE5 (0xFFFFEC58) // (SMC) Cycle Register for CS 5
1928 #define AT91C_SMC_SETUP6 (0xFFFFEC60) // (SMC) Setup Register for CS 6
1929 #define AT91C_SMC_CYCLE6 (0xFFFFEC68) // (SMC) Cycle Register for CS 6
1930 #define AT91C_SMC_SETUP0 (0xFFFFEC00) // (SMC) Setup Register for CS 0
1931 #define AT91C_SMC_CYCLE0 (0xFFFFEC08) // (SMC) Cycle Register for CS 0
1932 #define AT91C_SMC_SETUP1 (0xFFFFEC10) // (SMC) Setup Register for CS 1
1933 #define AT91C_SMC_CTRL5 (0xFFFFEC5C) // (SMC) Control Register for CS 5
1934 #define AT91C_SMC_PULSE6 (0xFFFFEC64) // (SMC) Pulse Register for CS 6
1935 #define AT91C_SMC_CTRL6 (0xFFFFEC6C) // (SMC) Control Register for CS 6
1936 #define AT91C_SMC_PULSE7 (0xFFFFEC74) // (SMC) Pulse Register for CS 7
1937 #define AT91C_SMC_CTRL0 (0xFFFFEC0C) // (SMC) Control Register for CS 0
1938 #define AT91C_SMC_PULSE1 (0xFFFFEC14) // (SMC) Pulse Register for CS 1
1939 #define AT91C_SMC_SETUP7 (0xFFFFEC70) // (SMC) Setup Register for CS 7
1940 #define AT91C_SMC_CYCLE7 (0xFFFFEC78) // (SMC) Cycle Register for CS 7
1941 // ========== Register definition for MATRIX peripheral ==========
1942 #define AT91C_MATRIX_MCFG1 (0xFFFFEE04) // (MATRIX) Master Configuration Register 1 (rom)
1943 #define AT91C_MATRIX_MRCR (0xFFFFEF00) // (MATRIX) Master Remp Control Register
1944 #define AT91C_MATRIX_PRAS4 (0xFFFFEEA0) // (MATRIX) PRAS4 (periph)
1945 #define AT91C_MATRIX_SCFG4 (0xFFFFEE50) // (MATRIX) Slave Configuration Register 4 (bridge)
1946 #define AT91C_MATRIX_MCFG2 (0xFFFFEE08) // (MATRIX) Master Configuration Register 2 (hperiphs)
1947 #define AT91C_MATRIX_MCFG0 (0xFFFFEE00) // (MATRIX) Master Configuration Register 0 (ram96k)
1948 #define AT91C_MATRIX_MCFG3 (0xFFFFEE0C) // (MATRIX) Master Configuration Register 3 (ebi)
1949 #define AT91C_MATRIX_MCFG4 (0xFFFFEE10) // (MATRIX) Master Configuration Register 4 (bridge)
1950 #define AT91C_MATRIX_MCFG5 (0xFFFFEE14) // (MATRIX) Master Configuration Register 5 (mailbox)
1951 #define AT91C_MATRIX_PRAS0 (0xFFFFEE80) // (MATRIX) PRAS0 (ram0)
1952 #define AT91C_MATRIX_PRAS1 (0xFFFFEE88) // (MATRIX) PRAS1 (ram1)
1953 #define AT91C_MATRIX_PRAS2 (0xFFFFEE90) // (MATRIX) PRAS2 (ram2)
1954 #define AT91C_MATRIX_PRAS3 (0xFFFFEE98) // (MATRIX) PRAS3 (ebi)
1955 #define AT91C_MATRIX_SCFG2 (0xFFFFEE48) // (MATRIX) Slave Configuration Register 2 (hperiphs)
1956 #define AT91C_MATRIX_SCFG0 (0xFFFFEE40) // (MATRIX) Slave Configuration Register 0 (ram96k)
1957 #define AT91C_MATRIX_SCFG3 (0xFFFFEE4C) // (MATRIX) Slave Configuration Register 3 (ebi)
1958 #define AT91C_MATRIX_SCFG1 (0xFFFFEE44) // (MATRIX) Slave Configuration Register 1 (rom)
1959 // ========== Register definition for CCFG peripheral ==========
1960 #define AT91C_CCFG_MATRIXVERSION (0xFFFFEFFC) // (CCFG) Version Register
1961 #define AT91C_CCFG_EBICSA (0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register
1962 // ========== Register definition for PDC_DBGU peripheral ==========
1963 #define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
1964 #define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
1965 #define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
1966 #define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
1967 #define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
1968 #define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
1969 #define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
1970 #define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
1971 #define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
1972 #define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
1973 // ========== Register definition for DBGU peripheral ==========
1974 #define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register
1975 #define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register
1976 #define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register
1977 #define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register
1978 #define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register
1979 #define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register
1980 #define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register
1981 #define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register
1982 #define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register
1983 #define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register
1984 #define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register
1985 #define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register
1986 // ========== Register definition for AIC peripheral ==========
1987 #define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
1988 #define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
1989 #define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register
1990 #define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
1991 #define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
1992 #define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)
1993 #define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register
1994 #define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register
1995 #define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
1996 #define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register
1997 #define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
1998 #define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register
1999 #define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
2000 #define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
2001 #define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
2002 #define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register
2003 #define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
2004 #define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
2005 // ========== Register definition for PIOA peripheral ==========
2006 #define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register
2007 #define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register
2008 #define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register
2009 #define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register
2010 #define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register
2011 #define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register
2012 #define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register
2013 #define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register
2014 #define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register
2015 #define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register
2016 #define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register
2017 #define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register
2018 #define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register
2019 #define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register
2020 #define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr
2021 #define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register
2022 #define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register
2023 #define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register
2024 #define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register
2025 #define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register
2026 #define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register
2027 #define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register
2028 #define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register
2029 #define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register
2030 #define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register
2031 #define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register
2032 #define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register
2033 #define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register
2034 #define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register
2035 // ========== Register definition for PIOB peripheral ==========
2036 #define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register
2037 #define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register
2038 #define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register
2039 #define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register
2040 #define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register
2041 #define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register
2042 #define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register
2043 #define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register
2044 #define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register
2045 #define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register
2046 #define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register
2047 #define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register
2048 #define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register
2049 #define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr
2050 #define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register
2051 #define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register
2052 #define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register
2053 #define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register
2054 #define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register
2055 #define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register
2056 #define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register
2057 #define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register
2058 #define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register
2059 #define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register
2060 #define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register
2061 #define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register
2062 #define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register
2063 #define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register
2064 #define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register
2065 // ========== Register definition for PIOC peripheral ==========
2066 #define AT91C_PIOC_IFDR (0xFFFFF824) // (PIOC) Input Filter Disable Register
2067 #define AT91C_PIOC_ODR (0xFFFFF814) // (PIOC) Output Disable Registerr
2068 #define AT91C_PIOC_ABSR (0xFFFFF878) // (PIOC) AB Select Status Register
2069 #define AT91C_PIOC_SODR (0xFFFFF830) // (PIOC) Set Output Data Register
2070 #define AT91C_PIOC_IFSR (0xFFFFF828) // (PIOC) Input Filter Status Register
2071 #define AT91C_PIOC_CODR (0xFFFFF834) // (PIOC) Clear Output Data Register
2072 #define AT91C_PIOC_ODSR (0xFFFFF838) // (PIOC) Output Data Status Register
2073 #define AT91C_PIOC_IER (0xFFFFF840) // (PIOC) Interrupt Enable Register
2074 #define AT91C_PIOC_IMR (0xFFFFF848) // (PIOC) Interrupt Mask Register
2075 #define AT91C_PIOC_OWDR (0xFFFFF8A4) // (PIOC) Output Write Disable Register
2076 #define AT91C_PIOC_MDDR (0xFFFFF854) // (PIOC) Multi-driver Disable Register
2077 #define AT91C_PIOC_PDSR (0xFFFFF83C) // (PIOC) Pin Data Status Register
2078 #define AT91C_PIOC_IDR (0xFFFFF844) // (PIOC) Interrupt Disable Register
2079 #define AT91C_PIOC_ISR (0xFFFFF84C) // (PIOC) Interrupt Status Register
2080 #define AT91C_PIOC_PDR (0xFFFFF804) // (PIOC) PIO Disable Register
2081 #define AT91C_PIOC_OWSR (0xFFFFF8A8) // (PIOC) Output Write Status Register
2082 #define AT91C_PIOC_OWER (0xFFFFF8A0) // (PIOC) Output Write Enable Register
2083 #define AT91C_PIOC_ASR (0xFFFFF870) // (PIOC) Select A Register
2084 #define AT91C_PIOC_PPUSR (0xFFFFF868) // (PIOC) Pull-up Status Register
2085 #define AT91C_PIOC_PPUDR (0xFFFFF860) // (PIOC) Pull-up Disable Register
2086 #define AT91C_PIOC_MDSR (0xFFFFF858) // (PIOC) Multi-driver Status Register
2087 #define AT91C_PIOC_MDER (0xFFFFF850) // (PIOC) Multi-driver Enable Register
2088 #define AT91C_PIOC_IFER (0xFFFFF820) // (PIOC) Input Filter Enable Register
2089 #define AT91C_PIOC_OSR (0xFFFFF818) // (PIOC) Output Status Register
2090 #define AT91C_PIOC_OER (0xFFFFF810) // (PIOC) Output Enable Register
2091 #define AT91C_PIOC_PSR (0xFFFFF808) // (PIOC) PIO Status Register
2092 #define AT91C_PIOC_PER (0xFFFFF800) // (PIOC) PIO Enable Register
2093 #define AT91C_PIOC_BSR (0xFFFFF874) // (PIOC) Select B Register
2094 #define AT91C_PIOC_PPUER (0xFFFFF864) // (PIOC) Pull-up Enable Register
2095 // ========== Register definition for CKGR peripheral ==========
2096 #define AT91C_CKGR_PLLBR (0xFFFFFC2C) // (CKGR) PLL B Register
2097 #define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register
2098 #define AT91C_CKGR_PLLAR (0xFFFFFC28) // (CKGR) PLL A Register
2099 #define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register
2100 // ========== Register definition for PMC peripheral ==========
2101 #define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register
2102 #define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register
2103 #define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register
2104 #define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register
2105 #define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
2106 #define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register
2107 #define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register
2108 #define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register
2109 #define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register
2110 #define AT91C_PMC_PLLAR (0xFFFFFC28) // (PMC) PLL A Register
2111 #define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register
2112 #define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
2113 #define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
2114 #define AT91C_PMC_PLLBR (0xFFFFFC2C) // (PMC) PLL B Register
2115 #define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register
2116 #define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register
2117 // ========== Register definition for RSTC peripheral ==========
2118 #define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register
2119 #define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register
2120 #define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register
2121 // ========== Register definition for SHDWC peripheral ==========
2122 #define AT91C_SHDWC_SHMR (0xFFFFFD14) // (SHDWC) Shut Down Mode Register
2123 #define AT91C_SHDWC_SHSR (0xFFFFFD18) // (SHDWC) Shut Down Status Register
2124 #define AT91C_SHDWC_SHCR (0xFFFFFD10) // (SHDWC) Shut Down Control Register
2125 // ========== Register definition for RTTC peripheral ==========
2126 #define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register
2127 #define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register
2128 #define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register
2129 #define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register
2130 // ========== Register definition for PITC peripheral ==========
2131 #define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register
2132 #define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register
2133 #define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register
2134 #define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register
2135 // ========== Register definition for WDTC peripheral ==========
2136 #define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register
2137 #define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register
2138 #define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register
2139 // ========== Register definition for TC0 peripheral ==========
2140 #define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register
2141 #define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register
2142 #define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C
2143 #define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A
2144 #define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
2145 #define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register
2146 #define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register
2147 #define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B
2148 #define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value
2149 #define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register
2150 // ========== Register definition for TC1 peripheral ==========
2151 #define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register
2152 #define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register
2153 #define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C
2154 #define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A
2155 #define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
2156 #define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register
2157 #define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register
2158 #define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B
2159 #define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value
2160 #define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register
2161 // ========== Register definition for TC2 peripheral ==========
2162 #define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register
2163 #define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register
2164 #define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C
2165 #define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A
2166 #define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
2167 #define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register
2168 #define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register
2169 #define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B
2170 #define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value
2171 #define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register
2172 // ========== Register definition for TC3 peripheral ==========
2173 #define AT91C_TC3_IMR (0xFFFDC02C) // (TC3) Interrupt Mask Register
2174 #define AT91C_TC3_IER (0xFFFDC024) // (TC3) Interrupt Enable Register
2175 #define AT91C_TC3_RC (0xFFFDC01C) // (TC3) Register C
2176 #define AT91C_TC3_RA (0xFFFDC014) // (TC3) Register A
2177 #define AT91C_TC3_CMR (0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)
2178 #define AT91C_TC3_IDR (0xFFFDC028) // (TC3) Interrupt Disable Register
2179 #define AT91C_TC3_SR (0xFFFDC020) // (TC3) Status Register
2180 #define AT91C_TC3_RB (0xFFFDC018) // (TC3) Register B
2181 #define AT91C_TC3_CV (0xFFFDC010) // (TC3) Counter Value
2182 #define AT91C_TC3_CCR (0xFFFDC000) // (TC3) Channel Control Register
2183 // ========== Register definition for TC4 peripheral ==========
2184 #define AT91C_TC4_IMR (0xFFFDC06C) // (TC4) Interrupt Mask Register
2185 #define AT91C_TC4_IER (0xFFFDC064) // (TC4) Interrupt Enable Register
2186 #define AT91C_TC4_RC (0xFFFDC05C) // (TC4) Register C
2187 #define AT91C_TC4_RA (0xFFFDC054) // (TC4) Register A
2188 #define AT91C_TC4_CMR (0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)
2189 #define AT91C_TC4_IDR (0xFFFDC068) // (TC4) Interrupt Disable Register
2190 #define AT91C_TC4_SR (0xFFFDC060) // (TC4) Status Register
2191 #define AT91C_TC4_RB (0xFFFDC058) // (TC4) Register B
2192 #define AT91C_TC4_CV (0xFFFDC050) // (TC4) Counter Value
2193 #define AT91C_TC4_CCR (0xFFFDC040) // (TC4) Channel Control Register
2194 // ========== Register definition for TC5 peripheral ==========
2195 #define AT91C_TC5_IDR (0xFFFDC0A8) // (TC5) Interrupt Disable Register
2196 #define AT91C_TC5_CMR (0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)
2197 #define AT91C_TC5_RB (0xFFFDC098) // (TC5) Register B
2198 #define AT91C_TC5_CV (0xFFFDC090) // (TC5) Counter Value
2199 #define AT91C_TC5_CCR (0xFFFDC080) // (TC5) Channel Control Register
2200 #define AT91C_TC5_SR (0xFFFDC0A0) // (TC5) Status Register
2201 #define AT91C_TC5_RA (0xFFFDC094) // (TC5) Register A
2202 #define AT91C_TC5_RC (0xFFFDC09C) // (TC5) Register C
2203 #define AT91C_TC5_IMR (0xFFFDC0AC) // (TC5) Interrupt Mask Register
2204 #define AT91C_TC5_IER (0xFFFDC0A4) // (TC5) Interrupt Enable Register
2205 // ========== Register definition for TCB0 peripheral ==========
2206 #define AT91C_TCB0_BMR (0xFFFA00C4) // (TCB0) TC Block Mode Register
2207 #define AT91C_TCB0_BCR (0xFFFA00C0) // (TCB0) TC Block Control Register
2208 // ========== Register definition for TCB1 peripheral ==========
2209 #define AT91C_TCB1_BCR (0xFFFDC0C0) // (TCB1) TC Block Control Register
2210 #define AT91C_TCB1_BMR (0xFFFDC0C4) // (TCB1) TC Block Mode Register
2211 // ========== Register definition for PDC_MCI peripheral ==========
2212 #define AT91C_MCI_PTSR (0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register
2213 #define AT91C_MCI_TNCR (0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register
2214 #define AT91C_MCI_RNCR (0xFFFA8114) // (PDC_MCI) Receive Next Counter Register
2215 #define AT91C_MCI_TCR (0xFFFA810C) // (PDC_MCI) Transmit Counter Register
2216 #define AT91C_MCI_RCR (0xFFFA8104) // (PDC_MCI) Receive Counter Register
2217 #define AT91C_MCI_PTCR (0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register
2218 #define AT91C_MCI_TNPR (0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register
2219 #define AT91C_MCI_RNPR (0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register
2220 #define AT91C_MCI_TPR (0xFFFA8108) // (PDC_MCI) Transmit Pointer Register
2221 #define AT91C_MCI_RPR (0xFFFA8100) // (PDC_MCI) Receive Pointer Register
2222 // ========== Register definition for MCI peripheral ==========
2223 #define AT91C_MCI_VR (0xFFFA80FC) // (MCI) MCI Version Register
2224 #define AT91C_MCI_RSPR (0xFFFA8020) // (MCI) MCI Response Register
2225 #define AT91C_MCI_BLKR (0xFFFA8018) // (MCI) MCI Block Register
2226 #define AT91C_MCI_ARGR (0xFFFA8010) // (MCI) MCI Argument Register
2227 #define AT91C_MCI_DTOR (0xFFFA8008) // (MCI) MCI Data Timeout Register
2228 #define AT91C_MCI_CR (0xFFFA8000) // (MCI) MCI Control Register
2229 #define AT91C_MCI_TDR (0xFFFA8034) // (MCI) MCI Transmit Data Register
2230 #define AT91C_MCI_CMDR (0xFFFA8014) // (MCI) MCI Command Register
2231 #define AT91C_MCI_IDR (0xFFFA8048) // (MCI) MCI Interrupt Disable Register
2232 #define AT91C_MCI_SR (0xFFFA8040) // (MCI) MCI Status Register
2233 #define AT91C_MCI_RDR (0xFFFA8030) // (MCI) MCI Receive Data Register
2234 #define AT91C_MCI_IMR (0xFFFA804C) // (MCI) MCI Interrupt Mask Register
2235 #define AT91C_MCI_IER (0xFFFA8044) // (MCI) MCI Interrupt Enable Register
2236 #define AT91C_MCI_MR (0xFFFA8004) // (MCI) MCI Mode Register
2237 #define AT91C_MCI_SDCR (0xFFFA800C) // (MCI) MCI SD Card Register
2238 // ========== Register definition for PDC_TWI peripheral ==========
2239 #define AT91C_TWI_RCR (0xFFFAC104) // (PDC_TWI) Receive Counter Register
2240 #define AT91C_TWI_PTCR (0xFFFAC120) // (PDC_TWI) PDC Transfer Control Register
2241 #define AT91C_TWI_TNPR (0xFFFAC118) // (PDC_TWI) Transmit Next Pointer Register
2242 #define AT91C_TWI_RNPR (0xFFFAC110) // (PDC_TWI) Receive Next Pointer Register
2243 #define AT91C_TWI_TPR (0xFFFAC108) // (PDC_TWI) Transmit Pointer Register
2244 #define AT91C_TWI_RPR (0xFFFAC100) // (PDC_TWI) Receive Pointer Register
2245 #define AT91C_TWI_PTSR (0xFFFAC124) // (PDC_TWI) PDC Transfer Status Register
2246 #define AT91C_TWI_TNCR (0xFFFAC11C) // (PDC_TWI) Transmit Next Counter Register
2247 #define AT91C_TWI_RNCR (0xFFFAC114) // (PDC_TWI) Receive Next Counter Register
2248 #define AT91C_TWI_TCR (0xFFFAC10C) // (PDC_TWI) Transmit Counter Register
2249 // ========== Register definition for TWI peripheral ==========
2250 #define AT91C_TWI_THR (0xFFFAC034) // (TWI) Transmit Holding Register
2251 #define AT91C_TWI_IMR (0xFFFAC02C) // (TWI) Interrupt Mask Register
2252 #define AT91C_TWI_IER (0xFFFAC024) // (TWI) Interrupt Enable Register
2253 #define AT91C_TWI_IADR (0xFFFAC00C) // (TWI) Internal Address Register
2254 #define AT91C_TWI_MMR (0xFFFAC004) // (TWI) Master Mode Register
2255 #define AT91C_TWI_RHR (0xFFFAC030) // (TWI) Receive Holding Register
2256 #define AT91C_TWI_IDR (0xFFFAC028) // (TWI) Interrupt Disable Register
2257 #define AT91C_TWI_SR (0xFFFAC020) // (TWI) Status Register
2258 #define AT91C_TWI_CWGR (0xFFFAC010) // (TWI) Clock Waveform Generator Register
2259 #define AT91C_TWI_CR (0xFFFAC000) // (TWI) Control Register
2260 // ========== Register definition for PDC_US0 peripheral ==========
2261 #define AT91C_US0_TNCR (0xFFFB011C) // (PDC_US0) Transmit Next Counter Register
2262 #define AT91C_US0_RNCR (0xFFFB0114) // (PDC_US0) Receive Next Counter Register
2263 #define AT91C_US0_TCR (0xFFFB010C) // (PDC_US0) Transmit Counter Register
2264 #define AT91C_US0_RCR (0xFFFB0104) // (PDC_US0) Receive Counter Register
2265 #define AT91C_US0_PTCR (0xFFFB0120) // (PDC_US0) PDC Transfer Control Register
2266 #define AT91C_US0_TNPR (0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register
2267 #define AT91C_US0_RNPR (0xFFFB0110) // (PDC_US0) Receive Next Pointer Register
2268 #define AT91C_US0_PTSR (0xFFFB0124) // (PDC_US0) PDC Transfer Status Register
2269 #define AT91C_US0_RPR (0xFFFB0100) // (PDC_US0) Receive Pointer Register
2270 #define AT91C_US0_TPR (0xFFFB0108) // (PDC_US0) Transmit Pointer Register
2271 // ========== Register definition for US0 peripheral ==========
2272 #define AT91C_US0_IF (0xFFFB004C) // (US0) IRDA_FILTER Register
2273 #define AT91C_US0_NER (0xFFFB0044) // (US0) Nb Errors Register
2274 #define AT91C_US0_RTOR (0xFFFB0024) // (US0) Receiver Time-out Register
2275 #define AT91C_US0_THR (0xFFFB001C) // (US0) Transmitter Holding Register
2276 #define AT91C_US0_CSR (0xFFFB0014) // (US0) Channel Status Register
2277 #define AT91C_US0_IDR (0xFFFB000C) // (US0) Interrupt Disable Register
2278 #define AT91C_US0_MR (0xFFFB0004) // (US0) Mode Register
2279 #define AT91C_US0_FIDI (0xFFFB0040) // (US0) FI_DI_Ratio Register
2280 #define AT91C_US0_TTGR (0xFFFB0028) // (US0) Transmitter Time-guard Register
2281 #define AT91C_US0_BRGR (0xFFFB0020) // (US0) Baud Rate Generator Register
2282 #define AT91C_US0_RHR (0xFFFB0018) // (US0) Receiver Holding Register
2283 #define AT91C_US0_IMR (0xFFFB0010) // (US0) Interrupt Mask Register
2284 #define AT91C_US0_IER (0xFFFB0008) // (US0) Interrupt Enable Register
2285 #define AT91C_US0_CR (0xFFFB0000) // (US0) Control Register
2286 // ========== Register definition for PDC_US1 peripheral ==========
2287 #define AT91C_US1_PTCR (0xFFFB4120) // (PDC_US1) PDC Transfer Control Register
2288 #define AT91C_US1_TNPR (0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register
2289 #define AT91C_US1_RNPR (0xFFFB4110) // (PDC_US1) Receive Next Pointer Register
2290 #define AT91C_US1_TPR (0xFFFB4108) // (PDC_US1) Transmit Pointer Register
2291 #define AT91C_US1_RPR (0xFFFB4100) // (PDC_US1) Receive Pointer Register
2292 #define AT91C_US1_PTSR (0xFFFB4124) // (PDC_US1) PDC Transfer Status Register
2293 #define AT91C_US1_TNCR (0xFFFB411C) // (PDC_US1) Transmit Next Counter Register
2294 #define AT91C_US1_RNCR (0xFFFB4114) // (PDC_US1) Receive Next Counter Register
2295 #define AT91C_US1_TCR (0xFFFB410C) // (PDC_US1) Transmit Counter Register
2296 #define AT91C_US1_RCR (0xFFFB4104) // (PDC_US1) Receive Counter Register
2297 // ========== Register definition for US1 peripheral ==========
2298 #define AT91C_US1_FIDI (0xFFFB4040) // (US1) FI_DI_Ratio Register
2299 #define AT91C_US1_TTGR (0xFFFB4028) // (US1) Transmitter Time-guard Register
2300 #define AT91C_US1_BRGR (0xFFFB4020) // (US1) Baud Rate Generator Register
2301 #define AT91C_US1_RHR (0xFFFB4018) // (US1) Receiver Holding Register
2302 #define AT91C_US1_IMR (0xFFFB4010) // (US1) Interrupt Mask Register
2303 #define AT91C_US1_IER (0xFFFB4008) // (US1) Interrupt Enable Register
2304 #define AT91C_US1_CR (0xFFFB4000) // (US1) Control Register
2305 #define AT91C_US1_IF (0xFFFB404C) // (US1) IRDA_FILTER Register
2306 #define AT91C_US1_NER (0xFFFB4044) // (US1) Nb Errors Register
2307 #define AT91C_US1_RTOR (0xFFFB4024) // (US1) Receiver Time-out Register
2308 #define AT91C_US1_THR (0xFFFB401C) // (US1) Transmitter Holding Register
2309 #define AT91C_US1_CSR (0xFFFB4014) // (US1) Channel Status Register
2310 #define AT91C_US1_IDR (0xFFFB400C) // (US1) Interrupt Disable Register
2311 #define AT91C_US1_MR (0xFFFB4004) // (US1) Mode Register
2312 // ========== Register definition for PDC_US2 peripheral ==========
2313 #define AT91C_US2_PTSR (0xFFFB8124) // (PDC_US2) PDC Transfer Status Register
2314 #define AT91C_US2_TNCR (0xFFFB811C) // (PDC_US2) Transmit Next Counter Register
2315 #define AT91C_US2_RNCR (0xFFFB8114) // (PDC_US2) Receive Next Counter Register
2316 #define AT91C_US2_TCR (0xFFFB810C) // (PDC_US2) Transmit Counter Register
2317 #define AT91C_US2_RCR (0xFFFB8104) // (PDC_US2) Receive Counter Register
2318 #define AT91C_US2_PTCR (0xFFFB8120) // (PDC_US2) PDC Transfer Control Register
2319 #define AT91C_US2_TNPR (0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register
2320 #define AT91C_US2_RNPR (0xFFFB8110) // (PDC_US2) Receive Next Pointer Register
2321 #define AT91C_US2_TPR (0xFFFB8108) // (PDC_US2) Transmit Pointer Register
2322 #define AT91C_US2_RPR (0xFFFB8100) // (PDC_US2) Receive Pointer Register
2323 // ========== Register definition for US2 peripheral ==========
2324 #define AT91C_US2_FIDI (0xFFFB8040) // (US2) FI_DI_Ratio Register
2325 #define AT91C_US2_TTGR (0xFFFB8028) // (US2) Transmitter Time-guard Register
2326 #define AT91C_US2_BRGR (0xFFFB8020) // (US2) Baud Rate Generator Register
2327 #define AT91C_US2_RHR (0xFFFB8018) // (US2) Receiver Holding Register
2328 #define AT91C_US2_IMR (0xFFFB8010) // (US2) Interrupt Mask Register
2329 #define AT91C_US2_IER (0xFFFB8008) // (US2) Interrupt Enable Register
2330 #define AT91C_US2_CR (0xFFFB8000) // (US2) Control Register
2331 #define AT91C_US2_IF (0xFFFB804C) // (US2) IRDA_FILTER Register
2332 #define AT91C_US2_NER (0xFFFB8044) // (US2) Nb Errors Register
2333 #define AT91C_US2_RTOR (0xFFFB8024) // (US2) Receiver Time-out Register
2334 #define AT91C_US2_THR (0xFFFB801C) // (US2) Transmitter Holding Register
2335 #define AT91C_US2_CSR (0xFFFB8014) // (US2) Channel Status Register
2336 #define AT91C_US2_IDR (0xFFFB800C) // (US2) Interrupt Disable Register
2337 #define AT91C_US2_MR (0xFFFB8004) // (US2) Mode Register
2338 // ========== Register definition for PDC_US3 peripheral ==========
2339 #define AT91C_US3_PTCR (0xFFFD0120) // (PDC_US3) PDC Transfer Control Register
2340 #define AT91C_US3_TNPR (0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register
2341 #define AT91C_US3_RNPR (0xFFFD0110) // (PDC_US3) Receive Next Pointer Register
2342 #define AT91C_US3_TPR (0xFFFD0108) // (PDC_US3) Transmit Pointer Register
2343 #define AT91C_US3_RPR (0xFFFD0100) // (PDC_US3) Receive Pointer Register
2344 #define AT91C_US3_PTSR (0xFFFD0124) // (PDC_US3) PDC Transfer Status Register
2345 #define AT91C_US3_TNCR (0xFFFD011C) // (PDC_US3) Transmit Next Counter Register
2346 #define AT91C_US3_RNCR (0xFFFD0114) // (PDC_US3) Receive Next Counter Register
2347 #define AT91C_US3_TCR (0xFFFD010C) // (PDC_US3) Transmit Counter Register
2348 #define AT91C_US3_RCR (0xFFFD0104) // (PDC_US3) Receive Counter Register
2349 // ========== Register definition for US3 peripheral ==========
2350 #define AT91C_US3_IF (0xFFFD004C) // (US3) IRDA_FILTER Register
2351 #define AT91C_US3_NER (0xFFFD0044) // (US3) Nb Errors Register
2352 #define AT91C_US3_RTOR (0xFFFD0024) // (US3) Receiver Time-out Register
2353 #define AT91C_US3_THR (0xFFFD001C) // (US3) Transmitter Holding Register
2354 #define AT91C_US3_CSR (0xFFFD0014) // (US3) Channel Status Register
2355 #define AT91C_US3_IDR (0xFFFD000C) // (US3) Interrupt Disable Register
2356 #define AT91C_US3_MR (0xFFFD0004) // (US3) Mode Register
2357 #define AT91C_US3_FIDI (0xFFFD0040) // (US3) FI_DI_Ratio Register
2358 #define AT91C_US3_TTGR (0xFFFD0028) // (US3) Transmitter Time-guard Register
2359 #define AT91C_US3_BRGR (0xFFFD0020) // (US3) Baud Rate Generator Register
2360 #define AT91C_US3_RHR (0xFFFD0018) // (US3) Receiver Holding Register
2361 #define AT91C_US3_IMR (0xFFFD0010) // (US3) Interrupt Mask Register
2362 #define AT91C_US3_IER (0xFFFD0008) // (US3) Interrupt Enable Register
2363 #define AT91C_US3_CR (0xFFFD0000) // (US3) Control Register
2364 // ========== Register definition for PDC_US4 peripheral ==========
2365 #define AT91C_US4_PTCR (0xFFFD4120) // (PDC_US4) PDC Transfer Control Register
2366 #define AT91C_US4_TNPR (0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register
2367 #define AT91C_US4_RNPR (0xFFFD4110) // (PDC_US4) Receive Next Pointer Register
2368 #define AT91C_US4_TPR (0xFFFD4108) // (PDC_US4) Transmit Pointer Register
2369 #define AT91C_US4_RPR (0xFFFD4100) // (PDC_US4) Receive Pointer Register
2370 #define AT91C_US4_PTSR (0xFFFD4124) // (PDC_US4) PDC Transfer Status Register
2371 #define AT91C_US4_TNCR (0xFFFD411C) // (PDC_US4) Transmit Next Counter Register
2372 #define AT91C_US4_RNCR (0xFFFD4114) // (PDC_US4) Receive Next Counter Register
2373 #define AT91C_US4_TCR (0xFFFD410C) // (PDC_US4) Transmit Counter Register
2374 #define AT91C_US4_RCR (0xFFFD4104) // (PDC_US4) Receive Counter Register
2375 // ========== Register definition for US4 peripheral ==========
2376 #define AT91C_US4_CSR (0xFFFD4014) // (US4) Channel Status Register
2377 #define AT91C_US4_IDR (0xFFFD400C) // (US4) Interrupt Disable Register
2378 #define AT91C_US4_MR (0xFFFD4004) // (US4) Mode Register
2379 #define AT91C_US4_TTGR (0xFFFD4028) // (US4) Transmitter Time-guard Register
2380 #define AT91C_US4_BRGR (0xFFFD4020) // (US4) Baud Rate Generator Register
2381 #define AT91C_US4_RHR (0xFFFD4018) // (US4) Receiver Holding Register
2382 #define AT91C_US4_IMR (0xFFFD4010) // (US4) Interrupt Mask Register
2383 #define AT91C_US4_NER (0xFFFD4044) // (US4) Nb Errors Register
2384 #define AT91C_US4_RTOR (0xFFFD4024) // (US4) Receiver Time-out Register
2385 #define AT91C_US4_FIDI (0xFFFD4040) // (US4) FI_DI_Ratio Register
2386 #define AT91C_US4_CR (0xFFFD4000) // (US4) Control Register
2387 #define AT91C_US4_IER (0xFFFD4008) // (US4) Interrupt Enable Register
2388 #define AT91C_US4_IF (0xFFFD404C) // (US4) IRDA_FILTER Register
2389 #define AT91C_US4_THR (0xFFFD401C) // (US4) Transmitter Holding Register
2390 // ========== Register definition for PDC_US5 peripheral ==========
2391 #define AT91C_US5_PTCR (0xFFFD8120) // (PDC_US5) PDC Transfer Control Register
2392 #define AT91C_US5_TNPR (0xFFFD8118) // (PDC_US5) Transmit Next Pointer Register
2393 #define AT91C_US5_RNPR (0xFFFD8110) // (PDC_US5) Receive Next Pointer Register
2394 #define AT91C_US5_TPR (0xFFFD8108) // (PDC_US5) Transmit Pointer Register
2395 #define AT91C_US5_RPR (0xFFFD8100) // (PDC_US5) Receive Pointer Register
2396 #define AT91C_US5_PTSR (0xFFFD8124) // (PDC_US5) PDC Transfer Status Register
2397 #define AT91C_US5_TNCR (0xFFFD811C) // (PDC_US5) Transmit Next Counter Register
2398 #define AT91C_US5_RNCR (0xFFFD8114) // (PDC_US5) Receive Next Counter Register
2399 #define AT91C_US5_TCR (0xFFFD810C) // (PDC_US5) Transmit Counter Register
2400 #define AT91C_US5_RCR (0xFFFD8104) // (PDC_US5) Receive Counter Register
2401 // ========== Register definition for US5 peripheral ==========
2402 #define AT91C_US5_IF (0xFFFD804C) // (US5) IRDA_FILTER Register
2403 #define AT91C_US5_NER (0xFFFD8044) // (US5) Nb Errors Register
2404 #define AT91C_US5_MR (0xFFFD8004) // (US5) Mode Register
2405 #define AT91C_US5_RHR (0xFFFD8018) // (US5) Receiver Holding Register
2406 #define AT91C_US5_IMR (0xFFFD8010) // (US5) Interrupt Mask Register
2407 #define AT91C_US5_IER (0xFFFD8008) // (US5) Interrupt Enable Register
2408 #define AT91C_US5_CR (0xFFFD8000) // (US5) Control Register
2409 #define AT91C_US5_IDR (0xFFFD800C) // (US5) Interrupt Disable Register
2410 #define AT91C_US5_CSR (0xFFFD8014) // (US5) Channel Status Register
2411 #define AT91C_US5_THR (0xFFFD801C) // (US5) Transmitter Holding Register
2412 #define AT91C_US5_RTOR (0xFFFD8024) // (US5) Receiver Time-out Register
2413 #define AT91C_US5_FIDI (0xFFFD8040) // (US5) FI_DI_Ratio Register
2414 #define AT91C_US5_BRGR (0xFFFD8020) // (US5) Baud Rate Generator Register
2415 #define AT91C_US5_TTGR (0xFFFD8028) // (US5) Transmitter Time-guard Register
2416 // ========== Register definition for PDC_SSC0 peripheral ==========
2417 #define AT91C_SSC0_PTSR (0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register
2418 #define AT91C_SSC0_TNCR (0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register
2419 #define AT91C_SSC0_RNCR (0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register
2420 #define AT91C_SSC0_TCR (0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register
2421 #define AT91C_SSC0_RCR (0xFFFBC104) // (PDC_SSC0) Receive Counter Register
2422 #define AT91C_SSC0_PTCR (0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register
2423 #define AT91C_SSC0_TNPR (0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register
2424 #define AT91C_SSC0_RNPR (0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register
2425 #define AT91C_SSC0_TPR (0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register
2426 #define AT91C_SSC0_RPR (0xFFFBC100) // (PDC_SSC0) Receive Pointer Register
2427 // ========== Register definition for SSC0 peripheral ==========
2428 #define AT91C_SSC0_RHR (0xFFFBC020) // (SSC0) Receive Holding Register
2429 #define AT91C_SSC0_TCMR (0xFFFBC018) // (SSC0) Transmit Clock Mode Register
2430 #define AT91C_SSC0_RCMR (0xFFFBC010) // (SSC0) Receive Clock ModeRegister
2431 #define AT91C_SSC0_CR (0xFFFBC000) // (SSC0) Control Register
2432 #define AT91C_SSC0_TSHR (0xFFFBC034) // (SSC0) Transmit Sync Holding Register
2433 #define AT91C_SSC0_THR (0xFFFBC024) // (SSC0) Transmit Holding Register
2434 #define AT91C_SSC0_TFMR (0xFFFBC01C) // (SSC0) Transmit Frame Mode Register
2435 #define AT91C_SSC0_RFMR (0xFFFBC014) // (SSC0) Receive Frame Mode Register
2436 #define AT91C_SSC0_IDR (0xFFFBC048) // (SSC0) Interrupt Disable Register
2437 #define AT91C_SSC0_SR (0xFFFBC040) // (SSC0) Status Register
2438 #define AT91C_SSC0_RSHR (0xFFFBC030) // (SSC0) Receive Sync Holding Register
2439 #define AT91C_SSC0_IMR (0xFFFBC04C) // (SSC0) Interrupt Mask Register
2440 #define AT91C_SSC0_IER (0xFFFBC044) // (SSC0) Interrupt Enable Register
2441 #define AT91C_SSC0_CMR (0xFFFBC004) // (SSC0) Clock Mode Register
2442 // ========== Register definition for PDC_SPI0 peripheral ==========
2443 #define AT91C_SPI0_PTSR (0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register
2444 #define AT91C_SPI0_TNCR (0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register
2445 #define AT91C_SPI0_RNCR (0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register
2446 #define AT91C_SPI0_TCR (0xFFFC810C) // (PDC_SPI0) Transmit Counter Register
2447 #define AT91C_SPI0_PTCR (0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register
2448 #define AT91C_SPI0_RCR (0xFFFC8104) // (PDC_SPI0) Receive Counter Register
2449 #define AT91C_SPI0_TNPR (0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register
2450 #define AT91C_SPI0_RPR (0xFFFC8100) // (PDC_SPI0) Receive Pointer Register
2451 #define AT91C_SPI0_TPR (0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register
2452 #define AT91C_SPI0_RNPR (0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register
2453 // ========== Register definition for SPI0 peripheral ==========
2454 #define AT91C_SPI0_CSR (0xFFFC8030) // (SPI0) Chip Select Register
2455 #define AT91C_SPI0_IDR (0xFFFC8018) // (SPI0) Interrupt Disable Register
2456 #define AT91C_SPI0_SR (0xFFFC8010) // (SPI0) Status Register
2457 #define AT91C_SPI0_RDR (0xFFFC8008) // (SPI0) Receive Data Register
2458 #define AT91C_SPI0_CR (0xFFFC8000) // (SPI0) Control Register
2459 #define AT91C_SPI0_IMR (0xFFFC801C) // (SPI0) Interrupt Mask Register
2460 #define AT91C_SPI0_IER (0xFFFC8014) // (SPI0) Interrupt Enable Register
2461 #define AT91C_SPI0_TDR (0xFFFC800C) // (SPI0) Transmit Data Register
2462 #define AT91C_SPI0_MR (0xFFFC8004) // (SPI0) Mode Register
2463 // ========== Register definition for PDC_SPI1 peripheral ==========
2464 #define AT91C_SPI1_PTSR (0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register
2465 #define AT91C_SPI1_TNCR (0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register
2466 #define AT91C_SPI1_RNCR (0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register
2467 #define AT91C_SPI1_TCR (0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register
2468 #define AT91C_SPI1_RCR (0xFFFCC104) // (PDC_SPI1) Receive Counter Register
2469 #define AT91C_SPI1_PTCR (0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register
2470 #define AT91C_SPI1_TNPR (0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register
2471 #define AT91C_SPI1_RNPR (0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register
2472 #define AT91C_SPI1_TPR (0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register
2473 #define AT91C_SPI1_RPR (0xFFFCC100) // (PDC_SPI1) Receive Pointer Register
2474 // ========== Register definition for SPI1 peripheral ==========
2475 #define AT91C_SPI1_IMR (0xFFFCC01C) // (SPI1) Interrupt Mask Register
2476 #define AT91C_SPI1_IER (0xFFFCC014) // (SPI1) Interrupt Enable Register
2477 #define AT91C_SPI1_TDR (0xFFFCC00C) // (SPI1) Transmit Data Register
2478 #define AT91C_SPI1_MR (0xFFFCC004) // (SPI1) Mode Register
2479 #define AT91C_SPI1_CSR (0xFFFCC030) // (SPI1) Chip Select Register
2480 #define AT91C_SPI1_IDR (0xFFFCC018) // (SPI1) Interrupt Disable Register
2481 #define AT91C_SPI1_SR (0xFFFCC010) // (SPI1) Status Register
2482 #define AT91C_SPI1_RDR (0xFFFCC008) // (SPI1) Receive Data Register
2483 #define AT91C_SPI1_CR (0xFFFCC000) // (SPI1) Control Register
2484 // ========== Register definition for PDC_ADC peripheral ==========
2485 #define AT91C_ADC_PTCR (0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register
2486 #define AT91C_ADC_TNPR (0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register
2487 #define AT91C_ADC_RNPR (0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register
2488 #define AT91C_ADC_TPR (0xFFFE0108) // (PDC_ADC) Transmit Pointer Register
2489 #define AT91C_ADC_RPR (0xFFFE0100) // (PDC_ADC) Receive Pointer Register
2490 #define AT91C_ADC_PTSR (0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register
2491 #define AT91C_ADC_TNCR (0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register
2492 #define AT91C_ADC_RNCR (0xFFFE0114) // (PDC_ADC) Receive Next Counter Register
2493 #define AT91C_ADC_TCR (0xFFFE010C) // (PDC_ADC) Transmit Counter Register
2494 #define AT91C_ADC_RCR (0xFFFE0104) // (PDC_ADC) Receive Counter Register
2495 // ========== Register definition for ADC peripheral ==========
2496 #define AT91C_ADC_CDR6 (0xFFFE0048) // (ADC) ADC Channel Data Register 6
2497 #define AT91C_ADC_CDR4 (0xFFFE0040) // (ADC) ADC Channel Data Register 4
2498 #define AT91C_ADC_CHER (0xFFFE0010) // (ADC) ADC Channel Enable Register
2499 #define AT91C_ADC_CR (0xFFFE0000) // (ADC) ADC Control Register
2500 #define AT91C_ADC_IER (0xFFFE0024) // (ADC) ADC Interrupt Enable Register
2501 #define AT91C_ADC_SR (0xFFFE001C) // (ADC) ADC Status Register
2502 #define AT91C_ADC_CHDR (0xFFFE0014) // (ADC) ADC Channel Disable Register
2503 #define AT91C_ADC_MR (0xFFFE0004) // (ADC) ADC Mode Register
2504 #define AT91C_ADC_CHSR (0xFFFE0018) // (ADC) ADC Channel Status Register
2505 #define AT91C_ADC_LCDR (0xFFFE0020) // (ADC) ADC Last Converted Data Register
2506 #define AT91C_ADC_IDR (0xFFFE0028) // (ADC) ADC Interrupt Disable Register
2507 #define AT91C_ADC_CDR0 (0xFFFE0030) // (ADC) ADC Channel Data Register 0
2508 #define AT91C_ADC_CDR2 (0xFFFE0038) // (ADC) ADC Channel Data Register 2
2509 #define AT91C_ADC_CDR7 (0xFFFE004C) // (ADC) ADC Channel Data Register 7
2510 #define AT91C_ADC_IMR (0xFFFE002C) // (ADC) ADC Interrupt Mask Register
2511 #define AT91C_ADC_CDR1 (0xFFFE0034) // (ADC) ADC Channel Data Register 1
2512 #define AT91C_ADC_CDR3 (0xFFFE003C) // (ADC) ADC Channel Data Register 3
2513 #define AT91C_ADC_CDR5 (0xFFFE0044) // (ADC) ADC Channel Data Register 5
2514 // ========== Register definition for EMACB peripheral ==========
2515 #define AT91C_EMACB_SA1L (0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes
2516 #define AT91C_EMACB_SA2H (0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes
2517 #define AT91C_EMACB_FRO (0xFFFC404C) // (EMACB) Frames Received OK Register
2518 #define AT91C_EMACB_NCFGR (0xFFFC4004) // (EMACB) Network Configuration Register
2519 #define AT91C_EMACB_TID (0xFFFC40B8) // (EMACB) Type ID Checking Register
2520 #define AT91C_EMACB_SA3L (0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes
2521 #define AT91C_EMACB_ECOL (0xFFFC4060) // (EMACB) Excessive Collision Register
2522 #define AT91C_EMACB_FCSE (0xFFFC4050) // (EMACB) Frame Check Sequence Error Register
2523 #define AT91C_EMACB_NSR (0xFFFC4008) // (EMACB) Network Status Register
2524 #define AT91C_EMACB_RBQP (0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer
2525 #define AT91C_EMACB_TPQ (0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register
2526 #define AT91C_EMACB_SA3H (0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes
2527 #define AT91C_EMACB_RSE (0xFFFC4074) // (EMACB) Receive Symbol Errors Register
2528 #define AT91C_EMACB_TUND (0xFFFC4064) // (EMACB) Transmit Underrun Error Register
2529 #define AT91C_EMACB_TBQP (0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer
2530 #define AT91C_EMACB_IDR (0xFFFC402C) // (EMACB) Interrupt Disable Register
2531 #define AT91C_EMACB_USRIO (0xFFFC40C0) // (EMACB) USER Input/Output Register
2532 #define AT91C_EMACB_RLE (0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register
2533 #define AT91C_EMACB_ELE (0xFFFC4078) // (EMACB) Excessive Length Errors Register
2534 #define AT91C_EMACB_IMR (0xFFFC4030) // (EMACB) Interrupt Mask Register
2535 #define AT91C_EMACB_RSR (0xFFFC4020) // (EMACB) Receive Status Register
2536 #define AT91C_EMACB_SA1H (0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes
2537 #define AT91C_EMACB_TPF (0xFFFC408C) // (EMACB) Transmitted Pause Frames Register
2538 #define AT91C_EMACB_MAN (0xFFFC4034) // (EMACB) PHY Maintenance Register
2539 #define AT91C_EMACB_SA2L (0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes
2540 #define AT91C_EMACB_REV (0xFFFC40FC) // (EMACB) Revision Register
2541 #define AT91C_EMACB_FTO (0xFFFC4040) // (EMACB) Frames Transmitted OK Register
2542 #define AT91C_EMACB_SCF (0xFFFC4044) // (EMACB) Single Collision Frame Register
2543 #define AT91C_EMACB_ALE (0xFFFC4054) // (EMACB) Alignment Error Register
2544 #define AT91C_EMACB_SA4L (0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes
2545 #define AT91C_EMACB_MCF (0xFFFC4048) // (EMACB) Multiple Collision Frame Register
2546 #define AT91C_EMACB_DTF (0xFFFC4058) // (EMACB) Deferred Transmission Frame Register
2547 #define AT91C_EMACB_CSE (0xFFFC4068) // (EMACB) Carrier Sense Error Register
2548 #define AT91C_EMACB_NCR (0xFFFC4000) // (EMACB) Network Control Register
2549 #define AT91C_EMACB_WOL (0xFFFC40C4) // (EMACB) Wake On LAN Register
2550 #define AT91C_EMACB_SA4H (0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes
2551 #define AT91C_EMACB_LCOL (0xFFFC405C) // (EMACB) Late Collision Register
2552 #define AT91C_EMACB_RRE (0xFFFC406C) // (EMACB) Receive Ressource Error Register
2553 #define AT91C_EMACB_RJA (0xFFFC407C) // (EMACB) Receive Jabbers Register
2554 #define AT91C_EMACB_ISR (0xFFFC4024) // (EMACB) Interrupt Status Register
2555 #define AT91C_EMACB_TSR (0xFFFC4014) // (EMACB) Transmit Status Register
2556 #define AT91C_EMACB_HRB (0xFFFC4090) // (EMACB) Hash Address Bottom[31:0]
2557 #define AT91C_EMACB_ROV (0xFFFC4070) // (EMACB) Receive Overrun Errors Register
2558 #define AT91C_EMACB_USF (0xFFFC4080) // (EMACB) Undersize Frames Register
2559 #define AT91C_EMACB_IER (0xFFFC4028) // (EMACB) Interrupt Enable Register
2560 #define AT91C_EMACB_PTR (0xFFFC4038) // (EMACB) Pause Time Register
2561 #define AT91C_EMACB_HRT (0xFFFC4094) // (EMACB) Hash Address Top[63:32]
2562 #define AT91C_EMACB_STE (0xFFFC4084) // (EMACB) SQE Test Error Register
2563 #define AT91C_EMACB_PFR (0xFFFC403C) // (EMACB) Pause Frames received Register
2564 // ========== Register definition for UDP peripheral ==========
2565 #define AT91C_UDP_FDR (0xFFFA4050) // (UDP) Endpoint FIFO Data Register
2566 #define AT91C_UDP_IER (0xFFFA4010) // (UDP) Interrupt Enable Register
2567 #define AT91C_UDP_FADDR (0xFFFA4008) // (UDP) Function Address Register
2568 #define AT91C_UDP_NUM (0xFFFA4000) // (UDP) Frame Number Register
2569 #define AT91C_UDP_TXVC (0xFFFA4074) // (UDP) Transceiver Control Register
2570 #define AT91C_UDP_GLBSTATE (0xFFFA4004) // (UDP) Global State Register
2571 #define AT91C_UDP_IDR (0xFFFA4014) // (UDP) Interrupt Disable Register
2572 #define AT91C_UDP_ISR (0xFFFA401C) // (UDP) Interrupt Status Register
2573 #define AT91C_UDP_CSR (0xFFFA4030) // (UDP) Endpoint Control and Status Register
2574 #define AT91C_UDP_RSTEP (0xFFFA4028) // (UDP) Reset Endpoint Register
2575 #define AT91C_UDP_IMR (0xFFFA4018) // (UDP) Interrupt Mask Register
2576 #define AT91C_UDP_ICR (0xFFFA4020) // (UDP) Interrupt Clear Register
2577 // ========== Register definition for UHP peripheral ==========
2578 #define AT91C_UHP_HcRhPortStatus (0x00500054) // (UHP) Root Hub Port Status Register
2579 #define AT91C_UHP_HcRhDescriptorB (0x0050004C) // (UHP) Root Hub characteristics B
2580 #define AT91C_UHP_HcLSThreshold (0x00500044) // (UHP) LS Threshold
2581 #define AT91C_UHP_HcFmNumber (0x0050003C) // (UHP) Frame number
2582 #define AT91C_UHP_HcFmInterval (0x00500034) // (UHP) Bit time between 2 consecutive SOFs
2583 #define AT91C_UHP_HcBulkCurrentED (0x0050002C) // (UHP) Current endpoint of the Bulk list
2584 #define AT91C_UHP_HcControlCurrentED (0x00500024) // (UHP) Endpoint Control and Status Register
2585 #define AT91C_UHP_HcPeriodCurrentED (0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
2586 #define AT91C_UHP_HcInterruptDisable (0x00500014) // (UHP) Interrupt Disable Register
2587 #define AT91C_UHP_HcInterruptStatus (0x0050000C) // (UHP) Interrupt Status Register
2588 #define AT91C_UHP_HcControl (0x00500004) // (UHP) Operating modes for the Host Controller
2589 #define AT91C_UHP_HcRhStatus (0x00500050) // (UHP) Root Hub Status register
2590 #define AT91C_UHP_HcRhDescriptorA (0x00500048) // (UHP) Root Hub characteristics A
2591 #define AT91C_UHP_HcPeriodicStart (0x00500040) // (UHP) Periodic Start
2592 #define AT91C_UHP_HcFmRemaining (0x00500038) // (UHP) Bit time remaining in the current Frame
2593 #define AT91C_UHP_HcBulkDoneHead (0x00500030) // (UHP) Last completed transfer descriptor
2594 #define AT91C_UHP_HcBulkHeadED (0x00500028) // (UHP) First endpoint register of the Bulk list
2595 #define AT91C_UHP_HcControlHeadED (0x00500020) // (UHP) First Endpoint Descriptor of the Control list
2596 #define AT91C_UHP_HcHCCA (0x00500018) // (UHP) Pointer to the Host Controller Communication Area
2597 #define AT91C_UHP_HcInterruptEnable (0x00500010) // (UHP) Interrupt Enable Register
2598 #define AT91C_UHP_HcCommandStatus (0x00500008) // (UHP) Command & status Register
2599 #define AT91C_UHP_HcRevision (0x00500000) // (UHP) Revision
2600 // ========== Register definition for HECC peripheral ==========
2601 // ========== Register definition for HISI peripheral ==========
2602 #define AT91C_HISI_Y2RSET0 (0xFFFC0030) // (HISI) Color Space Conversion Register
2603 #define AT91C_HISI_PFBD (0xFFFC0028) // (HISI) Preview Frame Buffer Address Register
2604 #define AT91C_HISI_PSIZE (0xFFFC0020) // (HISI) Preview Size Register
2605 #define AT91C_HISI_IDR (0xFFFC0010) // (HISI) Interrupt Disable Register
2606 #define AT91C_HISI_R2YSET1 (0xFFFC003C) // (HISI) Color Space Conversion Register
2607 #define AT91C_HISI_Y2RSET1 (0xFFFC0034) // (HISI) Color Space Conversion Register
2608 #define AT91C_HISI_CDBA (0xFFFC002C) // (HISI) Codec Dma Address Register
2609 #define AT91C_HISI_PDECF (0xFFFC0024) // (HISI) Preview Decimation Factor Register
2610 #define AT91C_HISI_R2YSET2 (0xFFFC0040) // (HISI) Color Space Conversion Register
2611 #define AT91C_HISI_R2YSET0 (0xFFFC0038) // (HISI) Color Space Conversion Register
2612 #define AT91C_HISI_CR1 (0xFFFC0000) // (HISI) Control Register 1
2613 #define AT91C_HISI_SR (0xFFFC0008) // (HISI) Status Register
2614 #define AT91C_HISI_CR2 (0xFFFC0004) // (HISI) Control Register 2
2615 #define AT91C_HISI_IER (0xFFFC000C) // (HISI) Interrupt Enable Register
2616 #define AT91C_HISI_IMR (0xFFFC0014) // (HISI) Interrupt Mask Register
2618 // *****************************************************************************
2619 // PIO DEFINITIONS FOR AT91SAM9260
2620 // *****************************************************************************
2621 #define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
2622 #define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) // SPI 0 Master In Slave
2623 #define AT91C_PA0_MCDB0 (AT91C_PIO_PA0) // Multimedia Card B Data 0
2624 #define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
2625 #define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) // SPI 0 Master Out Slave
2626 #define AT91C_PA1_MCCDB (AT91C_PIO_PA1) // Multimedia Card B Command
2627 #define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
2628 #define AT91C_PA10_MCDA2 (AT91C_PIO_PA10) // Multimedia Card A Data 2
2629 #define AT91C_PA10_ETX2 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 2
2630 #define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
2631 #define AT91C_PA11_MCDA3 (AT91C_PIO_PA11) // Multimedia Card A Data 3
2632 #define AT91C_PA11_ETX3 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 3
2633 #define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
2634 #define AT91C_PA12_ETX0 (AT91C_PIO_PA12) // Ethernet MAC Transmit Data 0
2635 #define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
2636 #define AT91C_PA13_ETX1 (AT91C_PIO_PA13) // Ethernet MAC Transmit Data 1
2637 #define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
2638 #define AT91C_PA14_ERX0 (AT91C_PIO_PA14) // Ethernet MAC Receive Data 0
2639 #define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
2640 #define AT91C_PA15_ERX1 (AT91C_PIO_PA15) // Ethernet MAC Receive Data 1
2641 #define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
2642 #define AT91C_PA16_ETXEN (AT91C_PIO_PA16) // Ethernet MAC Transmit Enable
2643 #define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
2644 #define AT91C_PA17_ERXDV (AT91C_PIO_PA17) // Ethernet MAC Receive Data Valid
2645 #define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
2646 #define AT91C_PA18_ERXER (AT91C_PIO_PA18) // Ethernet MAC Receive Error
2647 #define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
2648 #define AT91C_PA19_ETXCK (AT91C_PIO_PA19) // Ethernet MAC Transmit Clock/Reference Clock
2649 #define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
2650 #define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) // SPI 0 Serial Clock
2651 #define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
2652 #define AT91C_PA20_EMDC (AT91C_PIO_PA20) // Ethernet MAC Management Data Clock
2653 #define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
2654 #define AT91C_PA21_EMDIO (AT91C_PIO_PA21) // Ethernet MAC Management Data Input/Output
2655 #define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
2656 #define AT91C_PA22_ADTRG (AT91C_PIO_PA22) // ADC Trigger
2657 #define AT91C_PA22_ETXER (AT91C_PIO_PA22) // Ethernet MAC Transmikt Coding Error
2658 #define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
2659 #define AT91C_PA23_TWD (AT91C_PIO_PA23) // TWI Two-wire Serial Data
2660 #define AT91C_PA23_ETX2 (AT91C_PIO_PA23) // Ethernet MAC Transmit Data 2
2661 #define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
2662 #define AT91C_PA24_TWCK (AT91C_PIO_PA24) // TWI Two-wire Serial Clock
2663 #define AT91C_PA24_ETX3 (AT91C_PIO_PA24) // Ethernet MAC Transmit Data 3
2664 #define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
2665 #define AT91C_PA25_TCLK0 (AT91C_PIO_PA25) // Timer Counter 0 external clock input
2666 #define AT91C_PA25_ERX2 (AT91C_PIO_PA25) // Ethernet MAC Receive Data 2
2667 #define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
2668 #define AT91C_PA26_TIOA0 (AT91C_PIO_PA26) // Timer Counter 0 Multipurpose Timer I/O Pin A
2669 #define AT91C_PA26_ERX3 (AT91C_PIO_PA26) // Ethernet MAC Receive Data 3
2670 #define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
2671 #define AT91C_PA27_TIOA1 (AT91C_PIO_PA27) // Timer Counter 1 Multipurpose Timer I/O Pin A
2672 #define AT91C_PA27_ERXCK (AT91C_PIO_PA27) // Ethernet MAC Receive Clock
2673 #define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
2674 #define AT91C_PA28_TIOA2 (AT91C_PIO_PA28) // Timer Counter 2 Multipurpose Timer I/O Pin A
2675 #define AT91C_PA28_ECRS (AT91C_PIO_PA28) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
2676 #define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
2677 #define AT91C_PA29_SCK1 (AT91C_PIO_PA29) // USART 1 Serial Clock
2678 #define AT91C_PA29_ECOL (AT91C_PIO_PA29) // Ethernet MAC Collision Detected
2679 #define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
2680 #define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) // SPI 0 Peripheral Chip Select 0
2681 #define AT91C_PA3_MCDB3 (AT91C_PIO_PA3) // Multimedia Card B Data 3
2682 #define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
2683 #define AT91C_PA30_SCK2 (AT91C_PIO_PA30) // USART 2 Serial Clock
2684 #define AT91C_PA30_RXD4 (AT91C_PIO_PA30) // USART 4 Receive Data
2685 #define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
2686 #define AT91C_PA31_SCK0 (AT91C_PIO_PA31) // USART 0 Serial Clock
2687 #define AT91C_PA31_TXD4 (AT91C_PIO_PA31) // USART 4 Transmit Data
2688 #define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
2689 #define AT91C_PA4_RTS2 (AT91C_PIO_PA4) // USART 2 Ready To Send
2690 #define AT91C_PA4_MCDB2 (AT91C_PIO_PA4) // Multimedia Card B Data 2
2691 #define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
2692 #define AT91C_PA5_CTS2 (AT91C_PIO_PA5) // USART 2 Clear To Send
2693 #define AT91C_PA5_MCDB1 (AT91C_PIO_PA5) // Multimedia Card B Data 1
2694 #define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
2695 #define AT91C_PA6_MCDA0 (AT91C_PIO_PA6) // Multimedia Card A Data 0
2696 #define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
2697 #define AT91C_PA7_MCCDA (AT91C_PIO_PA7) // Multimedia Card A Command
2698 #define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
2699 #define AT91C_PA8_MCCK (AT91C_PIO_PA8) // Multimedia Card Clock
2700 #define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
2701 #define AT91C_PA9_MCDA1 (AT91C_PIO_PA9) // Multimedia Card A Data 1
2702 #define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
2703 #define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) // SPI 1 Master In Slave
2704 #define AT91C_PB0_TIOA3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin A
2705 #define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
2706 #define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) // SPI 1 Master Out Slave
2707 #define AT91C_PB1_TIOB3 (AT91C_PIO_PB1) // Timer Counter 3 Multipurpose Timer I/O Pin B
2708 #define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
2709 #define AT91C_PB10_TXD3 (AT91C_PIO_PB10) // USART 3 Transmit Data
2710 #define AT91C_PB10_ISI_D8 (AT91C_PIO_PB10) // Image Sensor Data 8
2711 #define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
2712 #define AT91C_PB11_RXD3 (AT91C_PIO_PB11) // USART 3 Receive Data
2713 #define AT91C_PB11_ISI_D9 (AT91C_PIO_PB11) // Image Sensor Data 9
2714 #define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
2715 #define AT91C_PB12_TXD5 (AT91C_PIO_PB12) // USART 5 Transmit Data
2716 #define AT91C_PB12_ISI_D10 (AT91C_PIO_PB12) // Image Sensor Data 10
2717 #define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
2718 #define AT91C_PB13_RXD5 (AT91C_PIO_PB13) // USART 5 Receive Data
2719 #define AT91C_PB13_ISI_D11 (AT91C_PIO_PB13) // Image Sensor Data 11
2720 #define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
2721 #define AT91C_PB14_DRXD (AT91C_PIO_PB14) // DBGU Debug Receive Data
2722 #define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
2723 #define AT91C_PB15_DTXD (AT91C_PIO_PB15) // DBGU Debug Transmit Data
2724 #define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
2725 #define AT91C_PB16_TK0 (AT91C_PIO_PB16) // SSC0 Transmit Clock
2726 #define AT91C_PB16_TCLK3 (AT91C_PIO_PB16) // Timer Counter 3 external clock input
2727 #define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
2728 #define AT91C_PB17_TF0 (AT91C_PIO_PB17) // SSC0 Transmit Frame Sync
2729 #define AT91C_PB17_TCLK4 (AT91C_PIO_PB17) // Timer Counter 4 external clock input
2730 #define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
2731 #define AT91C_PB18_TD0 (AT91C_PIO_PB18) // SSC0 Transmit data
2732 #define AT91C_PB18_TIOB4 (AT91C_PIO_PB18) // Timer Counter 4 Multipurpose Timer I/O Pin B
2733 #define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
2734 #define AT91C_PB19_RD0 (AT91C_PIO_PB19) // SSC0 Receive Data
2735 #define AT91C_PB19_TIOB5 (AT91C_PIO_PB19) // Timer Counter 5 Multipurpose Timer I/O Pin B
2736 #define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
2737 #define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) // SPI 1 Serial Clock
2738 #define AT91C_PB2_TIOA4 (AT91C_PIO_PB2) // Timer Counter 4 Multipurpose Timer I/O Pin A
2739 #define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
2740 #define AT91C_PB20_RK0 (AT91C_PIO_PB20) // SSC0 Receive Clock
2741 #define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // Image Sensor Data 0
2742 #define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
2743 #define AT91C_PB21_RF0 (AT91C_PIO_PB21) // SSC0 Receive Frame Sync
2744 #define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // Image Sensor Data 1
2745 #define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
2746 #define AT91C_PB22_DSR0 (AT91C_PIO_PB22) // USART 0 Data Set ready
2747 #define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // Image Sensor Data 2
2748 #define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
2749 #define AT91C_PB23_DCD0 (AT91C_PIO_PB23) // USART 0 Data Carrier Detect
2750 #define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // Image Sensor Data 3
2751 #define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
2752 #define AT91C_PB24_DTR0 (AT91C_PIO_PB24) // USART 0 Data Terminal ready
2753 #define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // Image Sensor Data 4
2754 #define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
2755 #define AT91C_PB25_RI0 (AT91C_PIO_PB25) // USART 0 Ring Indicator
2756 #define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // Image Sensor Data 5
2757 #define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
2758 #define AT91C_PB26_RTS0 (AT91C_PIO_PB26) // USART 0 Ready To Send
2759 #define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // Image Sensor Data 6
2760 #define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
2761 #define AT91C_PB27_CTS0 (AT91C_PIO_PB27) // USART 0 Clear To Send
2762 #define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // Image Sensor Data 7
2763 #define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
2764 #define AT91C_PB28_RTS1 (AT91C_PIO_PB28) // USART 1 Ready To Send
2765 #define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // Image Sensor Data Clock
2766 #define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
2767 #define AT91C_PB29_CTS1 (AT91C_PIO_PB29) // USART 1 Clear To Send
2768 #define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // Image Sensor Vertical Synchro
2769 #define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
2770 #define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) // SPI 1 Peripheral Chip Select 0
2771 #define AT91C_PB3_TIOA5 (AT91C_PIO_PB3) // Timer Counter 5 Multipurpose Timer I/O Pin A
2772 #define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
2773 #define AT91C_PB30_PCK0_0 (AT91C_PIO_PB30) // PMC Programmable Clock Output 0
2774 #define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // Image Sensor Horizontal Synchro
2775 #define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31
2776 #define AT91C_PB31_PCK1_0 (AT91C_PIO_PB31) // PMC Programmable Clock Output 1
2777 #define AT91C_PB31_ISI_MCK (AT91C_PIO_PB31) // Image Sensor Reference Clock
2778 #define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
2779 #define AT91C_PB4_TXD0 (AT91C_PIO_PB4) // USART 0 Transmit Data
2780 #define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
2781 #define AT91C_PB5_RXD0 (AT91C_PIO_PB5) // USART 0 Receive Data
2782 #define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
2783 #define AT91C_PB6_TXD1 (AT91C_PIO_PB6) // USART 1 Transmit Data
2784 #define AT91C_PB6_TCLK1 (AT91C_PIO_PB6) // Timer Counter 1 external clock input
2785 #define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
2786 #define AT91C_PB7_RXD1 (AT91C_PIO_PB7) // USART 1 Receive Data
2787 #define AT91C_PB7_TCLK2 (AT91C_PIO_PB7) // Timer Counter 2 external clock input
2788 #define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
2789 #define AT91C_PB8_TXD2 (AT91C_PIO_PB8) // USART 2 Transmit Data
2790 #define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
2791 #define AT91C_PB9_RXD2 (AT91C_PIO_PB9) // USART 2 Receive Data
2792 #define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0
2793 #define AT91C_PC0_AD0 (AT91C_PIO_PC0) // ADC Analog Input 0
2794 #define AT91C_PC0_SCK3 (AT91C_PIO_PC0) // USART 3 Serial Clock
2795 #define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1
2796 #define AT91C_PC1_AD1 (AT91C_PIO_PC1) // ADC Analog Input 1
2797 #define AT91C_PC1_PCK0 (AT91C_PIO_PC1) // PMC Programmable Clock Output 0
2798 #define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10
2799 #define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) // Address Bus[25]
2800 #define AT91C_PC10_CTS3 (AT91C_PIO_PC10) // USART 3 Clear To Send
2801 #define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11
2802 #define AT91C_PC11_NCS2 (AT91C_PIO_PC11) // Chip Select Line 2
2803 #define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) // SPI 0 Peripheral Chip Select 1
2804 #define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12
2805 #define AT91C_PC12_IRQ0 (AT91C_PIO_PC12) // External Interrupt 0
2806 #define AT91C_PC12_NCS7 (AT91C_PIO_PC12) // Chip Select Line 7
2807 #define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13
2808 #define AT91C_PC13_FIQ (AT91C_PIO_PC13) // AIC Fast Interrupt Input
2809 #define AT91C_PC13_NCS6 (AT91C_PIO_PC13) // Chip Select Line 6
2810 #define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14
2811 #define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // Chip Select Line 3
2812 #define AT91C_PC14_IRQ2 (AT91C_PIO_PC14) // External Interrupt 2
2813 #define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15
2814 #define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // External Wait Signal
2815 #define AT91C_PC15_IRQ1 (AT91C_PIO_PC15) // External Interrupt 1
2816 #define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16
2817 #define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus[16]
2818 #define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) // SPI 0 Peripheral Chip Select 2
2819 #define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17
2820 #define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus[17]
2821 #define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) // SPI 0 Peripheral Chip Select 3
2822 #define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18
2823 #define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus[18]
2824 #define AT91C_PC18_SPI1_NPCS1 (AT91C_PIO_PC18) // SPI 1 Peripheral Chip Select 1
2825 #define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19
2826 #define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus[19]
2827 #define AT91C_PC19_SPI1_NPCS2 (AT91C_PIO_PC19) // SPI 1 Peripheral Chip Select 2
2828 #define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2
2829 #define AT91C_PC2_AD2 (AT91C_PIO_PC2) // ADC Analog Input 2
2830 #define AT91C_PC2_PCK1 (AT91C_PIO_PC2) // PMC Programmable Clock Output 1
2831 #define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20
2832 #define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus[20]
2833 #define AT91C_PC20_SPI1_NPCS3 (AT91C_PIO_PC20) // SPI 1 Peripheral Chip Select 3
2834 #define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21
2835 #define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus[21]
2836 #define AT91C_PC21_EF100 (AT91C_PIO_PC21) // Ethernet MAC Force 100 Mbits/sec
2837 #define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22
2838 #define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus[22]
2839 #define AT91C_PC22_TCLK5 (AT91C_PIO_PC22) // Timer Counter 5 external clock input
2840 #define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23
2841 #define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus[23]
2842 #define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24
2843 #define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus[24]
2844 #define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25
2845 #define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus[25]
2846 #define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26
2847 #define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus[26]
2848 #define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27
2849 #define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus[27]
2850 #define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28
2851 #define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus[28]
2852 #define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29
2853 #define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus[29]
2854 #define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3
2855 #define AT91C_PC3_AD3 (AT91C_PIO_PC3) // ADC Analog Input 3
2856 #define AT91C_PC3_SPI1_NPCS3 (AT91C_PIO_PC3) // SPI 1 Peripheral Chip Select 3
2857 #define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30
2858 #define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus[30]
2859 #define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31
2860 #define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus[31]
2861 #define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4
2862 #define AT91C_PC4_A23 (AT91C_PIO_PC4) // Address Bus[23]
2863 #define AT91C_PC4_SPI1_NPCS2 (AT91C_PIO_PC4) // SPI 1 Peripheral Chip Select 2
2864 #define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5
2865 #define AT91C_PC5_A24 (AT91C_PIO_PC5) // Address Bus[24]
2866 #define AT91C_PC5_SPI1_NPCS1 (AT91C_PIO_PC5) // SPI 1 Peripheral Chip Select 1
2867 #define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6
2868 #define AT91C_PC6_TIOB2 (AT91C_PIO_PC6) // Timer Counter 2 Multipurpose Timer I/O Pin B
2869 #define AT91C_PC6_CFCE1 (AT91C_PIO_PC6) // Compact Flash Enable 1
2870 #define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7
2871 #define AT91C_PC7_TIOB1 (AT91C_PIO_PC7) // Timer Counter 1 Multipurpose Timer I/O Pin B
2872 #define AT91C_PC7_CFCE2 (AT91C_PIO_PC7) // Compact Flash Enable 2
2873 #define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8
2874 #define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) // Chip Select Line 4
2875 #define AT91C_PC8_RTS3 (AT91C_PIO_PC8) // USART 3 Ready To Send
2876 #define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9
2877 #define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) // Chip Select Line 5
2878 #define AT91C_PC9_TIOB0 (AT91C_PIO_PC9) // Timer Counter 0 Multipurpose Timer I/O Pin B
2880 // *****************************************************************************
2881 // PERIPHERAL ID DEFINITIONS FOR AT91SAM9260
2882 // *****************************************************************************
2883 #define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
2884 #define AT91C_ID_SYS ( 1) // System Controller
2885 #define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
2886 #define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
2887 #define AT91C_ID_PIOC ( 4) // Parallel IO Controller C
2888 #define AT91C_ID_ADC ( 5) // ADC
2889 #define AT91C_ID_US0 ( 6) // USART 0
2890 #define AT91C_ID_US1 ( 7) // USART 1
2891 #define AT91C_ID_US2 ( 8) // USART 2
2892 #define AT91C_ID_MCI ( 9) // Multimedia Card Interface 0
2893 #define AT91C_ID_UDP (10) // USB Device Port
2894 #define AT91C_ID_TWI (11) // Two-Wire Interface
2895 #define AT91C_ID_SPI0 (12) // Serial Peripheral Interface 0
2896 #define AT91C_ID_SPI1 (13) // Serial Peripheral Interface 1
2897 #define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0
2898 #define AT91C_ID_TC0 (17) // Timer Counter 0
2899 #define AT91C_ID_TC1 (18) // Timer Counter 1
2900 #define AT91C_ID_TC2 (19) // Timer Counter 2
2901 #define AT91C_ID_UHP (20) // USB Host Port
2902 #define AT91C_ID_EMAC (21) // Ethernet Mac
2903 #define AT91C_ID_HISI (22) // Image Sensor Interface
2904 #define AT91C_ID_US3 (23) // USART 3
2905 #define AT91C_ID_US4 (24) // USART 4
2906 #define AT91C_ID_US5 (25) // USART 5
2907 #define AT91C_ID_TC3 (26) // Timer Counter 3
2908 #define AT91C_ID_TC4 (27) // Timer Counter 4
2909 #define AT91C_ID_TC5 (28) // Timer Counter 5
2910 #define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0)
2911 #define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1)
2912 #define AT91C_ID_IRQ2 (31) // Advanced Interrupt Controller (IRQ2)
2913 #define AT91C_ALL_INT (0xFFFE7FFF) // ALL VALID INTERRUPTS
2915 // *****************************************************************************
2916 // BASE ADDRESS DEFINITIONS FOR AT91SAM9260
2917 // *****************************************************************************
2918 #define AT91C_BASE_SYS (0xFFFFFD00) // (SYS) Base Address
2919 #define AT91C_BASE_EBI (0xFFFFEA00) // (EBI) Base Address
2920 #define AT91C_BASE_HECC (0xFFFFE800) // (HECC) Base Address
2921 #define AT91C_BASE_SDRAMC (0xFFFFEA00) // (SDRAMC) Base Address
2922 #define AT91C_BASE_SMC (0xFFFFEC00) // (SMC) Base Address
2923 #define AT91C_BASE_MATRIX (0xFFFFEE00) // (MATRIX) Base Address
2924 #define AT91C_BASE_CCFG (0xFFFFEF10) // (CCFG) Base Address
2925 #define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address
2926 #define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address
2927 #define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address
2928 #define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address
2929 #define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address
2930 #define AT91C_BASE_PIOC (0xFFFFF800) // (PIOC) Base Address
2931 #define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address
2932 #define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address
2933 #define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address
2934 #define AT91C_BASE_SHDWC (0xFFFFFD10) // (SHDWC) Base Address
2935 #define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address
2936 #define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address
2937 #define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address
2938 #define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address
2939 #define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address
2940 #define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address
2941 #define AT91C_BASE_TC3 (0xFFFDC000) // (TC3) Base Address
2942 #define AT91C_BASE_TC4 (0xFFFDC040) // (TC4) Base Address
2943 #define AT91C_BASE_TC5 (0xFFFDC080) // (TC5) Base Address
2944 #define AT91C_BASE_TCB0 (0xFFFA0000) // (TCB0) Base Address
2945 #define AT91C_BASE_TCB1 (0xFFFDC000) // (TCB1) Base Address
2946 #define AT91C_BASE_PDC_MCI (0xFFFA8100) // (PDC_MCI) Base Address
2947 #define AT91C_BASE_MCI (0xFFFA8000) // (MCI) Base Address
2948 #define AT91C_BASE_PDC_TWI (0xFFFAC100) // (PDC_TWI) Base Address
2949 #define AT91C_BASE_TWI (0xFFFAC000) // (TWI) Base Address
2950 #define AT91C_BASE_PDC_US0 (0xFFFB0100) // (PDC_US0) Base Address
2951 #define AT91C_BASE_US0 (0xFFFB0000) // (US0) Base Address
2952 #define AT91C_BASE_PDC_US1 (0xFFFB4100) // (PDC_US1) Base Address
2953 #define AT91C_BASE_US1 (0xFFFB4000) // (US1) Base Address
2954 #define AT91C_BASE_PDC_US2 (0xFFFB8100) // (PDC_US2) Base Address
2955 #define AT91C_BASE_US2 (0xFFFB8000) // (US2) Base Address
2956 #define AT91C_BASE_PDC_US3 (0xFFFD0100) // (PDC_US3) Base Address
2957 #define AT91C_BASE_US3 (0xFFFD0000) // (US3) Base Address
2958 #define AT91C_BASE_PDC_US4 (0xFFFD4100) // (PDC_US4) Base Address
2959 #define AT91C_BASE_US4 (0xFFFD4000) // (US4) Base Address
2960 #define AT91C_BASE_PDC_US5 (0xFFFD8100) // (PDC_US5) Base Address
2961 #define AT91C_BASE_US5 (0xFFFD8000) // (US5) Base Address
2962 #define AT91C_BASE_PDC_SSC0 (0xFFFBC100) // (PDC_SSC0) Base Address
2963 #define AT91C_BASE_SSC0 (0xFFFBC000) // (SSC0) Base Address
2964 #define AT91C_BASE_PDC_SPI0 (0xFFFC8100) // (PDC_SPI0) Base Address
2965 #define AT91C_BASE_SPI0 (0xFFFC8000) // (SPI0) Base Address
2966 #define AT91C_BASE_PDC_SPI1 (0xFFFCC100) // (PDC_SPI1) Base Address
2967 #define AT91C_BASE_SPI1 (0xFFFCC000) // (SPI1) Base Address
2968 #define AT91C_BASE_PDC_ADC (0xFFFE0100) // (PDC_ADC) Base Address
2969 #define AT91C_BASE_ADC (0xFFFE0000) // (ADC) Base Address
2970 #define AT91C_BASE_EMACB (0xFFFC4000) // (EMACB) Base Address
2971 #define AT91C_BASE_UDP (0xFFFA4000) // (UDP) Base Address
2972 #define AT91C_BASE_UHP (0x00500000) // (UHP) Base Address
2973 #define AT91C_BASE_HISI (0xFFFC0000) // (HISI) Base Address
2975 // *****************************************************************************
2976 // MEMORY MAPPING DEFINITIONS FOR AT91SAM9260
2977 // *****************************************************************************
2979 #define AT91C_IROM (0x00100000) // Internal ROM base address
2980 #define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes)
2982 #define AT91C_IRAM_1 (0x00200000) // Maximum IRAM_1 Area : 4Kbyte base address
2983 #define AT91C_IRAM_1_SIZE (0x00001000) // Maximum IRAM_1 Area : 4Kbyte size in byte (4 Kbytes)
2985 #define AT91C_IRAM_2 (0x00300000) // Maximum IRAM_2 AREA : 4 Kbyte base address
2986 #define AT91C_IRAM_2_SIZE (0x00001000) // Maximum IRAM_2 AREA : 4 Kbyte size in byte (4 Kbytes)
2988 #define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address
2989 #define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
2991 #define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address
2992 #define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
2994 #define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address
2995 #define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)
2997 #define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address
2998 #define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)
3000 #define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address
3001 #define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)
3003 #define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address
3004 #define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
3006 #define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address
3007 #define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
3009 #define AT91C_EBI_SM (0x40000000) // SmartMedia on Chip Select 3 base address
3010 #define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)
3012 #define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address
3013 #define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
3015 #define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on Chip Select 4 base address
3016 #define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)
3018 #define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address
3019 #define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
3021 #define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on Chip Select 5 base address
3022 #define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)
3024 #define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address
3025 #define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)
3027 #define AT91C_EBI_CS7 (0x80000000) // EBI Chip Select 7 base address
3028 #define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)
3030 #define AT91C_NR_PIO (32 * 3)
3032 #endif /* AT91SAM9260_INC_H */
