1 // ----------------------------------------------------------------------------
2 // ATMEL Microcontroller Software Support - ROUSSET -
3 // ----------------------------------------------------------------------------
4 // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
5 // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
7 // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
8 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
9 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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11 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
12 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
13 // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
14 // ----------------------------------------------------------------------------
15 // File Name : AT91CAP9.h
16 // Object : AT91CAP9 definitions
17 // Generated : AT91 SW Application Group 04/18/2006 (16:56:20)
19 // CVS Reference : /AT91CAP9.pl/1.1/Tue Aug 16 16:50:18 2005//
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57 // ----------------------------------------------------------------------------
59 #ifndef _AT91CAP9_INC_H_
60 #define _AT91CAP9_INC_H_
62 // Hardware register definition
64 // *****************************************************************************
65 // SOFTWARE API DEFINITION FOR Error Correction Code controller
66 // *****************************************************************************
67 // *** Register offset in AT91S_ECC structure ***
68 #define ECC_CR ( 0) // ECC reset register
69 #define ECC_MR ( 4) // ECC Page size register
70 #define ECC_SR ( 8) // ECC Status register
71 #define ECC_PR (12) // ECC Parity register
72 #define ECC_NPR (16) // ECC Parity N register
73 #define ECC_VR (252) // ECC Version register
74 // -------- ECC_CR : (ECC Offset: 0x0) ECC reset register --------
75 #define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity
76 // -------- ECC_MR : (ECC Offset: 0x4) ECC page size register --------
77 #define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size
78 // -------- ECC_SR : (ECC Offset: 0x8) ECC status register --------
79 #define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error
80 #define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error
81 #define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR
82 // -------- ECC_PR : (ECC Offset: 0xc) ECC parity register --------
83 #define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error
84 #define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit
85 // -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register --------
86 #define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N
87 // -------- ECC_VR : (ECC Offset: 0xfc) ECC version register --------
88 #define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register
90 // *****************************************************************************
91 // SOFTWARE API DEFINITION FOR Busr Cellular RAM Controller Interface
92 // *****************************************************************************
93 // *** Register offset in AT91S_BCRAMC structure ***
94 #define BCRAMC_CR ( 0) // BCRAM Controller Configuration Register
95 #define BCRAMC_TPR ( 4) // BCRAM Controller Timing Parameter Register
96 #define BCRAMC_HSR ( 8) // BCRAM Controller High Speed Register
97 #define BCRAMC_LPR (12) // BCRAM Controller Low Power Register
98 #define BCRAMC_MDR (16) // BCRAM Memory Device Register
99 #define BCRAMC_PADDSR (236) // BCRAM PADDR Size Register
100 #define BCRAMC_IPNR1 (240) // BCRAM IP Name Register 1
101 #define BCRAMC_IPNR2 (244) // BCRAM IP Name Register 2
102 #define BCRAMC_IPFR (248) // BCRAM IP Features Register
103 #define BCRAMC_VR (252) // BCRAM Version Register
104 // -------- BCRAMC_CR : (BCRAMC Offset: 0x0) BCRAM Controller Configuration Register --------
105 #define AT91C_BCRAMC_EN (0x1 << 0) // (BCRAMC) Enable
106 #define AT91C_BCRAMC_CAS (0x7 << 4) // (BCRAMC) CAS Latency
107 #define AT91C_BCRAMC_CAS_2 (0x2 << 4) // (BCRAMC) 2 cycles Latency for Cellular RAM v1.0/1.5/2.0
108 #define AT91C_BCRAMC_CAS_3 (0x3 << 4) // (BCRAMC) 3 cycles Latency for Cellular RAM v1.0/1.5/2.0
109 #define AT91C_BCRAMC_CAS_4 (0x4 << 4) // (BCRAMC) 4 cycles Latency for Cellular RAM v1.5/2.0
110 #define AT91C_BCRAMC_CAS_5 (0x5 << 4) // (BCRAMC) 5 cycles Latency for Cellular RAM v1.5/2.0
111 #define AT91C_BCRAMC_CAS_6 (0x6 << 4) // (BCRAMC) 6 cycles Latency for Cellular RAM v1.5/2.0
112 #define AT91C_BCRAMC_DBW (0x1 << 8) // (BCRAMC) Data Bus Width
113 #define AT91C_BCRAMC_DBW_32_BITS (0x0 << 8) // (BCRAMC) 32 Bits datas bus
114 #define AT91C_BCRAMC_DBW_16_BITS (0x1 << 8) // (BCRAMC) 16 Bits datas bus
115 #define AT91C_BCRAM_NWIR (0x3 << 12) // (BCRAMC) Number Of Words in Row
116 #define AT91C_BCRAM_NWIR_64 (0x0 << 12) // (BCRAMC) 64 Words in Row
117 #define AT91C_BCRAM_NWIR_128 (0x1 << 12) // (BCRAMC) 128 Words in Row
118 #define AT91C_BCRAM_NWIR_256 (0x2 << 12) // (BCRAMC) 256 Words in Row
119 #define AT91C_BCRAM_NWIR_512 (0x3 << 12) // (BCRAMC) 512 Words in Row
120 #define AT91C_BCRAM_ADMX (0x1 << 16) // (BCRAMC) ADDR / DATA Mux
121 #define AT91C_BCRAM_ADMX_NO_MUX (0x0 << 16) // (BCRAMC) No ADD/DATA Mux for Cellular RAM v1.0/1.5/2.0
122 #define AT91C_BCRAM_ADMX_MUX (0x1 << 16) // (BCRAMC) ADD/DATA Mux Only for Cellular RAM v2.0
123 #define AT91C_BCRAM_DS (0x3 << 20) // (BCRAMC) Drive Strength
124 #define AT91C_BCRAM_DS_FULL_DRIVE (0x0 << 20) // (BCRAMC) Full Cellular RAM Drive
125 #define AT91C_BCRAM_DS_HALF_DRIVE (0x1 << 20) // (BCRAMC) Half Cellular RAM Drive
126 #define AT91C_BCRAM_DS_QUARTER_DRIVE (0x2 << 20) // (BCRAMC) Quarter Cellular RAM Drive
127 #define AT91C_BCRAM_VFLAT (0x1 << 24) // (BCRAMC) Variable or Fixed Latency
128 #define AT91C_BCRAM_VFLAT_VARIABLE (0x0 << 24) // (BCRAMC) Variable Latency
129 #define AT91C_BCRAM_VFLAT_FIXED (0x1 << 24) // (BCRAMC) Fixed Latency
130 // -------- BCRAMC_TPR : (BCRAMC Offset: 0x4) BCRAMC Timing Parameter Register --------
131 #define AT91C_BCRAMC_TCW (0xF << 0) // (BCRAMC) Chip Enable to End of Write
132 #define AT91C_BCRAMC_TCW_0 (0x0) // (BCRAMC) Value : 0
133 #define AT91C_BCRAMC_TCW_1 (0x1) // (BCRAMC) Value : 1
134 #define AT91C_BCRAMC_TCW_2 (0x2) // (BCRAMC) Value : 2
135 #define AT91C_BCRAMC_TCW_3 (0x3) // (BCRAMC) Value : 3
136 #define AT91C_BCRAMC_TCW_4 (0x4) // (BCRAMC) Value : 4
137 #define AT91C_BCRAMC_TCW_5 (0x5) // (BCRAMC) Value : 5
138 #define AT91C_BCRAMC_TCW_6 (0x6) // (BCRAMC) Value : 6
139 #define AT91C_BCRAMC_TCW_7 (0x7) // (BCRAMC) Value : 7
140 #define AT91C_BCRAMC_TCW_8 (0x8) // (BCRAMC) Value : 8
141 #define AT91C_BCRAMC_TCW_9 (0x9) // (BCRAMC) Value : 9
142 #define AT91C_BCRAMC_TCW_10 (0xA) // (BCRAMC) Value : 10
143 #define AT91C_BCRAMC_TCW_11 (0xB) // (BCRAMC) Value : 11
144 #define AT91C_BCRAMC_TCW_12 (0xC) // (BCRAMC) Value : 12
145 #define AT91C_BCRAMC_TCW_13 (0xD) // (BCRAMC) Value : 13
146 #define AT91C_BCRAMC_TCW_14 (0xE) // (BCRAMC) Value : 14
147 #define AT91C_BCRAMC_TCW_15 (0xF) // (BCRAMC) Value : 15
148 #define AT91C_BCRAMC_TCRES (0x3 << 4) // (BCRAMC) CRE Setup
149 #define AT91C_BCRAMC_TCRES_0 (0x0 << 4) // (BCRAMC) Value : 0
150 #define AT91C_BCRAMC_TCRES_1 (0x1 << 4) // (BCRAMC) Value : 1
151 #define AT91C_BCRAMC_TCRES_2 (0x2 << 4) // (BCRAMC) Value : 2
152 #define AT91C_BCRAMC_TCRES_3 (0x3 << 4) // (BCRAMC) Value : 3
153 #define AT91C_BCRAMC_TCKA (0xF << 8) // (BCRAMC) WE High to CLK Valid
154 #define AT91C_BCRAMC_TCKA_0 (0x0 << 8) // (BCRAMC) Value : 0
155 #define AT91C_BCRAMC_TCKA_1 (0x1 << 8) // (BCRAMC) Value : 1
156 #define AT91C_BCRAMC_TCKA_2 (0x2 << 8) // (BCRAMC) Value : 2
157 #define AT91C_BCRAMC_TCKA_3 (0x3 << 8) // (BCRAMC) Value : 3
158 #define AT91C_BCRAMC_TCKA_4 (0x4 << 8) // (BCRAMC) Value : 4
159 #define AT91C_BCRAMC_TCKA_5 (0x5 << 8) // (BCRAMC) Value : 5
160 #define AT91C_BCRAMC_TCKA_6 (0x6 << 8) // (BCRAMC) Value : 6
161 #define AT91C_BCRAMC_TCKA_7 (0x7 << 8) // (BCRAMC) Value : 7
162 #define AT91C_BCRAMC_TCKA_8 (0x8 << 8) // (BCRAMC) Value : 8
163 #define AT91C_BCRAMC_TCKA_9 (0x9 << 8) // (BCRAMC) Value : 9
164 #define AT91C_BCRAMC_TCKA_10 (0xA << 8) // (BCRAMC) Value : 10
165 #define AT91C_BCRAMC_TCKA_11 (0xB << 8) // (BCRAMC) Value : 11
166 #define AT91C_BCRAMC_TCKA_12 (0xC << 8) // (BCRAMC) Value : 12
167 #define AT91C_BCRAMC_TCKA_13 (0xD << 8) // (BCRAMC) Value : 13
168 #define AT91C_BCRAMC_TCKA_14 (0xE << 8) // (BCRAMC) Value : 14
169 #define AT91C_BCRAMC_TCKA_15 (0xF << 8) // (BCRAMC) Value : 15
170 // -------- BCRAMC_HSR : (BCRAMC Offset: 0x8) BCRAM Controller High Speed Register --------
171 #define AT91C_BCRAMC_DA (0x1 << 0) // (BCRAMC) Decode Cycle Enable Bit
172 #define AT91C_BCRAMC_DA_DISABLE (0x0) // (BCRAMC) Disable Decode Cycle
173 #define AT91C_BCRAMC_DA_ENABLE (0x1) // (BCRAMC) Enable Decode Cycle
174 // -------- BCRAMC_LPR : (BCRAMC Offset: 0xc) BCRAM Controller Low-power Register --------
175 #define AT91C_BCRAMC_PAR (0x7 << 0) // (BCRAMC) Partial Array Refresh
176 #define AT91C_BCRAMC_PAR_FULL (0x0) // (BCRAMC) Full Refresh
177 #define AT91C_BCRAMC_PAR_PARTIAL_BOTTOM_HALF (0x1) // (BCRAMC) Partial Bottom Half Refresh
178 #define AT91C_BCRAMC_PAR_PARTIAL_BOTTOM_QUARTER (0x2) // (BCRAMC) Partial Bottom Quarter Refresh
179 #define AT91C_BCRAMC_PAR_PARTIAL_BOTTOM_EIGTH (0x3) // (BCRAMC) Partial Bottom eigth Refresh
180 #define AT91C_BCRAMC_PAR_NONE (0x4) // (BCRAMC) Not Refreshed
181 #define AT91C_BCRAMC_PAR_PARTIAL_TOP_HALF (0x5) // (BCRAMC) Partial Top Half Refresh
182 #define AT91C_BCRAMC_PAR_PARTIAL_TOP_QUARTER (0x6) // (BCRAMC) Partial Top Quarter Refresh
183 #define AT91C_BCRAMC_PAR_PARTIAL_TOP_EIGTH (0x7) // (BCRAMC) Partial Top eigth Refresh
184 #define AT91C_BCRAMC_TCR (0x3 << 4) // (BCRAMC) Temperature Compensated Self Refresh
185 #define AT91C_BCRAMC_TCR_85C (0x0 << 4) // (BCRAMC) +85C Temperature
186 #define AT91C_BCRAMC_TCR_INTERNAL_OR_70C (0x1 << 4) // (BCRAMC) Internal Sensor or +70C Temperature
187 #define AT91C_BCRAMC_TCR_45C (0x2 << 4) // (BCRAMC) +45C Temperature
188 #define AT91C_BCRAMC_TCR_15C (0x3 << 4) // (BCRAMC) +15C Temperature
189 #define AT91C_BCRAMC_LPCB (0x3 << 8) // (BCRAMC) Low-power Command Bit
190 #define AT91C_BCRAMC_LPCB_DISABLE (0x0 << 8) // (BCRAMC) Disable Low Power Features
191 #define AT91C_BCRAMC_LPCB_STANDBY (0x1 << 8) // (BCRAMC) Enable Cellular RAM Standby Mode
192 #define AT91C_BCRAMC_LPCB_DEEP_POWER_DOWN (0x2 << 8) // (BCRAMC) Enable Cellular RAM Deep Power Down Mode
193 // -------- BCRAMC_MDR : (BCRAMC Offset: 0x10) BCRAM Controller Memory Device Register --------
194 #define AT91C_BCRAMC_MD (0x3 << 0) // (BCRAMC) Memory Device Type
195 #define AT91C_BCRAMC_MD_BCRAM_V10 (0x0) // (BCRAMC) Busrt Cellular RAM v1.0
196 #define AT91C_BCRAMC_MD_BCRAM_V15 (0x1) // (BCRAMC) Busrt Cellular RAM v1.5
197 #define AT91C_BCRAMC_MD_BCRAM_V20 (0x2) // (BCRAMC) Busrt Cellular RAM v2.0
199 // *****************************************************************************
200 // SOFTWARE API DEFINITION FOR SDRAM Controller Interface
201 // *****************************************************************************
202 // *** Register offset in AT91S_SDRAMC structure ***
203 #define SDRAMC_MR ( 0) // SDRAM Controller Mode Register
204 #define SDRAMC_TR ( 4) // SDRAM Controller Refresh Timer Register
205 #define SDRAMC_CR ( 8) // SDRAM Controller Configuration Register
206 #define SDRAMC_HSR (12) // SDRAM Controller High Speed Register
207 #define SDRAMC_LPR (16) // SDRAM Controller Low Power Register
208 #define SDRAMC_IER (20) // SDRAM Controller Interrupt Enable Register
209 #define SDRAMC_IDR (24) // SDRAM Controller Interrupt Disable Register
210 #define SDRAMC_IMR (28) // SDRAM Controller Interrupt Mask Register
211 #define SDRAMC_ISR (32) // SDRAM Controller Interrupt Mask Register
212 #define SDRAMC_MDR (36) // SDRAM Memory Device Register
213 // -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
214 #define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode
215 #define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode
216 #define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access
217 #define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
218 #define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access
219 #define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh
220 #define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register
221 #define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode
222 // -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
223 #define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter
224 // -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
225 #define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits
226 #define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits
227 #define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits
228 #define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits
229 #define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits
230 #define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits
231 #define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits
232 #define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits
233 #define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits
234 #define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks
235 #define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks
236 #define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks
237 #define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency
238 #define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles
239 #define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles
240 #define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width
241 #define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus
242 #define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus
243 #define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles
244 #define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0
245 #define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1
246 #define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2
247 #define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3
248 #define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4
249 #define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5
250 #define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6
251 #define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7
252 #define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8
253 #define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9
254 #define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10
255 #define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11
256 #define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12
257 #define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13
258 #define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14
259 #define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15
260 #define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
261 #define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0
262 #define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1
263 #define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2
264 #define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3
265 #define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4
266 #define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5
267 #define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6
268 #define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7
269 #define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8
270 #define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9
271 #define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10
272 #define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11
273 #define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12
274 #define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13
275 #define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14
276 #define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15
277 #define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
278 #define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0
279 #define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1
280 #define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2
281 #define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3
282 #define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4
283 #define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5
284 #define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6
285 #define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7
286 #define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8
287 #define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9
288 #define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10
289 #define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11
290 #define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12
291 #define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13
292 #define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14
293 #define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15
294 #define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
295 #define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0
296 #define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1
297 #define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2
298 #define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3
299 #define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4
300 #define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5
301 #define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6
302 #define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7
303 #define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8
304 #define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9
305 #define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10
306 #define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11
307 #define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12
308 #define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13
309 #define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14
310 #define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15
311 #define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
312 #define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0
313 #define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1
314 #define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2
315 #define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3
316 #define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4
317 #define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5
318 #define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6
319 #define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7
320 #define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8
321 #define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9
322 #define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10
323 #define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11
324 #define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12
325 #define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13
326 #define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14
327 #define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15
328 #define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
329 #define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0
330 #define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1
331 #define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2
332 #define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3
333 #define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4
334 #define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5
335 #define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6
336 #define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7
337 #define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8
338 #define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9
339 #define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10
340 #define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11
341 #define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12
342 #define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13
343 #define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14
344 #define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15
345 // -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------
346 #define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit
347 #define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle
348 #define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle
349 // -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------
350 #define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations
351 #define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features
352 #define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH
353 #define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN
354 #define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
355 #define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
356 #define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
357 #define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
358 #define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
359 #define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
360 #define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
361 #define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
362 // -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
363 #define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status
364 // -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
365 // -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
366 // -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
367 // -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
368 #define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type
369 #define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode
370 #define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode
372 // *****************************************************************************
373 // SOFTWARE API DEFINITION FOR DDR/SDRAM Controller
374 // *****************************************************************************
375 // *** Register offset in AT91S_SDDRC structure ***
376 #define SDDRC_MR ( 0) //
377 #define SDDRC_RTR ( 4) //
378 #define SDDRC_CR ( 8) //
379 #define SDDRC_T0PR (12) //
380 #define SDDRC_T1PR (16) //
381 #define SDDRC_HS (20) //
382 #define SDDRC_LPR (24) //
383 #define SDDRC_MDR (28) //
384 #define SDDRC_VERSION (252) //
385 // -------- SDDRC_MR : (SDDRC Offset: 0x0) --------
386 #define AT91C_MODE (0xF << 0) // (SDDRC)
387 #define AT91C_MODE_NORMAL_CMD (0x0) // (SDDRC) Normal Mode
388 #define AT91C_MODE_NOP_CMD (0x1) // (SDDRC) Issue a NOP Command at every access
389 #define AT91C_MODE_PRCGALL_CMD (0x2) // (SDDRC) Issue a All Banks Precharge Command at every access
390 #define AT91C_MODE_LMR_CMD (0x3) // (SDDRC) Issue a Load Mode Register at every access
391 #define AT91C_MODE_RFSH_CMD (0x4) // (SDDRC) Issue a Refresh
392 #define AT91C_MODE_EXT_LMR_CMD (0x5) // (SDDRC) Issue an Extended Load Mode Register
393 #define AT91C_MODE_DEEP_CMD (0x6) // (SDDRC) Enter Deep Power Mode
394 // -------- SDDRC_RTR : (SDDRC Offset: 0x4) --------
395 #define AT91C_COUNT (0xFFF << 0) // (SDDRC)
396 // -------- SDDRC_CR : (SDDRC Offset: 0x8) --------
397 #define AT91C_NC (0x3 << 0) // (SDDRC)
398 #define AT91C_NC_DDR9_SDR8 (0x0) // (SDDRC) DDR 9 Bits | SDR 8 Bits
399 #define AT91C_NC_DDR10_SDR9 (0x1) // (SDDRC) DDR 10 Bits | SDR 9 Bits
400 #define AT91C_NC_DDR11_SDR10 (0x2) // (SDDRC) DDR 11 Bits | SDR 10 Bits
401 #define AT91C_NC_DDR12_SDR11 (0x3) // (SDDRC) DDR 12 Bits | SDR 11 Bits
402 #define AT91C_NR (0x3 << 2) // (SDDRC)
403 #define AT91C_NR_11 (0x0 << 2) // (SDDRC) 11 Bits
404 #define AT91C_NR_12 (0x1 << 2) // (SDDRC) 12 Bits
405 #define AT91C_NR_13 (0x2 << 2) // (SDDRC) 13 Bits
406 #define AT91C_NR_14 (0x3 << 2) // (SDDRC) 14 Bits
407 #define AT91C_CAS (0x7 << 4) // (SDDRC)
408 #define AT91C_CAS_2 (0x2 << 4) // (SDDRC) 2 cycles
409 #define AT91C_CAS_3 (0x3 << 4) // (SDDRC) 3 cycles
410 #define AT91C_DLL (0x1 << 7) // (SDDRC)
411 #define AT91C_DLL_RESET_DISABLED (0x0 << 7) // (SDDRC) Disable DLL reset
412 #define AT91C_DLL_RESET_ENABLED (0x1 << 7) // (SDDRC) Enable DLL reset
413 #define AT91C_DIC_DS (0x1 << 8) // (SDDRC)
414 // -------- SDDRC_T0PR : (SDDRC Offset: 0xc) --------
415 #define AT91C_TRAS (0xF << 0) // (SDDRC)
416 #define AT91C_TRAS_0 (0x0) // (SDDRC) Value : 0
417 #define AT91C_TRAS_1 (0x1) // (SDDRC) Value : 1
418 #define AT91C_TRAS_2 (0x2) // (SDDRC) Value : 2
419 #define AT91C_TRAS_3 (0x3) // (SDDRC) Value : 3
420 #define AT91C_TRAS_4 (0x4) // (SDDRC) Value : 4
421 #define AT91C_TRAS_5 (0x5) // (SDDRC) Value : 5
422 #define AT91C_TRAS_6 (0x6) // (SDDRC) Value : 6
423 #define AT91C_TRAS_7 (0x7) // (SDDRC) Value : 7
424 #define AT91C_TRAS_8 (0x8) // (SDDRC) Value : 8
425 #define AT91C_TRAS_9 (0x9) // (SDDRC) Value : 9
426 #define AT91C_TRAS_10 (0xA) // (SDDRC) Value : 10
427 #define AT91C_TRAS_11 (0xB) // (SDDRC) Value : 11
428 #define AT91C_TRAS_12 (0xC) // (SDDRC) Value : 12
429 #define AT91C_TRAS_13 (0xD) // (SDDRC) Value : 13
430 #define AT91C_TRAS_14 (0xE) // (SDDRC) Value : 14
431 #define AT91C_TRAS_15 (0xF) // (SDDRC) Value : 15
432 #define AT91C_TRCD (0xF << 4) // (SDDRC)
433 #define AT91C_TRCD_0 (0x0 << 4) // (SDDRC) Value : 0
434 #define AT91C_TRCD_1 (0x1 << 4) // (SDDRC) Value : 1
435 #define AT91C_TRCD_2 (0x2 << 4) // (SDDRC) Value : 2
436 #define AT91C_TRCD_3 (0x3 << 4) // (SDDRC) Value : 3
437 #define AT91C_TRCD_4 (0x4 << 4) // (SDDRC) Value : 4
438 #define AT91C_TRCD_5 (0x5 << 4) // (SDDRC) Value : 5
439 #define AT91C_TRCD_6 (0x6 << 4) // (SDDRC) Value : 6
440 #define AT91C_TRCD_7 (0x7 << 4) // (SDDRC) Value : 7
441 #define AT91C_TRCD_8 (0x8 << 4) // (SDDRC) Value : 8
442 #define AT91C_TRCD_9 (0x9 << 4) // (SDDRC) Value : 9
443 #define AT91C_TRCD_10 (0xA << 4) // (SDDRC) Value : 10
444 #define AT91C_TRCD_11 (0xB << 4) // (SDDRC) Value : 11
445 #define AT91C_TRCD_12 (0xC << 4) // (SDDRC) Value : 12
446 #define AT91C_TRCD_13 (0xD << 4) // (SDDRC) Value : 13
447 #define AT91C_TRCD_14 (0xE << 4) // (SDDRC) Value : 14
448 #define AT91C_TRCD_15 (0xF << 4) // (SDDRC) Value : 15
449 #define AT91C_TWR (0xF << 8) // (SDDRC)
450 #define AT91C_TWR_0 (0x0 << 8) // (SDDRC) Value : 0
451 #define AT91C_TWR_1 (0x1 << 8) // (SDDRC) Value : 1
452 #define AT91C_TWR_2 (0x2 << 8) // (SDDRC) Value : 2
453 #define AT91C_TWR_3 (0x3 << 8) // (SDDRC) Value : 3
454 #define AT91C_TWR_4 (0x4 << 8) // (SDDRC) Value : 4
455 #define AT91C_TWR_5 (0x5 << 8) // (SDDRC) Value : 5
456 #define AT91C_TWR_6 (0x6 << 8) // (SDDRC) Value : 6
457 #define AT91C_TWR_7 (0x7 << 8) // (SDDRC) Value : 7
458 #define AT91C_TWR_8 (0x8 << 8) // (SDDRC) Value : 8
459 #define AT91C_TWR_9 (0x9 << 8) // (SDDRC) Value : 9
460 #define AT91C_TWR_10 (0xA << 8) // (SDDRC) Value : 10
461 #define AT91C_TWR_11 (0xB << 8) // (SDDRC) Value : 11
462 #define AT91C_TWR_12 (0xC << 8) // (SDDRC) Value : 12
463 #define AT91C_TWR_13 (0xD << 8) // (SDDRC) Value : 13
464 #define AT91C_TWR_14 (0xE << 8) // (SDDRC) Value : 14
465 #define AT91C_TWR_15 (0xF << 8) // (SDDRC) Value : 15
466 #define AT91C_TRC (0xF << 12) // (SDDRC)
467 #define AT91C_TRC_0 (0x0 << 12) // (SDDRC) Value : 0
468 #define AT91C_TRC_1 (0x1 << 12) // (SDDRC) Value : 1
469 #define AT91C_TRC_2 (0x2 << 12) // (SDDRC) Value : 2
470 #define AT91C_TRC_3 (0x3 << 12) // (SDDRC) Value : 3
471 #define AT91C_TRC_4 (0x4 << 12) // (SDDRC) Value : 4
472 #define AT91C_TRC_5 (0x5 << 12) // (SDDRC) Value : 5
473 #define AT91C_TRC_6 (0x6 << 12) // (SDDRC) Value : 6
474 #define AT91C_TRC_7 (0x7 << 12) // (SDDRC) Value : 7
475 #define AT91C_TRC_8 (0x8 << 12) // (SDDRC) Value : 8
476 #define AT91C_TRC_9 (0x9 << 12) // (SDDRC) Value : 9
477 #define AT91C_TRC_10 (0xA << 12) // (SDDRC) Value : 10
478 #define AT91C_TRC_11 (0xB << 12) // (SDDRC) Value : 11
479 #define AT91C_TRC_12 (0xC << 12) // (SDDRC) Value : 12
480 #define AT91C_TRC_13 (0xD << 12) // (SDDRC) Value : 13
481 #define AT91C_TRC_14 (0xE << 12) // (SDDRC) Value : 14
482 #define AT91C_TRC_15 (0xF << 12) // (SDDRC) Value : 15
483 #define AT91C_TRP (0xF << 16) // (SDDRC)
484 #define AT91C_TRP_0 (0x0 << 16) // (SDDRC) Value : 0
485 #define AT91C_TRP_1 (0x1 << 16) // (SDDRC) Value : 1
486 #define AT91C_TRP_2 (0x2 << 16) // (SDDRC) Value : 2
487 #define AT91C_TRP_3 (0x3 << 16) // (SDDRC) Value : 3
488 #define AT91C_TRP_4 (0x4 << 16) // (SDDRC) Value : 4
489 #define AT91C_TRP_5 (0x5 << 16) // (SDDRC) Value : 5
490 #define AT91C_TRP_6 (0x6 << 16) // (SDDRC) Value : 6
491 #define AT91C_TRP_7 (0x7 << 16) // (SDDRC) Value : 7
492 #define AT91C_TRP_8 (0x8 << 16) // (SDDRC) Value : 8
493 #define AT91C_TRP_9 (0x9 << 16) // (SDDRC) Value : 9
494 #define AT91C_TRP_10 (0xA << 16) // (SDDRC) Value : 10
495 #define AT91C_TRP_11 (0xB << 16) // (SDDRC) Value : 11
496 #define AT91C_TRP_12 (0xC << 16) // (SDDRC) Value : 12
497 #define AT91C_TRP_13 (0xD << 16) // (SDDRC) Value : 13
498 #define AT91C_TRP_14 (0xE << 16) // (SDDRC) Value : 14
499 #define AT91C_TRP_15 (0xF << 16) // (SDDRC) Value : 15
500 #define AT91C_TRRD (0xF << 20) // (SDDRC)
501 #define AT91C_TRRD_0 (0x0 << 20) // (SDDRC) Value : 0
502 #define AT91C_TRRD_1 (0x1 << 20) // (SDDRC) Value : 1
503 #define AT91C_TRRD_2 (0x2 << 20) // (SDDRC) Value : 2
504 #define AT91C_TRRD_3 (0x3 << 20) // (SDDRC) Value : 3
505 #define AT91C_TRRD_4 (0x4 << 20) // (SDDRC) Value : 4
506 #define AT91C_TRRD_5 (0x5 << 20) // (SDDRC) Value : 5
507 #define AT91C_TRRD_6 (0x6 << 20) // (SDDRC) Value : 6
508 #define AT91C_TRRD_7 (0x7 << 20) // (SDDRC) Value : 7
509 #define AT91C_TRRD_8 (0x8 << 20) // (SDDRC) Value : 8
510 #define AT91C_TRRD_9 (0x9 << 20) // (SDDRC) Value : 9
511 #define AT91C_TRRD_10 (0xA << 20) // (SDDRC) Value : 10
512 #define AT91C_TRRD_11 (0xB << 20) // (SDDRC) Value : 11
513 #define AT91C_TRRD_12 (0xC << 20) // (SDDRC) Value : 12
514 #define AT91C_TRRD_13 (0xD << 20) // (SDDRC) Value : 13
515 #define AT91C_TRRD_14 (0xE << 20) // (SDDRC) Value : 14
516 #define AT91C_TRRD_15 (0xF << 20) // (SDDRC) Value : 15
517 #define AT91C_TWTR (0x1 << 24) // (SDDRC)
518 #define AT91C_TWTR_0 (0x0 << 24) // (SDDRC) Value : 0
519 #define AT91C_TWTR_1 (0x1 << 24) // (SDDRC) Value : 1
520 #define AT91C_TMRD (0xF << 28) // (SDDRC)
521 #define AT91C_TMRD_0 (0x0 << 28) // (SDDRC) Value : 0
522 #define AT91C_TMRD_1 (0x1 << 28) // (SDDRC) Value : 1
523 #define AT91C_TMRD_2 (0x2 << 28) // (SDDRC) Value : 2
524 #define AT91C_TMRD_3 (0x3 << 28) // (SDDRC) Value : 3
525 #define AT91C_TMRD_4 (0x4 << 28) // (SDDRC) Value : 4
526 #define AT91C_TMRD_5 (0x5 << 28) // (SDDRC) Value : 5
527 #define AT91C_TMRD_6 (0x6 << 28) // (SDDRC) Value : 6
528 #define AT91C_TMRD_7 (0x7 << 28) // (SDDRC) Value : 7
529 #define AT91C_TMRD_8 (0x8 << 28) // (SDDRC) Value : 8
530 #define AT91C_TMRD_9 (0x9 << 28) // (SDDRC) Value : 9
531 #define AT91C_TMRD_10 (0xA << 28) // (SDDRC) Value : 10
532 #define AT91C_TMRD_11 (0xB << 28) // (SDDRC) Value : 11
533 #define AT91C_TMRD_12 (0xC << 28) // (SDDRC) Value : 12
534 #define AT91C_TMRD_13 (0xD << 28) // (SDDRC) Value : 13
535 #define AT91C_TMRD_14 (0xE << 28) // (SDDRC) Value : 14
536 #define AT91C_TMRD_15 (0xF << 28) // (SDDRC) Value : 15
537 // -------- SDDRC_T1PR : (SDDRC Offset: 0x10) --------
538 #define AT91C_TRFC (0x1F << 0) // (SDDRC)
539 #define AT91C_TRFC_0 (0x0) // (SDDRC) Value : 0
540 #define AT91C_TRFC_1 (0x1) // (SDDRC) Value : 1
541 #define AT91C_TRFC_2 (0x2) // (SDDRC) Value : 2
542 #define AT91C_TRFC_3 (0x3) // (SDDRC) Value : 3
543 #define AT91C_TRFC_4 (0x4) // (SDDRC) Value : 4
544 #define AT91C_TRFC_5 (0x5) // (SDDRC) Value : 5
545 #define AT91C_TRFC_6 (0x6) // (SDDRC) Value : 6
546 #define AT91C_TRFC_7 (0x7) // (SDDRC) Value : 7
547 #define AT91C_TRFC_8 (0x8) // (SDDRC) Value : 8
548 #define AT91C_TRFC_9 (0x9) // (SDDRC) Value : 9
549 #define AT91C_TRFC_10 (0xA) // (SDDRC) Value : 10
550 #define AT91C_TRFC_11 (0xB) // (SDDRC) Value : 11
551 #define AT91C_TRFC_12 (0xC) // (SDDRC) Value : 12
552 #define AT91C_TRFC_13 (0xD) // (SDDRC) Value : 13
553 #define AT91C_TRFC_14 (0xE) // (SDDRC) Value : 14
554 #define AT91C_TRFC_15 (0xF) // (SDDRC) Value : 15
555 #define AT91C_TXSNR (0xFF << 8) // (SDDRC)
556 #define AT91C_TXSNR_0 (0x0 << 8) // (SDDRC) Value : 0
557 #define AT91C_TXSNR_1 (0x1 << 8) // (SDDRC) Value : 1
558 #define AT91C_TXSNR_2 (0x2 << 8) // (SDDRC) Value : 2
559 #define AT91C_TXSNR_3 (0x3 << 8) // (SDDRC) Value : 3
560 #define AT91C_TXSNR_4 (0x4 << 8) // (SDDRC) Value : 4
561 #define AT91C_TXSNR_5 (0x5 << 8) // (SDDRC) Value : 5
562 #define AT91C_TXSNR_6 (0x6 << 8) // (SDDRC) Value : 6
563 #define AT91C_TXSNR_7 (0x7 << 8) // (SDDRC) Value : 7
564 #define AT91C_TXSNR_8 (0x8 << 8) // (SDDRC) Value : 8
565 #define AT91C_TXSNR_9 (0x9 << 8) // (SDDRC) Value : 9
566 #define AT91C_TXSNR_10 (0xA << 8) // (SDDRC) Value : 10
567 #define AT91C_TXSNR_11 (0xB << 8) // (SDDRC) Value : 11
568 #define AT91C_TXSNR_12 (0xC << 8) // (SDDRC) Value : 12
569 #define AT91C_TXSNR_13 (0xD << 8) // (SDDRC) Value : 13
570 #define AT91C_TXSNR_14 (0xE << 8) // (SDDRC) Value : 14
571 #define AT91C_TXSNR_15 (0xF << 8) // (SDDRC) Value : 15
572 #define AT91C_TXSRD (0xFF << 16) // (SDDRC)
573 #define AT91C_TXSRD_0 (0x0 << 16) // (SDDRC) Value : 0
574 #define AT91C_TXSRD_1 (0x1 << 16) // (SDDRC) Value : 1
575 #define AT91C_TXSRD_2 (0x2 << 16) // (SDDRC) Value : 2
576 #define AT91C_TXSRD_3 (0x3 << 16) // (SDDRC) Value : 3
577 #define AT91C_TXSRD_4 (0x4 << 16) // (SDDRC) Value : 4
578 #define AT91C_TXSRD_5 (0x5 << 16) // (SDDRC) Value : 5
579 #define AT91C_TXSRD_6 (0x6 << 16) // (SDDRC) Value : 6
580 #define AT91C_TXSRD_7 (0x7 << 16) // (SDDRC) Value : 7
581 #define AT91C_TXSRD_8 (0x8 << 16) // (SDDRC) Value : 8
582 #define AT91C_TXSRD_9 (0x9 << 16) // (SDDRC) Value : 9
583 #define AT91C_TXSRD_10 (0xA << 16) // (SDDRC) Value : 10
584 #define AT91C_TXSRD_11 (0xB << 16) // (SDDRC) Value : 11
585 #define AT91C_TXSRD_12 (0xC << 16) // (SDDRC) Value : 12
586 #define AT91C_TXSRD_13 (0xD << 16) // (SDDRC) Value : 13
587 #define AT91C_TXSRD_14 (0xE << 16) // (SDDRC) Value : 14
588 #define AT91C_TXSRD_15 (0xF << 16) // (SDDRC) Value : 15
589 // -------- SDDRC_HS : (SDDRC Offset: 0x14) --------
590 #define AT91C_DA (0x1 << 0) // (SDDRC)
591 #define AT91C_OVL (0x1 << 1) // (SDDRC)
592 // -------- SDDRC_LPR : (SDDRC Offset: 0x18) --------
593 #define AT91C_LPCB (0x3 << 0) // (SDDRC)
594 #define AT91C_PASR (0x7 << 4) // (SDDRC)
595 #define AT91C_LP_TRC (0x3 << 8) // (SDDRC)
596 #define AT91C_DS (0x3 << 10) // (SDDRC)
597 #define AT91C_TIMEOUT (0x3 << 12) // (SDDRC)
598 // -------- SDDRC_MDR : (SDDRC Offset: 0x1c) --------
599 #define AT91C_MD (0x3 << 0) // (SDDRC)
600 #define AT91C_MD_SDR_SDRAM (0x0) // (SDDRC) SDR_SDRAM
601 #define AT91C_MD_LP_SDR_SDRAM (0x1) // (SDDRC) Low Power SDR_SDRAM
602 #define AT91C_MD_DDR_SDRAM (0x2) // (SDDRC) DDR_SDRAM
603 #define AT91C_MD_LP_DDR_SDRAM (0x3) // (SDDRC) Low Power DDR_SDRAM
604 #define AT91C_B16MODE (0x1 << 4) // (SDDRC)
605 #define AT91C_B16MODE_32_BITS (0x0 << 4) // (SDDRC) 32 Bits datas bus
606 #define AT91C_B16MODE_16_BITS (0x1 << 4) // (SDDRC) 16 Bits datas bus
608 // *****************************************************************************
609 // SOFTWARE API DEFINITION FOR Static Memory Controller Interface
610 // *****************************************************************************
611 // *** Register offset in AT91S_SMC structure ***
612 #define SMC_SETUP0 ( 0) // Setup Register for CS 0
613 #define SMC_PULSE0 ( 4) // Pulse Register for CS 0
614 #define SMC_CYCLE0 ( 8) // Cycle Register for CS 0
615 #define SMC_CTRL0 (12) // Control Register for CS 0
616 #define SMC_SETUP1 (16) // Setup Register for CS 1
617 #define SMC_PULSE1 (20) // Pulse Register for CS 1
618 #define SMC_CYCLE1 (24) // Cycle Register for CS 1
619 #define SMC_CTRL1 (28) // Control Register for CS 1
620 #define SMC_SETUP2 (32) // Setup Register for CS 2
621 #define SMC_PULSE2 (36) // Pulse Register for CS 2
622 #define SMC_CYCLE2 (40) // Cycle Register for CS 2
623 #define SMC_CTRL2 (44) // Control Register for CS 2
624 #define SMC_SETUP3 (48) // Setup Register for CS 3
625 #define SMC_PULSE3 (52) // Pulse Register for CS 3
626 #define SMC_CYCLE3 (56) // Cycle Register for CS 3
627 #define SMC_CTRL3 (60) // Control Register for CS 3
628 #define SMC_SETUP4 (64) // Setup Register for CS 4
629 #define SMC_PULSE4 (68) // Pulse Register for CS 4
630 #define SMC_CYCLE4 (72) // Cycle Register for CS 4
631 #define SMC_CTRL4 (76) // Control Register for CS 4
632 #define SMC_SETUP5 (80) // Setup Register for CS 5
633 #define SMC_PULSE5 (84) // Pulse Register for CS 5
634 #define SMC_CYCLE5 (88) // Cycle Register for CS 5
635 #define SMC_CTRL5 (92) // Control Register for CS 5
636 #define SMC_SETUP6 (96) // Setup Register for CS 6
637 #define SMC_PULSE6 (100) // Pulse Register for CS 6
638 #define SMC_CYCLE6 (104) // Cycle Register for CS 6
639 #define SMC_CTRL6 (108) // Control Register for CS 6
640 #define SMC_SETUP7 (112) // Setup Register for CS 7
641 #define SMC_PULSE7 (116) // Pulse Register for CS 7
642 #define SMC_CYCLE7 (120) // Cycle Register for CS 7
643 #define SMC_CTRL7 (124) // Control Register for CS 7
644 // -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------
645 #define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length
646 #define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access
647 #define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length
648 #define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
649 // -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------
650 #define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length
651 #define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access
652 #define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length
653 #define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
654 // -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------
655 #define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length
656 #define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length
657 // -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
658 #define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode
659 #define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode
660 #define AT91C_SMC_NWAITM (0x3 << 5) // (SMC) NWAIT Mode
661 #define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) // (SMC) External NWAIT disabled.
662 #define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) // (SMC) External NWAIT enabled in frozen mode.
663 #define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) // (SMC) External NWAIT enabled in ready mode.
664 #define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type
665 #define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
666 #define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
667 #define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width
668 #define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.
669 #define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.
670 #define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
671 #define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.
672 #define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.
673 #define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.
674 #define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size
675 #define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.
676 #define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.
677 #define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.
678 #define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
679 // -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
680 // -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
681 // -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
682 // -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
683 // -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
684 // -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
685 // -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
686 // -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
687 // -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
688 // -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
689 // -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
690 // -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
691 // -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
692 // -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
693 // -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
694 // -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
695 // -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
696 // -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
697 // -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
698 // -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
699 // -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
700 // -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
701 // -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
702 // -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
703 // -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
704 // -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
705 // -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
706 // -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
708 // *****************************************************************************
709 // SOFTWARE API DEFINITION FOR Slave Priority Registers
710 // *****************************************************************************
711 // *** Register offset in AT91S_MATRIX_PRS structure ***
712 #define MATRIX_PRAS ( 0) // Slave Priority Registers A for Slave
713 #define MATRIX_PRBS ( 4) // Slave Priority Registers B for Slave
715 // *****************************************************************************
716 // SOFTWARE API DEFINITION FOR AHB Matrix Interface
717 // *****************************************************************************
718 // *** Register offset in AT91S_MATRIX structure ***
719 #define MATRIX_MCFG ( 0) // Master Configuration Register
720 #define MATRIX_SCFG (64) // Slave Configuration Register
721 #define MATRIX_PRS (128) // Slave Priority Registers
722 #define MATRIX_MRCR (256) // Master Remp Control Register
723 // -------- MATRIX_MCFG : (MATRIX Offset: 0x0) Master Configuration Register rom --------
724 #define AT91C_MATRIX_ULBT (0x7 << 0) // (MATRIX) Undefined Length Burst Type
725 // -------- MATRIX_SCFG : (MATRIX Offset: 0x40) Slave Configuration Register --------
726 #define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
727 #define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
728 #define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
729 #define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
730 #define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
731 #define AT91C_MATRIX_FIXED_DEFMSTR (0x7 << 18) // (MATRIX) Fixed Index of Default Master
732 #define AT91C_MATRIX_FIXED_DEFMSTR_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
733 #define AT91C_MATRIX_FIXED_DEFMSTR_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
734 #define AT91C_MATRIX_FIXED_DEFMSTR_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
735 #define AT91C_MATRIX_FIXED_DEFMSTR_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
736 #define AT91C_MATRIX_FIXED_DEFMSTR_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master
737 #define AT91C_MATRIX_FIXED_DEFMSTR_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master
738 #define AT91C_MATRIX_FIXED_DEFMSTR_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
739 #define AT91C_MATRIX_FIXED_DEFMSTR_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master
740 #define AT91C_MATRIX_FIXED_DEFMSTR_USB (0x8 << 18) // (MATRIX) USB Master is Default Master
741 #define AT91C_MATRIX_ARBT (0x3 << 24) // (MATRIX) Arbitration Type
742 // -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register --------
743 #define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command Bit for ARM926EJ-S Instruction
744 #define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command Bit for ARM926EJ-S Data
745 #define AT91C_MATRIX_RCB2 (0x1 << 2) // (MATRIX) Remap Command Bit for PDC
746 #define AT91C_MATRIX_RCB3 (0x1 << 3) // (MATRIX) Remap Command Bit for LCD
747 #define AT91C_MATRIX_RCB4 (0x1 << 4) // (MATRIX) Remap Command Bit for 2DGC
748 #define AT91C_MATRIX_RCB5 (0x1 << 5) // (MATRIX) Remap Command Bit for ISI
749 #define AT91C_MATRIX_RCB6 (0x1 << 6) // (MATRIX) Remap Command Bit for DMA
750 #define AT91C_MATRIX_RCB7 (0x1 << 7) // (MATRIX) Remap Command Bit for EMAC
751 #define AT91C_MATRIX_RCB8 (0x1 << 8) // (MATRIX) Remap Command Bit for USB
752 #define AT91C_MATRIX_RCB9 (0x1 << 9) // (MATRIX) Remap Command Bit for USB
753 #define AT91C_MATRIX_RCB10 (0x1 << 10) // (MATRIX) Remap Command Bit for USB
754 #define AT91C_MATRIX_RCB11 (0x1 << 11) // (MATRIX) Remap Command Bit for USB
756 // *****************************************************************************
757 // SOFTWARE API DEFINITION FOR AHB CCFG Interface
758 // *****************************************************************************
759 // *** Register offset in AT91S_CCFG structure ***
760 #define CCFG_MPBS0 ( 4) // Slave 1 (MP Block Slave 0) Special Function Register
761 #define CCFG_UDPHS ( 8) // Slave 2 (AHB Periphs) Special Function Register
762 #define CCFG_MPBS1 (12) // Slave 3 (MP Block Slave 1) Special Function Register
763 #define CCFG_EBICSA (16) // EBI Chip Select Assignement Register
764 #define CCFG_MPBS2 (28) // Slave 7 (MP Block Slave 2) Special Function Register
765 #define CCFG_MPBS3 (32) // Slave 7 (MP Block Slave 3) Special Function Register
766 #define CCFG_BRIDGE (36) // Slave 8 (APB Bridge) Special Function Register
767 #define CCFG_MATRIXVERSION (236) // Version Register
768 // -------- CCFG_UDPHS : (CCFG Offset: 0x8) UDPHS Configuration --------
769 #define AT91C_CCFG_UDPHS_UDP_SELECT (0x1 << 31) // (CCFG) UDPHS or UDP Selection
770 #define AT91C_CCFG_UDPHS_UDP_SELECT_UDPHS (0x0 << 31) // (CCFG) UDPHS Selected.
771 #define AT91C_CCFG_UDPHS_UDP_SELECT_UDP (0x1 << 31) // (CCFG) UDP Selected.
772 // -------- CCFG_EBICSA : (CCFG Offset: 0x10) EBI Chip Select Assignement Register --------
773 #define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment
774 #define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
775 #define AT91C_EBI_CS1A_BCRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the BCRAM Controller.
776 #define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment
777 #define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
778 #define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
779 #define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment
780 #define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
781 #define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
782 #define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment
783 #define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
784 #define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
785 #define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration
786 #define AT91C_EBI_DDRPUC (0x1 << 9) // (CCFG) DDDR DQS Pull-up Configuration
787 #define AT91C_EBI_SUP (0x1 << 16) // (CCFG) EBI Supply
788 #define AT91C_EBI_SUP_1V8 (0x0 << 16) // (CCFG) EBI Supply is 1.8V
789 #define AT91C_EBI_SUP_3V3 (0x1 << 16) // (CCFG) EBI Supply is 3.3V
790 #define AT91C_EBI_LP (0x1 << 17) // (CCFG) EBI Low Power Reduction
791 #define AT91C_EBI_LP_LOW_DRIVE (0x0 << 17) // (CCFG) EBI Pads are in Standard drive
792 #define AT91C_EBI_LP_STD_DRIVE (0x1 << 17) // (CCFG) EBI Pads are in Low Drive (Low Power)
793 #define AT91C_CCFG_DDR_SDR_SELECT (0x1 << 31) // (CCFG) DDR or SDR Selection
794 #define AT91C_CCFG_DDR_SDR_SELECT_DDR (0x0 << 31) // (CCFG) DDR Selected.
795 #define AT91C_CCFG_DDR_SDR_SELECT_SDR (0x1 << 31) // (CCFG) SDR Selected.
796 // -------- CCFG_BRIDGE : (CCFG Offset: 0x24) BRIDGE Configuration --------
797 #define AT91C_CCFG_AES_TDES_SELECT (0x1 << 31) // (CCFG) AES or TDES Selection
798 #define AT91C_CCFG_AES_TDES_SELECT_AES (0x0 << 31) // (CCFG) AES Selected.
799 #define AT91C_CCFG_AES_TDES_SELECT_TDES (0x1 << 31) // (CCFG) TDES Selected.
801 // *****************************************************************************
802 // SOFTWARE API DEFINITION FOR Peripheral DMA Controller
803 // *****************************************************************************
804 // *** Register offset in AT91S_PDC structure ***
805 #define PDC_RPR ( 0) // Receive Pointer Register
806 #define PDC_RCR ( 4) // Receive Counter Register
807 #define PDC_TPR ( 8) // Transmit Pointer Register
808 #define PDC_TCR (12) // Transmit Counter Register
809 #define PDC_RNPR (16) // Receive Next Pointer Register
810 #define PDC_RNCR (20) // Receive Next Counter Register
811 #define PDC_TNPR (24) // Transmit Next Pointer Register
812 #define PDC_TNCR (28) // Transmit Next Counter Register
813 #define PDC_PTCR (32) // PDC Transfer Control Register
814 #define PDC_PTSR (36) // PDC Transfer Status Register
815 // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
816 #define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
817 #define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
818 #define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
819 #define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
820 // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
822 // *****************************************************************************
823 // SOFTWARE API DEFINITION FOR Debug Unit
824 // *****************************************************************************
825 // *** Register offset in AT91S_DBGU structure ***
826 #define DBGU_CR ( 0) // Control Register
827 #define DBGU_MR ( 4) // Mode Register
828 #define DBGU_IER ( 8) // Interrupt Enable Register
829 #define DBGU_IDR (12) // Interrupt Disable Register
830 #define DBGU_IMR (16) // Interrupt Mask Register
831 #define DBGU_CSR (20) // Channel Status Register
832 #define DBGU_RHR (24) // Receiver Holding Register
833 #define DBGU_THR (28) // Transmitter Holding Register
834 #define DBGU_BRGR (32) // Baud Rate Generator Register
835 #define DBGU_CIDR (64) // Chip ID Register
836 #define DBGU_EXID (68) // Chip ID Extension Register
837 #define DBGU_FNTR (72) // Force NTRST Register
838 #define DBGU_RPR (256) // Receive Pointer Register
839 #define DBGU_RCR (260) // Receive Counter Register
840 #define DBGU_TPR (264) // Transmit Pointer Register
841 #define DBGU_TCR (268) // Transmit Counter Register
842 #define DBGU_RNPR (272) // Receive Next Pointer Register
843 #define DBGU_RNCR (276) // Receive Next Counter Register
844 #define DBGU_TNPR (280) // Transmit Next Pointer Register
845 #define DBGU_TNCR (284) // Transmit Next Counter Register
846 #define DBGU_PTCR (288) // PDC Transfer Control Register
847 #define DBGU_PTSR (292) // PDC Transfer Status Register
848 // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
849 #define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
850 #define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
851 #define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
852 #define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
853 #define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
854 #define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
855 #define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
856 // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
857 #define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
858 #define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
859 #define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
860 #define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
861 #define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
862 #define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
863 #define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
864 #define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
865 #define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
866 #define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
867 #define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
868 #define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
869 // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
870 #define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
871 #define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
872 #define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
873 #define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
874 #define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
875 #define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
876 #define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
877 #define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
878 #define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
879 #define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
880 #define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
881 #define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
882 // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
883 // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
884 // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
885 // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
886 #define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
888 // *****************************************************************************
889 // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
890 // *****************************************************************************
891 // *** Register offset in AT91S_AIC structure ***
892 #define AIC_SMR ( 0) // Source Mode Register
893 #define AIC_SVR (128) // Source Vector Register
894 #define AIC_IVR (256) // IRQ Vector Register
895 #define AIC_FVR (260) // FIQ Vector Register
896 #define AIC_ISR (264) // Interrupt Status Register
897 #define AIC_IPR (268) // Interrupt Pending Register
898 #define AIC_IMR (272) // Interrupt Mask Register
899 #define AIC_CISR (276) // Core Interrupt Status Register
900 #define AIC_IECR (288) // Interrupt Enable Command Register
901 #define AIC_IDCR (292) // Interrupt Disable Command Register
902 #define AIC_ICCR (296) // Interrupt Clear Command Register
903 #define AIC_ISCR (300) // Interrupt Set Command Register
904 #define AIC_EOICR (304) // End of Interrupt Command Register
905 #define AIC_SPU (308) // Spurious Vector Register
906 #define AIC_DCR (312) // Debug Control Register (Protect)
907 #define AIC_FFER (320) // Fast Forcing Enable Register
908 #define AIC_FFDR (324) // Fast Forcing Disable Register
909 #define AIC_FFSR (328) // Fast Forcing Status Register
910 // -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
911 #define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
912 #define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
913 #define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
914 #define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
915 #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
916 #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
917 #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
918 #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
919 // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
920 #define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
921 #define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
922 // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
923 #define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
924 #define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
926 // *****************************************************************************
927 // SOFTWARE API DEFINITION FOR Parallel Input Output Controler
928 // *****************************************************************************
929 // *** Register offset in AT91S_PIO structure ***
930 #define PIO_PER(p) ( 0 + (p) * 0x200) // PIO Enable Register
931 #define PIO_PDR(p) ( 4 + (p) * 0x200) // PIO Disable Register
932 #define PIO_PSR(p) ( 8 + (p) * 0x200) // PIO Status Register
933 #define PIO_OER(p) (16 + (p) * 0x200) // Output Enable Register
934 #define PIO_ODR(p) (20 + (p) * 0x200) // Output Disable Registerr
935 #define PIO_OSR(p) (24 + (p) * 0x200) // Output Status Register
936 #define PIO_IFER(p) (32 + (p) * 0x200) // Input Filter Enable Register
937 #define PIO_IFDR(p) (36 + (p) * 0x200) // Input Filter Disable Register
938 #define PIO_IFSR(p) (40 + (p) * 0x200) // Input Filter Status Register
939 #define PIO_SODR(p) (48 + (p) * 0x200) // Set Output Data Register
940 #define PIO_CODR(p) (52 + (p) * 0x200) // Clear Output Data Register
941 #define PIO_ODSR(p) (56 + (p) * 0x200) // Output Data Status Register
942 #define PIO_PDSR(p) (60 + (p) * 0x200) // Pin Data Status Register
943 #define PIO_IER(p) (64 + (p) * 0x200) // Interrupt Enable Register
944 #define PIO_IDR(p) (68 + (p) * 0x200) // Interrupt Disable Register
945 #define PIO_IMR(p) (72 + (p) * 0x200) // Interrupt Mask Register
946 #define PIO_ISR(p) (76 + (p) * 0x200) // Interrupt Status Register
947 #define PIO_MDER(p) (80 + (p) * 0x200) // Multi-driver Enable Register
948 #define PIO_MDDR(p) (84 + (p) * 0x200) // Multi-driver Disable Register
949 #define PIO_MDSR(p) (88 + (p) * 0x200) // Multi-driver Status Register
950 #define PIO_PPUDR(p) (96 + (p) * 0x200) // Pull-up Disable Register
951 #define PIO_PPUER(p) (100 + (p) * 0x200) // Pull-up Enable Register
952 #define PIO_PPUSR(p) (104 + (p) * 0x200) // Pull-up Status Register
953 #define PIO_ASR(p) (112 + (p) * 0x200) // Select A Register
954 #define PIO_BSR(p) (116 + (p) * 0x200) // Select B Register
955 #define PIO_ABSR(p) (120 + (p) * 0x200) // AB Select Status Register
956 #define PIO_OWER(p) (160 + (p) * 0x200) // Output Write Enable Register
957 #define PIO_OWDR(p) (164 + (p) * 0x200) // Output Write Disable Register
958 #define PIO_OWSR(p) (168 + (p) * 0x200) // Output Write Status Register
960 // *****************************************************************************
961 // SOFTWARE API DEFINITION FOR Clock Generator Controler
962 // *****************************************************************************
963 // *** Register offset in AT91S_CKGR structure ***
964 #define CKGR_UCKR ( 0) // UTMI Clock Configuration Register
965 #define CKGR_MOR ( 4) // Main Oscillator Register
966 #define CKGR_MCFR ( 8) // Main Clock Frequency Register
967 #define CKGR_PLLAR (12) // PLL A Register
968 #define CKGR_PLLBR (16) // PLL B Register
969 // -------- CKGR_UCKR : (CKGR Offset: 0x0) UTMI Clock Configuration Register --------
970 #define AT91C_CKGR_UPLLEN (0x1 << 16) // (CKGR) UTMI PLL Enable
971 #define AT91C_CKGR_UPLLEN_DISABLED (0x0 << 16) // (CKGR) The UTMI PLL is disabled
972 #define AT91C_CKGR_UPLLEN_ENABLED (0x1 << 16) // (CKGR) The UTMI PLL is enabled
973 #define AT91C_CKGR_PLLCOUNT (0xF << 20) // (CKGR) UTMI Oscillator Start-up Time
974 #define AT91C_CKGR_BIASEN (0x1 << 24) // (CKGR) UTMI BIAS Enable
975 #define AT91C_CKGR_BIASEN_DISABLED (0x0 << 24) // (CKGR) The UTMI BIAS is disabled
976 #define AT91C_CKGR_BIASEN_ENABLED (0x1 << 24) // (CKGR) The UTMI BIAS is enabled
977 #define AT91C_CKGR_BIASCOUNT (0xF << 28) // (CKGR) UTMI BIAS Start-up Time
978 // -------- CKGR_MOR : (CKGR Offset: 0x4) Main Oscillator Register --------
979 #define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
980 #define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
981 #define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
982 // -------- CKGR_MCFR : (CKGR Offset: 0x8) Main Clock Frequency Register --------
983 #define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
984 #define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
985 // -------- CKGR_PLLAR : (CKGR Offset: 0xc) PLL A Register --------
986 #define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected
987 #define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0
988 #define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed
989 #define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter
990 #define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range
991 #define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
992 #define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
993 #define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
994 #define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
995 #define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier
996 #define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR)
997 // -------- CKGR_PLLBR : (CKGR Offset: 0x10) PLL B Register --------
998 #define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected
999 #define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0
1000 #define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed
1001 #define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter
1002 #define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range
1003 #define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
1004 #define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
1005 #define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
1006 #define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
1007 #define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier
1008 #define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
1009 #define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
1010 #define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
1011 #define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
1013 // *****************************************************************************
1014 // SOFTWARE API DEFINITION FOR Power Management Controler
1015 // *****************************************************************************
1016 // *** Register offset in AT91S_PMC structure ***
1017 #define PMC_SCER ( 0) // System Clock Enable Register
1018 #define PMC_SCDR ( 4) // System Clock Disable Register
1019 #define PMC_SCSR ( 8) // System Clock Status Register
1020 #define PMC_PCER (16) // Peripheral Clock Enable Register
1021 #define PMC_PCDR (20) // Peripheral Clock Disable Register
1022 #define PMC_PCSR (24) // Peripheral Clock Status Register
1023 #define PMC_UCKR (28) // UTMI Clock Configuration Register
1024 #define PMC_MOR (32) // Main Oscillator Register
1025 #define PMC_MCFR (36) // Main Clock Frequency Register
1026 #define PMC_PLLAR (40) // PLL A Register
1027 #define PMC_PLLBR (44) // PLL B Register
1028 #define PMC_MCKR (48) // Master Clock Register
1029 #define PMC_PCKR (64) // Programmable Clock Register
1030 #define PMC_IER (96) // Interrupt Enable Register
1031 #define PMC_IDR (100) // Interrupt Disable Register
1032 #define PMC_SR (104) // Status Register
1033 #define PMC_IMR (108) // Interrupt Mask Register
1034 // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
1035 #define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
1036 #define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock
1037 #define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock
1038 #define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
1039 #define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
1040 #define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
1041 #define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
1042 #define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
1043 // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
1044 // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
1045 // -------- CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register --------
1046 // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
1047 // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
1048 // -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
1049 // -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
1050 // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
1051 #define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
1052 #define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
1053 #define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
1054 #define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected
1055 #define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected
1056 #define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
1057 #define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
1058 #define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
1059 #define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
1060 #define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
1061 #define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
1062 #define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
1063 #define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
1064 #define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division
1065 #define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same
1066 #define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
1067 #define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock
1068 // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
1069 // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
1070 #define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
1071 #define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
1072 #define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
1073 #define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask
1074 #define AT91C_PMC_LOCKU (0x1 << 6) // (PMC) PLL UTMI Status/Enable/Disable/Mask
1075 #define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
1076 #define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
1077 #define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
1078 #define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
1079 // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
1080 // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
1081 // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
1083 // *****************************************************************************
1084 // SOFTWARE API DEFINITION FOR Reset Controller Interface
1085 // *****************************************************************************
1086 // *** Register offset in AT91S_RSTC structure ***
1087 #define RSTC_RCR ( 0) // Reset Control Register
1088 #define RSTC_RSR ( 4) // Reset Status Register
1089 #define RSTC_RMR ( 8) // Reset Mode Register
1090 // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
1091 #define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
1092 #define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset
1093 #define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
1094 #define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
1095 #define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
1096 // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
1097 #define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
1098 #define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
1099 #define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
1100 #define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
1101 #define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
1102 #define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
1103 #define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
1104 #define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
1105 #define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
1106 // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
1107 #define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
1108 #define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
1109 #define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
1111 // *****************************************************************************
1112 // SOFTWARE API DEFINITION FOR Shut Down Controller Interface
1113 // *****************************************************************************
1114 // *** Register offset in AT91S_SHDWC structure ***
1115 #define SHDWC_SHCR ( 0) // Shut Down Control Register
1116 #define SHDWC_SHMR ( 4) // Shut Down Mode Register
1117 #define SHDWC_SHSR ( 8) // Shut Down Status Register
1118 // -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------
1119 #define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset
1120 #define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password
1121 // -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------
1122 #define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection
1123 #define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.
1124 #define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level.
1125 #define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level.
1126 #define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.
1127 #define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0
1128 #define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection
1129 #define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input.
1130 #define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level.
1131 #define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level.
1132 #define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change.
1133 #define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1
1134 #define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
1135 #define AT91C_SHDWC_RTCWKEN (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable
1136 // -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------
1137 #define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status
1138 #define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status
1139 #define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status
1140 #define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up
1141 #define AT91C_SHDWC_RTCWK (0x1 << 17) // (SHDWC) Real Time Clock wake Up
1143 // *****************************************************************************
1144 // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
1145 // *****************************************************************************
1146 // *** Register offset in AT91S_RTTC structure ***
1147 #define RTTC_RTMR ( 0) // Real-time Mode Register
1148 #define RTTC_RTAR ( 4) // Real-time Alarm Register
1149 #define RTTC_RTVR ( 8) // Real-time Value Register
1150 #define RTTC_RTSR (12) // Real-time Status Register
1151 // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
1152 #define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
1153 #define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
1154 #define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
1155 #define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
1156 // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
1157 #define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
1158 // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
1159 #define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
1160 // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
1161 #define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
1162 #define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
1164 // *****************************************************************************
1165 // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
1166 // *****************************************************************************
1167 // *** Register offset in AT91S_PITC structure ***
1168 #define PITC_PIMR ( 0) // Period Interval Mode Register
1169 #define PITC_PISR ( 4) // Period Interval Status Register
1170 #define PITC_PIVR ( 8) // Period Interval Value Register
1171 #define PITC_PIIR (12) // Period Interval Image Register
1172 // -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
1173 #define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
1174 #define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
1175 #define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
1176 // -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
1177 #define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
1178 // -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
1179 #define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
1180 #define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
1181 // -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
1183 // *****************************************************************************
1184 // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
1185 // *****************************************************************************
1186 // *** Register offset in AT91S_WDTC structure ***
1187 #define WDTC_WDCR ( 0) // Watchdog Control Register
1188 #define WDTC_WDMR ( 4) // Watchdog Mode Register
1189 #define WDTC_WDSR ( 8) // Watchdog Status Register
1190 // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
1191 #define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
1192 #define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
1193 // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
1194 #define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
1195 #define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
1196 #define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
1197 #define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
1198 #define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
1199 #define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
1200 #define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
1201 #define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
1202 // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
1203 #define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
1204 #define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
1206 // *****************************************************************************
1207 // SOFTWARE API DEFINITION FOR USB Device Interface
1208 // *****************************************************************************
1209 // *** Register offset in AT91S_UDP structure ***
1210 #define UDP_NUM ( 0) // Frame Number Register
1211 #define UDP_GLBSTATE ( 4) // Global State Register
1212 #define UDP_FADDR ( 8) // Function Address Register
1213 #define UDP_IER (16) // Interrupt Enable Register
1214 #define UDP_IDR (20) // Interrupt Disable Register
1215 #define UDP_IMR (24) // Interrupt Mask Register
1216 #define UDP_ISR (28) // Interrupt Status Register
1217 #define UDP_ICR (32) // Interrupt Clear Register
1218 #define UDP_RSTEP (40) // Reset Endpoint Register
1219 #define UDP_CSR (48) // Endpoint Control and Status Register
1220 #define UDP_FDR (80) // Endpoint FIFO Data Register
1221 #define UDP_TXVC (116) // Transceiver Control Register
1222 // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
1223 #define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
1224 #define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
1225 #define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
1226 // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
1227 #define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
1228 #define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
1229 #define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
1230 #define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
1231 #define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
1232 // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
1233 #define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
1234 #define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
1235 // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
1236 #define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
1237 #define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
1238 #define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
1239 #define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
1240 #define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
1241 #define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
1242 #define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
1243 #define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
1244 #define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
1245 #define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
1246 #define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
1247 // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
1248 // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
1249 // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
1250 #define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
1251 // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
1252 // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
1253 #define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
1254 #define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
1255 #define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
1256 #define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
1257 #define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
1258 #define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
1259 // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
1260 #define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
1261 #define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
1262 #define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
1263 #define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
1264 #define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
1265 #define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
1266 #define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
1267 #define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
1268 #define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
1269 #define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
1270 #define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
1271 #define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
1272 #define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
1273 #define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
1274 #define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
1275 #define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
1276 #define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
1277 #define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
1278 #define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
1279 // -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
1280 #define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
1281 #define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
1283 // *****************************************************************************
1284 // SOFTWARE API DEFINITION FOR USB Enpoint FIFO data register
1285 // *****************************************************************************
1286 // *** Register offset in AT91S_UDPHS_EPTFIFO structure ***
1287 #define UDPHS_READEPT0 ( 0) // FIFO Endpoint Data Register 0
1288 #define UDPHS_READEPT1 (65536) // FIFO Endpoint Data Register 1
1289 #define UDPHS_READEPT2 (131072) // FIFO Endpoint Data Register 2
1290 #define UDPHS_READEPT3 (196608) // FIFO Endpoint Data Register 3
1291 #define UDPHS_READEPT4 (262144) // FIFO Endpoint Data Register 4
1292 #define UDPHS_READEPT5 (327680) // FIFO Endpoint Data Register 5
1293 #define UDPHS_READEPT6 (393216) // FIFO Endpoint Data Register 6
1294 #define UDPHS_READEPT7 (458752) // FIFO Endpoint Data Register 7
1295 #define UDPHS_READEPT8 (524288) // FIFO Endpoint Data Register 8
1296 #define UDPHS_READEPT9 (589824) // FIFO Endpoint Data Register 9
1297 #define UDPHS_READEPTA (655360) // FIFO Endpoint Data Register 10
1298 #define UDPHS_READEPTB (720896) // FIFO Endpoint Data Register 11
1299 #define UDPHS_READEPTC (786432) // FIFO Endpoint Data Register 12
1300 #define UDPHS_READEPTD (851968) // FIFO Endpoint Data Register 13
1301 #define UDPHS_READEPTE (917504) // FIFO Endpoint Data Register 14
1302 #define UDPHS_READEPTF (983040) // FIFO Endpoint Data Register 15
1304 // *****************************************************************************
1305 // SOFTWARE API DEFINITION FOR USB Endpoint struct
1306 // *****************************************************************************
1307 // *** Register offset in AT91S_UDPHS_EPT structure ***
1308 #define UDPHS_EPTCFG ( 0) // Endpoint Config Register
1309 #define UDPHS_EPTCTLENB ( 4) // Endpoint Control Enable Register
1310 #define UDPHS_EPTCTLDIS ( 8) // Endpoint Control Disable Register
1311 #define UDPHS_EPTCTL (12) // Endpoint Control Register
1312 #define UDPHS_EPTSETSTA (20) // Endpoint Set Status Register
1313 #define UDPHS_EPTCLRSTA (24) // Endpoint Clear Status Register
1314 #define UDPHS_EPTSTA (28) // Endpoint Status Register
1315 // -------- UDPHS_EPTCFG : (UDPHS_EPT Offset: 0x0) Endpoint Config Register --------
1316 #define AT91C_EPT_SIZE (0x1 << 0) // (UDPHS_EPT) Endpoint Size
1317 #define AT91C_EPT_SIZE_8 (0x0) // (UDPHS_EPT) 8 bytes
1318 #define AT91C_EPT_SIZE_16 (0x1) // (UDPHS_EPT) 16 bytes
1319 #define AT91C_EPT_SIZE_32 (0x2) // (UDPHS_EPT) 32 bytes
1320 #define AT91C_EPT_SIZE_64 (0x3) // (UDPHS_EPT) 64 bytes
1321 #define AT91C_EPT_SIZE_128 (0x4) // (UDPHS_EPT) 128 bytes
1322 #define AT91C_EPT_SIZE_256 (0x5) // (UDPHS_EPT) 256 bytes
1323 #define AT91C_EPT_SIZE_512 (0x6) // (UDPHS_EPT) 512 bytes
1324 #define AT91C_EPT_SIZE_1024 (0x7) // (UDPHS_EPT) 1024 bytes
1325 #define AT91C_EPT_DIR (0x1 << 3) // (UDPHS_EPT) Endpoint Direction 0:OUT, 1:IN
1326 #define AT91C_EPT_DIR_OUT (0x0 << 3) // (UDPHS_EPT) Direction OUT
1327 #define AT91C_EPT_DIR_IN (0x1 << 3) // (UDPHS_EPT) Direction IN
1328 #define AT91C_EPT_TYPE (0x1 << 4) // (UDPHS_EPT) Endpoint Type
1329 #define AT91C_EPT_TYPE_CTL_EPT (0x0 << 4) // (UDPHS_EPT) Control endpoint
1330 #define AT91C_EPT_TYPE_ISO_EPT (0x1 << 4) // (UDPHS_EPT) Isochronous endpoint
1331 #define AT91C_EPT_TYPE_BUL_EPT (0x2 << 4) // (UDPHS_EPT) Bulk endpoint
1332 #define AT91C_EPT_TYPE_INT_EPT (0x3 << 4) // (UDPHS_EPT) Interrupt endpoint
1333 #define AT91C_BK_NUMBER (0x1 << 6) // (UDPHS_EPT) Number of Banks
1334 #define AT91C_BK_NUMBER_0 (0x0 << 6) // (UDPHS_EPT) Zero Bank, the EndPoint is not mapped in memory
1335 #define AT91C_BK_NUMBER_1 (0x1 << 6) // (UDPHS_EPT) One Bank (Bank0)
1336 #define AT91C_BK_NUMBER_2 (0x2 << 6) // (UDPHS_EPT) Double bank (Ping-Pong : Bank0 / Bank1)
1337 #define AT91C_BK_NUMBER_3 (0x3 << 6) // (UDPHS_EPT) Triple Bank (Bank0 / Bank1 / Bank2)
1338 #define AT91C_NB_TRANS (0x1 << 8) // (UDPHS_EPT) Number Of Transaction per Micro-Frame (High-Bandwidth iso only)
1339 #define AT91C_EPT_MAPPED (0x1 << 31) // (UDPHS_EPT) Endpoint Mapped (read only
1340 // -------- UDPHS_EPTCTLENB : (UDPHS_EPT Offset: 0x4) Endpoint Control Enable Register --------
1341 #define AT91C_EPT_ENABLE (0x1 << 0) // (UDPHS_EPT) Endpoint Enable
1342 #define AT91C_AUTO_VALID (0x1 << 1) // (UDPHS_EPT) Packet Auto-Valid Enable/Disable
1343 #define AT91C_INT_DIS_DMA (0x1 << 3) // (UDPHS_EPT) Endpoint Interrupts DMA Request Enable/Disable
1344 #define AT91C_NYET_DIS (0x1 << 4) // (UDPHS_EPT) NO NYET Enable/Disable
1345 #define AT91C_DATAX_RX (0x1 << 6) // (UDPHS_EPT) DATAx Interrupt Enable/Disable
1346 #define AT91C_MDATA_RX (0x1 << 7) // (UDPHS_EPT) MDATA Interrupt Enabled/Disable
1347 #define AT91C_OVERFLOW_ERROR (0x1 << 8) // (UDPHS_EPT) OverFlow Error Interrupt Enable/Disable/Status
1348 #define AT91C_RX_BK_RDY (0x1 << 9) // (UDPHS_EPT) Received OUT Data Interrupt Enable/Clear/Disable
1349 #define AT91C_TX_COMPLETE (0x1 << 10) // (UDPHS_EPT) Transmitted IN Data Complete Interrupt Enable/Disable or Transmitted IN Data Complete (clear)
1350 #define AT91C_TX_BK_RDY_ERROR_TRANS (0x1 << 11) // (UDPHS_EPT) TX Packet Ready / Transaction Error / Interrupt Enable/Disable
1351 #define AT91C_RX_SETUP_ERROR_FLOW_ISO (0x1 << 12) // (UDPHS_EPT) Received SETUP / Error Flow Clear/Interrupt Enable/Disable
1352 #define AT91C_STALL_SENT_ERROR_CRC_ISO (0x1 << 13) // (UDPHS_EPT) Stall Sent / CRC error / Interrupt Enable/Disable
1353 #define AT91C_NAK_IN (0x1 << 14) // (UDPHS_EPT) NAKIN / Clear / Interrupt Enable/Disable
1354 #define AT91C_NAK_OUT (0x1 << 15) // (UDPHS_EPT) NAKOUT / Clear / Interrupt Enable/Disable
1355 #define AT91C_BUSY_BANK (0x1 << 18) // (UDPHS_EPT) Busy Bank Interrupt Enable/Disable
1356 #define AT91C_SHORT_PACKET (0x1 << 31) // (UDPHS_EPT) Short Packet / Interrupt Enable/Disable
1357 // -------- UDPHS_EPTCTLDIS : (UDPHS_EPT Offset: 0x8) Endpoint Control Disable Register --------
1358 #define AT91C_EPT_DISABLE (0x1 << 0) // (UDPHS_EPT) Endpoint Disable
1359 // -------- UDPHS_EPTCTL : (UDPHS_EPT Offset: 0xc) Endpoint Control Register --------
1360 // -------- UDPHS_EPTSETSTA : (UDPHS_EPT Offset: 0x14) Endpoint Set Status Register --------
1361 #define AT91C_FORCE_STALL (0x1 << 5) // (UDPHS_EPT) Stall Handshake Request Set/Clear/Status
1362 #define AT91C_KILL_BANK (0x1 << 9) // (UDPHS_EPT) KILL Bank Set (For IN EndPoint)
1363 #define AT91C_TX_BK_RDY (0x1 << 11) // (UDPHS_EPT) TX Packet Ready Set
1364 // -------- UDPHS_EPTCLRSTA : (UDPHS_EPT Offset: 0x18) Endpoint Clear Status Register --------
1365 #define AT91C_TOGGLE_SEQ (0x1 << 6) // (UDPHS_EPT) Data Toggle Clear
1366 #define AT91C_STALL_SENT (0x1 << 13) // (UDPHS_EPT) Stall Sent Clear
1367 // -------- UDPHS_EPTSTA : (UDPHS_EPT Offset: 0x1c) Endpoint Status Register --------
1368 #define AT91C_TOGGLE_SEQ_STA (0x3 << 6) // (UDPHS_EPT) Toggle Sequencing
1369 #define AT91C_TOGGLE_SEQ_STA_00 (0x0 << 6) // (UDPHS_EPT) Data0
1370 #define AT91C_TOGGLE_SEQ_STA_01 (0x1 << 6) // (UDPHS_EPT) Data1
1371 #define AT91C_TOGGLE_SEQ_STA_10 (0x2 << 6) // (UDPHS_EPT) Data2 (only for High-Bandwidth Isochronous EndPoint)
1372 #define AT91C_TOGGLE_SEQ_STA_11 (0x3 << 6) // (UDPHS_EPT) MData (only for High-Bandwidth Isochronous EndPoint)
1373 #define AT91C_RX_BK_RDY_KILL_BANK (0x1 << 9) // (UDPHS_EPT) Received OUT Data / KILL Bank
1374 #define AT91C_CURRENT_BANK_CONTROL_DIR (0x3 << 16) // (UDPHS_EPT)
1375 #define AT91C_CURRENT_BANK_CONTROL_DIR_00 (0x0 << 16) // (UDPHS_EPT) Bank 0
1376 #define AT91C_CURRENT_BANK_CONTROL_DIR_01 (0x1 << 16) // (UDPHS_EPT) Bank 1
1377 #define AT91C_CURRENT_BANK_CONTROL_DIR_10 (0x2 << 16) // (UDPHS_EPT) Bank 2
1378 #define AT91C_CURRENT_BANK_CONTROL_DIR_11 (0x3 << 16) // (UDPHS_EPT) Invalid
1379 #define AT91C_BUSY_BANK_STA (0x3 << 18) // (UDPHS_EPT) Busy Bank Number
1380 #define AT91C_BUSY_BANK_STA_00 (0x0 << 18) // (UDPHS_EPT) All banks are free
1381 #define AT91C_BUSY_BANK_STA_01 (0x1 << 18) // (UDPHS_EPT) 1 busy bank
1382 #define AT91C_BUSY_BANK_STA_10 (0x2 << 18) // (UDPHS_EPT) 2 busy banks
1383 #define AT91C_BUSY_BANK_STA_11 (0x3 << 18) // (UDPHS_EPT) 3 busy banks
1384 #define AT91C_BYTE_COUNT (0x7FF << 20) // (UDPHS_EPT) USB Byte Count
1386 // *****************************************************************************
1387 // SOFTWARE API DEFINITION FOR USB DMA struct
1388 // *****************************************************************************
1389 // *** Register offset in AT91S_UDPHS_DMA structure ***
1390 #define UDPHS_DMANXTDSC ( 0) // DMA Channel Next Descriptor Address
1391 #define UDPHS_DMAADDRESS ( 4) // DMA Channel AHB1 Address Register
1392 #define UDPHS_DMACONTROL ( 8) // DMA Channel Control Register
1393 #define UDPHS_DMASTATUS (12) // DMA Channel Status Register
1394 // -------- UDPHS_DMANXTDSC : (UDPHS_DMA Offset: 0x0) Next Descriptor Address Register --------
1395 #define AT91C_NEXT_DESCRIPTOR_ADDRESS (0xFFFFFFF << 4) // (UDPHS_DMA) next Channel Descriptor
1396 // -------- UDPHS_DMAADDRESS : (UDPHS_DMA Offset: 0x4) DMA Channel AHB1 Address Register --------
1397 #define AT91C_BUFFER_AHB1_ADDRESS (0x0 << 0) // (UDPHS_DMA) starting address of a DMA Channel transfer
1398 // -------- UDPHS_DMACONTROL : (UDPHS_DMA Offset: 0x8) DMA Channel Control Register --------
1399 #define AT91C_CHANNEL_ENABLE (0x1 << 0) // (UDPHS_DMA) Channel Enable
1400 #define AT91C_LOAD_NEXT_CHANNEL_TRANSFER_DESCRIPTOR_ENABLE (0x1 << 1) // (UDPHS_DMA) Load Next Channel Transfer Descriptor Enable
1401 #define AT91C_BUFFER_CLOSE_INPUT_ENABLE (0x1 << 2) // (UDPHS_DMA) Buffer Close Input Enable
1402 #define AT91C_END_OF_DMA_BUFFER_OUTPUT_ENABLE (0x1 << 3) // (UDPHS_DMA) End of DMA Buffer Output Enable
1403 #define AT91C_UDPHS_END_OF_TRANSFER_INTERRUPT_ENABLE (0x1 << 4) // (UDPHS_DMA) USB End Of Transfer Interrupt Enable
1404 #define AT91C_END_OF_CHANNEL_BUFFER_INTERRUPT_ENABLE (0x1 << 5) // (UDPHS_DMA) End Of Channel Buffer Interrupt Enable
1405 #define AT91C_DESCRIPTOR_LOADED_INTERRUPT_ENABLE (0x1 << 6) // (UDPHS_DMA) Descriptor Loaded Interrupt Enable
1406 #define AT91C_BURST_LOCK_ENABLE (0x1 << 7) // (UDPHS_DMA) Burst Lock Enable
1407 #define AT91C_BUFFER_BYTE_LENGTH (0xFFFF << 16) // (UDPHS_DMA) Buffer Byte Length (write only)
1408 // -------- UDPHS_DMASTATUS : (UDPHS_DMA Offset: 0xc) DMA Channelx Status Register --------
1409 #define AT91C_CHANNEL_ENABLED (0x1 << 0) // (UDPHS_DMA) Channel Enabled
1410 #define AT91C_CHANNEL_ACTIVE (0x1 << 1) // (UDPHS_DMA)
1411 #define AT91C_UDPHS_END_OF_CHANNEL_TRANSFER_STATUS (0x1 << 4) // (UDPHS_DMA)
1412 #define AT91C_END_OF_CHANNEL_BUFFER_STATUS (0x1 << 5) // (UDPHS_DMA)
1413 #define AT91C_DESCRIPTOR_LOADED_STATUS (0x1 << 6) // (UDPHS_DMA)
1414 #define AT91C_BUFFER_BYTE_COUNT (0xFFFF << 16) // (UDPHS_DMA)
1416 // *****************************************************************************
1417 // SOFTWARE API DEFINITION FOR USB High Speed Device Interface
1418 // *****************************************************************************
1419 // *** Register offset in AT91S_UDPHS structure ***
1420 #define UDPHS_CTRL ( 0) // USB Control Register
1421 #define UDPHS_FNUM ( 4) // USB Frame Number Register
1422 #define UDPHS_IEN (16) // USB Interrupt Enable Register
1423 #define UDPHS_INTSTA (20) // USB Interrupt Status Register
1424 #define UDPHS_CLRINT (24) // USB Clear Interrupt Register
1425 #define UDPHS_EPTRST (28) // USB Endpoints Reset Register
1426 #define UDPHS_TSTCNTA (212) // USB Test CounterA Register
1427 #define UDPHS_TSTCNTB (216) // USB Test CounterB Register
1428 #define UDPHS_TST (224) // USB Test Register
1429 #define UDPHS_IPPADDRSIZE (236) // HUSB2DEV PADDRSIZE Register
1430 #define UDPHS_IPNAME1 (240) // HUSB2DEV Name1 Register
1431 #define UDPHS_IPNAME2 (244) // HUSB2DEV Name2 Register
1432 #define UDPHS_IPFEATURES (248) // HUSB2DEV Features Register
1433 #define UDPHS_IPVERSION (252) // HUSB2DEV Version Register
1434 #define UDPHS_EPT (256) // USB Endpoint struct
1435 #define UDPHS_DMA (768) // USB DMA channel struct (not use [0])
1436 // -------- UDPHS_CTRL : (UDPHS Offset: 0x0) USB Control Register --------
1437 #define AT91C_DEV_ADDR (0x7F << 0) // (UDPHS) USB Address
1438 #define AT91C_FADDR_EN (0x1 << 7) // (UDPHS) Function Address Enable
1439 #define AT91C_EN_USB (0x1 << 8) // (UDPHS) USB Enable
1440 #define AT91C_DETACH (0x1 << 9) // (UDPHS) Detach Command
1441 #define AT91C_REMOTE_WAKE_UP (0x1 << 10) // (UDPHS) Send Remote Wake Up
1442 #define AT91C_PULLDOWN_DIS (0x1 << 11) // (UDPHS) PullDown Disable
1443 // -------- UDPHS_FNUM : (UDPHS Offset: 0x4) USB Frame Number Register --------
1444 #define AT91C_MICRO_FRAME_NUM (0x7 << 0) // (UDPHS) Micro Frame Number
1445 #define AT91C_FRAME_NUMBER (0x7FF << 3) // (UDPHS) Frame Number as defined in the Packet Field Formats
1446 #define AT91C_FRAME_NUM_ERROR (0x1 << 31) // (UDPHS) Frame Number CRC Error
1447 // -------- UDPHS_IEN : (UDPHS Offset: 0x10) USB Interrupt Enable Register --------
1448 #define AT91C_DET_SUSPEND (0x1 << 1) // (UDPHS) Suspend Interrupt Enable/Clear/Status
1449 #define AT91C_MICRO_SOF (0x1 << 2) // (UDPHS) Micro-SOF Interrupt Enable/Clear/Status
1450 #define AT91C_IEN_SOF (0x1 << 3) // (UDPHS) SOF Interrupt Enable/Clear/Status
1451 #define AT91C_END_OF_RESET (0x1 << 4) // (UDPHS) End Of Reset Interrupt Enable/Clear/Status
1452 #define AT91C_WAKE_UP (0x1 << 5) // (UDPHS) Wake Up CPU Interrupt Enable/Clear/Status
1453 #define AT91C_END_OF_RESUME (0x1 << 6) // (UDPHS) End Of Resume Interrupt Enable/Clear/Status
1454 #define AT91C_UPSTREAM_RESUME (0x1 << 7) // (UDPHS) Upstream Resume Interrupt Enable/Clear/Status
1455 #define AT91C_EPT_INT_0 (0x1 << 8) // (UDPHS) Endpoint 0 Interrupt Enable/Status
1456 #define AT91C_EPT_INT_1 (0x1 << 9) // (UDPHS) Endpoint 1 Interrupt Enable/Status
1457 #define AT91C_EPT_INT_2 (0x1 << 10) // (UDPHS) Endpoint 2 Interrupt Enable/Status
1458 #define AT91C_EPT_INT_3 (0x1 << 11) // (UDPHS) Endpoint 3 Interrupt Enable/Status
1459 #define AT91C_EPT_INT_4 (0x1 << 12) // (UDPHS) Endpoint 4 Interrupt Enable/Status
1460 #define AT91C_EPT_INT_5 (0x1 << 13) // (UDPHS) Endpoint 5 Interrupt Enable/Status
1461 #define AT91C_EPT_INT_6 (0x1 << 14) // (UDPHS) Endpoint 6 Interrupt Enable/Status
1462 #define AT91C_EPT_INT_7 (0x1 << 15) // (UDPHS) Endpoint 7 Interrupt Enable/Status
1463 #define AT91C_EPT_INT_8 (0x1 << 16) // (UDPHS) Endpoint 8 Interrupt Enable/Status
1464 #define AT91C_EPT_INT_9 (0x1 << 17) // (UDPHS) Endpoint 9 Interrupt Enable/Status
1465 #define AT91C_EPT_INT_10 (0x1 << 18) // (UDPHS) Endpoint 10 Interrupt Enable/Status
1466 #define AT91C_EPT_INT_11 (0x1 << 19) // (UDPHS) Endpoint 11 Interrupt Enable/Status
1467 #define AT91C_EPT_INT_12 (0x1 << 20) // (UDPHS) Endpoint 12 Interrupt Enable/Status
1468 #define AT91C_EPT_INT_13 (0x1 << 21) // (UDPHS) Endpoint 13 Interrupt Enable/Status
1469 #define AT91C_EPT_INT_14 (0x1 << 22) // (UDPHS) Endpoint 14 Interrupt Enable/Status
1470 #define AT91C_EPT_INT_15 (0x1 << 23) // (UDPHS) Endpoint 15 Interrupt Enable/Status
1471 #define AT91C_DMA_INT_1 (0x1 << 25) // (UDPHS) DMA Channel 1 Interrupt Enable/Status
1472 #define AT91C_DMA_INT_2 (0x1 << 26) // (UDPHS) DMA Channel 2 Interrupt Enable/Status
1473 #define AT91C_DMA_INT_3 (0x1 << 27) // (UDPHS) DMA Channel 3 Interrupt Enable/Status
1474 #define AT91C_DMA_INT_4 (0x1 << 28) // (UDPHS) DMA Channel 4 Interrupt Enable/Status
1475 #define AT91C_DMA_INT_5 (0x1 << 29) // (UDPHS) DMA Channel 5 Interrupt Enable/Status
1476 #define AT91C_DMA_INT_6 (0x1 << 30) // (UDPHS) DMA Channel 6 Interrupt Enable/Status
1477 #define AT91C_DMA_INT_7 (0x1 << 31) // (UDPHS) DMA Channel 7 Interrupt Enable/Status
1478 // -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) USB Interrupt Status Register --------
1479 #define AT91C_SPEED (0x1 << 0) // (UDPHS) Speed Status
1480 // -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) --------
1481 // -------- UDPHS_EPTRST : (UDPHS Offset: 0x1c) USB Endpoints Reset Register --------
1482 #define AT91C_RESET_EPT_0 (0x1 << 0) // (UDPHS) Endpoint Reset 0
1483 #define AT91C_RESET_EPT_1 (0x1 << 1) // (UDPHS) Endpoint Reset 1
1484 #define AT91C_RESET_EPT_2 (0x1 << 2) // (UDPHS) Endpoint Reset 2
1485 #define AT91C_RESET_EPT_3 (0x1 << 3) // (UDPHS) Endpoint Reset 3
1486 #define AT91C_RESET_EPT_4 (0x1 << 4) // (UDPHS) Endpoint Reset 4
1487 #define AT91C_RESET_EPT_5 (0x1 << 5) // (UDPHS) Endpoint Reset 5
1488 #define AT91C_RESET_EPT_6 (0x1 << 6) // (UDPHS) Endpoint Reset 6
1489 #define AT91C_RESET_EPT_7 (0x1 << 7) // (UDPHS) Endpoint Reset 7
1490 #define AT91C_RESET_EPT_8 (0x1 << 8) // (UDPHS) Endpoint Reset 8
1491 #define AT91C_RESET_EPT_9 (0x1 << 9) // (UDPHS) Endpoint Reset 9
1492 #define AT91C_RESET_EPT_10 (0x1 << 10) // (UDPHS) Endpoint Reset 10
1493 #define AT91C_RESET_EPT_11 (0x1 << 11) // (UDPHS) Endpoint Reset 11
1494 #define AT91C_RESET_EPT_12 (0x1 << 12) // (UDPHS) Endpoint Reset 12
1495 #define AT91C_RESET_EPT_13 (0x1 << 13) // (UDPHS) Endpoint Reset 13
1496 #define AT91C_RESET_EPT_14 (0x1 << 14) // (UDPHS) Endpoint Reset 14
1497 #define AT91C_RESET_EPT_15 (0x1 << 15) // (UDPHS) Endpoint Reset 15
1498 // -------- UDPHS_TST : (UDPHS Offset: 0xe0) USB Test Register --------
1499 #define AT91C_SPEED_CFG (0x3 << 0) // (UDPHS) Speed Configuration
1500 #define AT91C_SPEED_CFG_NM (0x0) // (UDPHS) Normal Mode
1501 #define AT91C_SPEED_CFG_RS (0x1) // (UDPHS) Reserved
1502 #define AT91C_SPEED_CFG_HS (0x2) // (UDPHS) Force High Speed
1503 #define AT91C_SPEED_CFG_FS (0x3) // (UDPHS) Force Full-Speed
1504 #define AT91C_TST_J_MODE (0x1 << 2) // (UDPHS) TestJMode
1505 #define AT91C_TST_K_MODE (0x1 << 3) // (UDPHS) TestKMode
1506 #define AT91C_TST_PKT_MODE (0x1 << 4) // (UDPHS) TestPacketMode
1507 #define AT91C_OPMODE2 (0x1 << 5) // (UDPHS) OpMode2
1508 // -------- UDPHS_IPPADDRSIZE : (UDPHS Offset: 0xec) HUSB2DEV PADDRSIZE Register --------
1509 #define AT91C_IPPADDRSIZE (0x0 << 0) // (UDPHS) 2^HUSB2DEV_PADDR_SIZE
1510 // -------- UDPHS_IPNAME1 : (UDPHS Offset: 0xf0) HUSB2DEV Name Register --------
1511 #define AT91C_IPNAME1 (0x0 << 0) // (UDPHS) ASCII string HUSB
1512 // -------- UDPHS_IPNAME2 : (UDPHS Offset: 0xf4) HUSB2DEV Name Register --------
1513 #define AT91C_IPNAME2 (0x0 << 0) // (UDPHS) ASCII string 2DEV
1514 // -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xf8) HUSB2DEV Features Register --------
1515 #define AT91C_EPT_NBR_MAX (0xF << 0) // (UDPHS) Max Number of Endpoints
1516 #define AT91C_DMA_CHANNEL_NBR (0x7 << 4) // (UDPHS) Number of DMA Channels
1517 #define AT91C_DMA_BUFFER_SIZE (0x1 << 7) // (UDPHS) DMA Buffer Size
1518 #define AT91C_DMA_FIFO_WORD_DEPTH (0xF << 8) // (UDPHS) DMA FIFO Depth in words
1519 #define AT91C_FIFO_MAX_SIZE (0x7 << 12) // (UDPHS) DPRAM size
1520 #define AT91C_BYTE_WRITE_DPRAM (0x1 << 15) // (UDPHS) DPRAM byte write capability
1521 #define AT91C_DATA_BUS_16_8 (0x1 << 16) // (UDPHS) UTMI DataBus16_8
1522 #define AT91C_EN_HIGH_BD_ISO_EPT_1 (0x1 << 17) // (UDPHS) Endpoint 1 High Bandwidth Isochronous Capability
1523 #define AT91C_EN_HIGH_BD_ISO_EPT_2 (0x1 << 18) // (UDPHS) Endpoint 2 High Bandwidth Isochronous Capability
1524 #define AT91C_EN_HIGH_BD_ISO_EPT_3 (0x1 << 19) // (UDPHS) Endpoint 3 High Bandwidth Isochronous Capability
1525 #define AT91C_EN_HIGH_BD_ISO_EPT_4 (0x1 << 20) // (UDPHS) Endpoint 4 High Bandwidth Isochronous Capability
1526 #define AT91C_EN_HIGH_BD_ISO_EPT_5 (0x1 << 21) // (UDPHS) Endpoint 5 High Bandwidth Isochronous Capability
1527 #define AT91C_EN_HIGH_BD_ISO_EPT_6 (0x1 << 22) // (UDPHS) Endpoint 6 High Bandwidth Isochronous Capability
1528 #define AT91C_EN_HIGH_BD_ISO_EPT_7 (0x1 << 23) // (UDPHS) Endpoint 7 High Bandwidth Isochronous Capability
1529 #define AT91C_EN_HIGH_BD_ISO_EPT_8 (0x1 << 24) // (UDPHS) Endpoint 8 High Bandwidth Isochronous Capability
1530 #define AT91C_EN_HIGH_BD_ISO_EPT_9 (0x1 << 25) // (UDPHS) Endpoint 9 High Bandwidth Isochronous Capability
1531 #define AT91C_EN_HIGH_BD_ISO_EPT_10 (0x1 << 26) // (UDPHS) Endpoint 10 High Bandwidth Isochronous Capability
1532 #define AT91C_EN_HIGH_BD_ISO_EPT_11 (0x1 << 27) // (UDPHS) Endpoint 11 High Bandwidth Isochronous Capability
1533 #define AT91C_EN_HIGH_BD_ISO_EPT_12 (0x1 << 28) // (UDPHS) Endpoint 12 High Bandwidth Isochronous Capability
1534 #define AT91C_EN_HIGH_BD_ISO_EPT_13 (0x1 << 29) // (UDPHS) Endpoint 13 High Bandwidth Isochronous Capability
1535 #define AT91C_EN_HIGH_BD_ISO_EPT_14 (0x1 << 30) // (UDPHS) Endpoint 14 High Bandwidth Isochronous Capability
1536 #define AT91C_EN_HIGH_BD_ISO_EPT_15 (0x1 << 31) // (UDPHS) Endpoint 15 High Bandwidth Isochronous Capability
1537 // -------- UDPHS_IPVERSION : (UDPHS Offset: 0xfc) HUSB2DEV Version Register --------
1538 #define AT91C_VERSION_NUM (0xFFFF << 0) // (UDPHS) Give the IP version
1539 #define AT91C_METAL_FIX_NUM (0x7 << 16) // (UDPHS) Give the number of metal fixes
1541 // *****************************************************************************
1542 // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
1543 // *****************************************************************************
1544 // *** Register offset in AT91S_TC structure ***
1545 #define TC_CCR ( 0) // Channel Control Register
1546 #define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
1547 #define TC_CV (16) // Counter Value
1548 #define TC_RA (20) // Register A
1549 #define TC_RB (24) // Register B
1550 #define TC_RC (28) // Register C
1551 #define TC_SR (32) // Status Register
1552 #define TC_IER (36) // Interrupt Enable Register
1553 #define TC_IDR (40) // Interrupt Disable Register
1554 #define TC_IMR (44) // Interrupt Mask Register
1555 // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
1556 #define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
1557 #define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
1558 #define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
1559 // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
1560 #define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
1561 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
1562 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
1563 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
1564 #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
1565 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
1566 #define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
1567 #define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
1568 #define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
1569 #define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
1570 #define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
1571 #define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
1572 #define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
1573 #define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
1574 #define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
1575 #define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
1576 #define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
1577 #define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
1578 #define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
1579 #define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
1580 #define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
1581 #define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
1582 #define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
1583 #define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
1584 #define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
1585 #define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
1586 #define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
1587 #define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
1588 #define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
1589 #define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
1590 #define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
1591 #define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
1592 #define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
1593 #define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
1594 #define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
1595 #define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
1596 #define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
1597 #define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
1598 #define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
1599 #define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
1600 #define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
1601 #define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
1602 #define AT91C_TC_WAVE (0x1 << 15) // (TC)
1603 #define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
1604 #define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
1605 #define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
1606 #define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
1607 #define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
1608 #define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
1609 #define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
1610 #define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
1611 #define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
1612 #define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
1613 #define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
1614 #define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
1615 #define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
1616 #define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
1617 #define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
1618 #define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
1619 #define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
1620 #define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
1621 #define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
1622 #define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
1623 #define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
1624 #define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
1625 #define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
1626 #define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
1627 #define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
1628 #define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
1629 #define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
1630 #define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
1631 #define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
1632 #define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
1633 #define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
1634 #define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
1635 #define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
1636 #define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
1637 #define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
1638 #define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
1639 #define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
1640 #define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
1641 #define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
1642 #define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
1643 #define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
1644 #define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
1645 #define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
1646 #define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
1647 #define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
1648 #define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
1649 #define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
1650 #define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
1651 #define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
1652 #define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
1653 // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
1654 #define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
1655 #define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
1656 #define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
1657 #define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
1658 #define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
1659 #define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
1660 #define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
1661 #define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
1662 #define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
1663 #define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
1664 #define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
1665 // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
1666 // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
1667 // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
1669 // *****************************************************************************
1670 // SOFTWARE API DEFINITION FOR Timer Counter Interface
1671 // *****************************************************************************
1672 // *** Register offset in AT91S_TCB structure ***
1673 #define TCB_TC0 ( 0) // TC Channel 0
1674 #define TCB_TC1 (64) // TC Channel 1
1675 #define TCB_TC2 (128) // TC Channel 2
1676 #define TCB_BCR (192) // TC Block Control Register
1677 #define TCB_BMR (196) // TC Block Mode Register
1678 // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
1679 #define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
1680 // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
1681 #define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
1682 #define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
1683 #define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
1684 #define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
1685 #define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
1686 #define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
1687 #define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
1688 #define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
1689 #define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
1690 #define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
1691 #define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
1692 #define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
1693 #define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
1694 #define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
1695 #define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
1697 // *****************************************************************************
1698 // SOFTWARE API DEFINITION FOR Multimedia Card Interface
1699 // *****************************************************************************
1700 // *** Register offset in AT91S_MCI structure ***
1701 #define MCI_CR ( 0) // MCI Control Register
1702 #define MCI_MR ( 4) // MCI Mode Register
1703 #define MCI_DTOR ( 8) // MCI Data Timeout Register
1704 #define MCI_SDCR (12) // MCI SD Card Register
1705 #define MCI_ARGR (16) // MCI Argument Register
1706 #define MCI_CMDR (20) // MCI Command Register
1707 #define MCI_BLKR (24) // MCI Block Register
1708 #define MCI_RSPR (32) // MCI Response Register
1709 #define MCI_RDR (48) // MCI Receive Data Register
1710 #define MCI_TDR (52) // MCI Transmit Data Register
1711 #define MCI_SR (64) // MCI Status Register
1712 #define MCI_IER (68) // MCI Interrupt Enable Register
1713 #define MCI_IDR (72) // MCI Interrupt Disable Register
1714 #define MCI_IMR (76) // MCI Interrupt Mask Register
1715 #define MCI_VR (252) // MCI Version Register
1716 #define MCI_RPR (256) // Receive Pointer Register
1717 #define MCI_RCR (260) // Receive Counter Register
1718 #define MCI_TPR (264) // Transmit Pointer Register
1719 #define MCI_TCR (268) // Transmit Counter Register
1720 #define MCI_RNPR (272) // Receive Next Pointer Register
1721 #define MCI_RNCR (276) // Receive Next Counter Register
1722 #define MCI_TNPR (280) // Transmit Next Pointer Register
1723 #define MCI_TNCR (284) // Transmit Next Counter Register
1724 #define MCI_PTCR (288) // PDC Transfer Control Register
1725 #define MCI_PTSR (292) // PDC Transfer Status Register
1726 // -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
1727 #define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable
1728 #define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable
1729 #define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable
1730 #define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable
1731 #define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset
1732 // -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
1733 #define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider
1734 #define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider
1735 #define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable
1736 #define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable
1737 #define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer
1738 #define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value
1739 #define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode
1740 #define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length
1741 // -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
1742 #define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number
1743 #define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier
1744 #define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1
1745 #define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16
1746 #define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128
1747 #define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256
1748 #define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024
1749 #define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096
1750 #define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536
1751 #define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576
1752 // -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
1753 #define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector
1754 #define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width
1755 // -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
1756 #define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number
1757 #define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type
1758 #define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response
1759 #define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response
1760 #define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response
1761 #define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD
1762 #define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD
1763 #define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD
1764 #define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD
1765 #define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command
1766 #define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response
1767 #define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command
1768 #define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond
1769 #define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD
1770 #define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer
1771 #define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer
1772 #define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer
1773 #define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction
1774 #define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type
1775 #define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
1776 #define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
1777 #define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type
1778 #define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type
1779 #define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type
1780 #define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command
1781 #define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command
1782 #define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command
1783 #define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command
1784 // -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register --------
1785 #define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
1786 // -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
1787 #define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag
1788 #define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag
1789 #define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag
1790 #define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag
1791 #define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag
1792 #define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag
1793 #define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag
1794 #define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag
1795 #define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A
1796 #define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B
1797 #define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
1798 #define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
1799 #define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag
1800 #define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag
1801 #define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag
1802 #define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag
1803 #define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag
1804 #define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag
1805 #define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag
1806 #define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag
1807 #define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag
1808 #define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag
1809 #define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag
1810 // -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
1811 // -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
1812 // -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------
1814 // *****************************************************************************
1815 // SOFTWARE API DEFINITION FOR Two-wire Interface
1816 // *****************************************************************************
1817 // *** Register offset in AT91S_TWI structure ***
1818 #define TWI_CR ( 0) // Control Register
1819 #define TWI_MMR ( 4) // Master Mode Register
1820 #define TWI_SMR ( 8) // Slave Mode Register
1821 #define TWI_IADR (12) // Internal Address Register
1822 #define TWI_CWGR (16) // Clock Waveform Generator Register
1823 #define TWI_SR (32) // Status Register
1824 #define TWI_IER (36) // Interrupt Enable Register
1825 #define TWI_IDR (40) // Interrupt Disable Register
1826 #define TWI_IMR (44) // Interrupt Mask Register
1827 #define TWI_RHR (48) // Receive Holding Register
1828 #define TWI_THR (52) // Transmit Holding Register
1829 #define TWI_RPR (256) // Receive Pointer Register
1830 #define TWI_RCR (260) // Receive Counter Register
1831 #define TWI_TPR (264) // Transmit Pointer Register
1832 #define TWI_TCR (268) // Transmit Counter Register
1833 #define TWI_RNPR (272) // Receive Next Pointer Register
1834 #define TWI_RNCR (276) // Receive Next Counter Register
1835 #define TWI_TNPR (280) // Transmit Next Pointer Register
1836 #define TWI_TNCR (284) // Transmit Next Counter Register
1837 #define TWI_PTCR (288) // PDC Transfer Control Register
1838 #define TWI_PTSR (292) // PDC Transfer Status Register
1839 // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
1840 #define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
1841 #define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
1842 #define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
1843 #define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
1844 #define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled
1845 #define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled
1846 #define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
1847 // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
1848 #define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
1849 #define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
1850 #define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
1851 #define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
1852 #define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
1853 #define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
1854 #define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
1855 // -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
1856 #define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address
1857 // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
1858 #define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
1859 #define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
1860 #define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
1861 // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
1862 #define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed
1863 #define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed
1864 #define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
1865 #define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY
1866 #define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY
1867 #define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode)
1868 #define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode)
1869 #define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode)
1870 #define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
1871 #define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged
1872 #define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged
1873 #define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode)
1874 #define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
1875 #define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
1876 #define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer
1877 #define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer
1878 #define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt
1879 #define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt
1880 // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
1881 // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
1882 // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
1884 // *****************************************************************************
1885 // SOFTWARE API DEFINITION FOR Usart
1886 // *****************************************************************************
1887 // *** Register offset in AT91S_USART structure ***
1888 #define US_CR ( 0) // Control Register
1889 #define US_MR ( 4) // Mode Register
1890 #define US_IER ( 8) // Interrupt Enable Register
1891 #define US_IDR (12) // Interrupt Disable Register
1892 #define US_IMR (16) // Interrupt Mask Register
1893 #define US_CSR (20) // Channel Status Register
1894 #define US_RHR (24) // Receiver Holding Register
1895 #define US_THR (28) // Transmitter Holding Register
1896 #define US_BRGR (32) // Baud Rate Generator Register
1897 #define US_RTOR (36) // Receiver Time-out Register
1898 #define US_TTGR (40) // Transmitter Time-guard Register
1899 #define US_FIDI (64) // FI_DI_Ratio Register
1900 #define US_NER (68) // Nb Errors Register
1901 #define US_IF (76) // IRDA_FILTER Register
1902 #define US_RPR (256) // Receive Pointer Register
1903 #define US_RCR (260) // Receive Counter Register
1904 #define US_TPR (264) // Transmit Pointer Register
1905 #define US_TCR (268) // Transmit Counter Register
1906 #define US_RNPR (272) // Receive Next Pointer Register
1907 #define US_RNCR (276) // Receive Next Counter Register
1908 #define US_TNPR (280) // Transmit Next Pointer Register
1909 #define US_TNCR (284) // Transmit Next Counter Register
1910 #define US_PTCR (288) // PDC Transfer Control Register
1911 #define US_PTSR (292) // PDC Transfer Status Register
1912 // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
1913 #define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
1914 #define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
1915 #define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
1916 #define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
1917 #define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
1918 #define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
1919 #define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
1920 #define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
1921 #define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
1922 #define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
1923 #define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
1924 // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
1925 #define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
1926 #define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
1927 #define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
1928 #define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
1929 #define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
1930 #define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
1931 #define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
1932 #define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
1933 #define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
1934 #define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
1935 #define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
1936 #define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
1937 #define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
1938 #define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
1939 #define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
1940 #define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
1941 #define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
1942 #define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
1943 #define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
1944 #define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
1945 #define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
1946 #define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
1947 #define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
1948 #define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
1949 #define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
1950 #define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
1951 #define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
1952 #define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
1953 #define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
1954 #define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
1955 #define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
1956 #define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
1957 // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
1958 #define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
1959 #define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
1960 #define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
1961 #define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
1962 #define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
1963 #define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
1964 #define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
1965 #define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
1966 // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
1967 // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
1968 // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
1969 #define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
1970 #define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
1971 #define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
1972 #define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
1974 // *****************************************************************************
1975 // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
1976 // *****************************************************************************
1977 // *** Register offset in AT91S_SSC structure ***
1978 #define SSC_CR ( 0) // Control Register
1979 #define SSC_CMR ( 4) // Clock Mode Register
1980 #define SSC_RCMR (16) // Receive Clock ModeRegister
1981 #define SSC_RFMR (20) // Receive Frame Mode Register
1982 #define SSC_TCMR (24) // Transmit Clock Mode Register
1983 #define SSC_TFMR (28) // Transmit Frame Mode Register
1984 #define SSC_RHR (32) // Receive Holding Register
1985 #define SSC_THR (36) // Transmit Holding Register
1986 #define SSC_RSHR (48) // Receive Sync Holding Register
1987 #define SSC_TSHR (52) // Transmit Sync Holding Register
1988 #define SSC_SR (64) // Status Register
1989 #define SSC_IER (68) // Interrupt Enable Register
1990 #define SSC_IDR (72) // Interrupt Disable Register
1991 #define SSC_IMR (76) // Interrupt Mask Register
1992 #define SSC_RPR (256) // Receive Pointer Register
1993 #define SSC_RCR (260) // Receive Counter Register
1994 #define SSC_TPR (264) // Transmit Pointer Register
1995 #define SSC_TCR (268) // Transmit Counter Register
1996 #define SSC_RNPR (272) // Receive Next Pointer Register
1997 #define SSC_RNCR (276) // Receive Next Counter Register
1998 #define SSC_TNPR (280) // Transmit Next Pointer Register
1999 #define SSC_TNCR (284) // Transmit Next Counter Register
2000 #define SSC_PTCR (288) // PDC Transfer Control Register
2001 #define SSC_PTSR (292) // PDC Transfer Status Register
2002 // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
2003 #define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
2004 #define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
2005 #define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
2006 #define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
2007 #define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
2008 // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
2009 #define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
2010 #define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
2011 #define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
2012 #define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
2013 #define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
2014 #define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
2015 #define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
2016 #define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
2017 #define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
2018 #define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
2019 #define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
2020 #define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
2021 #define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
2022 #define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
2023 #define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
2024 #define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
2025 #define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
2026 #define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
2027 #define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
2028 #define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
2029 #define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
2030 // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
2031 #define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
2032 #define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
2033 #define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
2034 #define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
2035 #define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
2036 #define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
2037 #define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
2038 #define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
2039 #define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
2040 #define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
2041 #define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
2042 #define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
2043 #define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
2044 // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
2045 // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
2046 #define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
2047 #define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
2048 // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
2049 #define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
2050 #define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
2051 #define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
2052 #define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
2053 #define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
2054 #define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
2055 #define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
2056 #define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
2057 #define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
2058 #define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
2059 #define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
2060 #define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
2061 // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
2062 // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
2063 // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
2065 // *****************************************************************************
2066 // SOFTWARE API DEFINITION FOR AC97 Controller Interface
2067 // *****************************************************************************
2068 // *** Register offset in AT91S_AC97C structure ***
2069 #define AC97C_MR ( 8) // Mode Register
2070 #define AC97C_ICA (16) // Input Channel AssignementRegister
2071 #define AC97C_OCA (20) // Output Channel Assignement Register
2072 #define AC97C_CARHR (32) // Channel A Receive Holding Register
2073 #define AC97C_CATHR (36) // Channel A Transmit Holding Register
2074 #define AC97C_CASR (40) // Channel A Status Register
2075 #define AC97C_CAMR (44) // Channel A Mode Register
2076 #define AC97C_CBRHR (48) // Channel B Receive Holding Register (optional)
2077 #define AC97C_CBTHR (52) // Channel B Transmit Holding Register (optional)
2078 #define AC97C_CBSR (56) // Channel B Status Register
2079 #define AC97C_CBMR (60) // Channel B Mode Register
2080 #define AC97C_CORHR (64) // COdec Transmit Holding Register
2081 #define AC97C_COTHR (68) // COdec Transmit Holding Register
2082 #define AC97C_COSR (72) // CODEC Status Register
2083 #define AC97C_COMR (76) // CODEC Mask Status Register
2084 #define AC97C_SR (80) // Status Register
2085 #define AC97C_IER (84) // Interrupt Enable Register
2086 #define AC97C_IDR (88) // Interrupt Disable Register
2087 #define AC97C_IMR (92) // Interrupt Mask Register
2088 #define AC97C_VERSION (252) // Version Register
2089 #define AC97C_RPR (256) // Receive Pointer Register
2090 #define AC97C_RCR (260) // Receive Counter Register
2091 #define AC97C_TPR (264) // Transmit Pointer Register
2092 #define AC97C_TCR (268) // Transmit Counter Register
2093 #define AC97C_RNPR (272) // Receive Next Pointer Register
2094 #define AC97C_RNCR (276) // Receive Next Counter Register
2095 #define AC97C_TNPR (280) // Transmit Next Pointer Register
2096 #define AC97C_TNCR (284) // Transmit Next Counter Register
2097 #define AC97C_PTCR (288) // PDC Transfer Control Register
2098 #define AC97C_PTSR (292) // PDC Transfer Status Register
2099 // -------- AC97C_MR : (AC97C Offset: 0x8) AC97C Mode Register --------
2100 #define AT91C_AC97C_ENA (0x1 << 0) // (AC97C) AC97 Controller Global Enable
2101 #define AT91C_AC97C_WRST (0x1 << 1) // (AC97C) Warm Reset
2102 #define AT91C_AC97C_VRA (0x1 << 2) // (AC97C) Variable RAte (for Data Slots)
2103 // -------- AC97C_ICA : (AC97C Offset: 0x10) AC97C Input Channel Assignement Register --------
2104 #define AT91C_AC97C_CHID3 (0x7 << 0) // (AC97C) Channel Id for the input slot 3
2105 #define AT91C_AC97C_CHID3_NONE (0x0) // (AC97C) No data will be transmitted during this slot
2106 #define AT91C_AC97C_CHID3_CA (0x1) // (AC97C) Channel A data will be transmitted during this slot
2107 #define AT91C_AC97C_CHID3_CB (0x2) // (AC97C) Channel B data will be transmitted during this slot
2108 #define AT91C_AC97C_CHID3_CC (0x3) // (AC97C) Channel C data will be transmitted during this slot
2109 #define AT91C_AC97C_CHID4 (0x7 << 3) // (AC97C) Channel Id for the input slot 4
2110 #define AT91C_AC97C_CHID4_NONE (0x0 << 3) // (AC97C) No data will be transmitted during this slot
2111 #define AT91C_AC97C_CHID4_CA (0x1 << 3) // (AC97C) Channel A data will be transmitted during this slot
2112 #define AT91C_AC97C_CHID4_CB (0x2 << 3) // (AC97C) Channel B data will be transmitted during this slot
2113 #define AT91C_AC97C_CHID4_CC (0x3 << 3) // (AC97C) Channel C data will be transmitted during this slot
2114 #define AT91C_AC97C_CHID5 (0x7 << 6) // (AC97C) Channel Id for the input slot 5
2115 #define AT91C_AC97C_CHID5_NONE (0x0 << 6) // (AC97C) No data will be transmitted during this slot
2116 #define AT91C_AC97C_CHID5_CA (0x1 << 6) // (AC97C) Channel A data will be transmitted during this slot
2117 #define AT91C_AC97C_CHID5_CB (0x2 << 6) // (AC97C) Channel B data will be transmitted during this slot
2118 #define AT91C_AC97C_CHID5_CC (0x3 << 6) // (AC97C) Channel C data will be transmitted during this slot
2119 #define AT91C_AC97C_CHID6 (0x7 << 9) // (AC97C) Channel Id for the input slot 6
2120 #define AT91C_AC97C_CHID6_NONE (0x0 << 9) // (AC97C) No data will be transmitted during this slot
2121 #define AT91C_AC97C_CHID6_CA (0x1 << 9) // (AC97C) Channel A data will be transmitted during this slot
2122 #define AT91C_AC97C_CHID6_CB (0x2 << 9) // (AC97C) Channel B data will be transmitted during this slot
2123 #define AT91C_AC97C_CHID6_CC (0x3 << 9) // (AC97C) Channel C data will be transmitted during this slot
2124 #define AT91C_AC97C_CHID7 (0x7 << 12) // (AC97C) Channel Id for the input slot 7
2125 #define AT91C_AC97C_CHID7_NONE (0x0 << 12) // (AC97C) No data will be transmitted during this slot
2126 #define AT91C_AC97C_CHID7_CA (0x1 << 12) // (AC97C) Channel A data will be transmitted during this slot
2127 #define AT91C_AC97C_CHID7_CB (0x2 << 12) // (AC97C) Channel B data will be transmitted during this slot
2128 #define AT91C_AC97C_CHID7_CC (0x3 << 12) // (AC97C) Channel C data will be transmitted during this slot
2129 #define AT91C_AC97C_CHID8 (0x7 << 15) // (AC97C) Channel Id for the input slot 8
2130 #define AT91C_AC97C_CHID8_NONE (0x0 << 15) // (AC97C) No data will be transmitted during this slot
2131 #define AT91C_AC97C_CHID8_CA (0x1 << 15) // (AC97C) Channel A data will be transmitted during this slot
2132 #define AT91C_AC97C_CHID8_CB (0x2 << 15) // (AC97C) Channel B data will be transmitted during this slot
2133 #define AT91C_AC97C_CHID8_CC (0x3 << 15) // (AC97C) Channel C data will be transmitted during this slot
2134 #define AT91C_AC97C_CHID9 (0x7 << 18) // (AC97C) Channel Id for the input slot 9
2135 #define AT91C_AC97C_CHID9_NONE (0x0 << 18) // (AC97C) No data will be transmitted during this slot
2136 #define AT91C_AC97C_CHID9_CA (0x1 << 18) // (AC97C) Channel A data will be transmitted during this slot
2137 #define AT91C_AC97C_CHID9_CB (0x2 << 18) // (AC97C) Channel B data will be transmitted during this slot
2138 #define AT91C_AC97C_CHID9_CC (0x3 << 18) // (AC97C) Channel C data will be transmitted during this slot
2139 #define AT91C_AC97C_CHID10 (0x7 << 21) // (AC97C) Channel Id for the input slot 10
2140 #define AT91C_AC97C_CHID10_NONE (0x0 << 21) // (AC97C) No data will be transmitted during this slot
2141 #define AT91C_AC97C_CHID10_CA (0x1 << 21) // (AC97C) Channel A data will be transmitted during this slot
2142 #define AT91C_AC97C_CHID10_CB (0x2 << 21) // (AC97C) Channel B data will be transmitted during this slot
2143 #define AT91C_AC97C_CHID10_CC (0x3 << 21) // (AC97C) Channel C data will be transmitted during this slot
2144 #define AT91C_AC97C_CHID11 (0x7 << 24) // (AC97C) Channel Id for the input slot 11
2145 #define AT91C_AC97C_CHID11_NONE (0x0 << 24) // (AC97C) No data will be transmitted during this slot
2146 #define AT91C_AC97C_CHID11_CA (0x1 << 24) // (AC97C) Channel A data will be transmitted during this slot
2147 #define AT91C_AC97C_CHID11_CB (0x2 << 24) // (AC97C) Channel B data will be transmitted during this slot
2148 #define AT91C_AC97C_CHID11_CC (0x3 << 24) // (AC97C) Channel C data will be transmitted during this slot
2149 #define AT91C_AC97C_CHID12 (0x7 << 27) // (AC97C) Channel Id for the input slot 12
2150 #define AT91C_AC97C_CHID12_NONE (0x0 << 27) // (AC97C) No data will be transmitted during this slot
2151 #define AT91C_AC97C_CHID12_CA (0x1 << 27) // (AC97C) Channel A data will be transmitted during this slot
2152 #define AT91C_AC97C_CHID12_CB (0x2 << 27) // (AC97C) Channel B data will be transmitted during this slot
2153 #define AT91C_AC97C_CHID12_CC (0x3 << 27) // (AC97C) Channel C data will be transmitted during this slot
2154 // -------- AC97C_OCA : (AC97C Offset: 0x14) AC97C Output Channel Assignement Register --------
2155 // -------- AC97C_CARHR : (AC97C Offset: 0x20) AC97C Channel A Receive Holding Register --------
2156 #define AT91C_AC97C_RDATA (0xFFFFF << 0) // (AC97C) Receive data
2157 // -------- AC97C_CATHR : (AC97C Offset: 0x24) AC97C Channel A Transmit Holding Register --------
2158 #define AT91C_AC97C_TDATA (0xFFFFF << 0) // (AC97C) Transmit data
2159 // -------- AC97C_CASR : (AC97C Offset: 0x28) AC97C Channel A Status Register --------
2160 #define AT91C_AC97C_TXRDY (0x1 << 0) // (AC97C)
2161 #define AT91C_AC97C_TXEMPTY (0x1 << 1) // (AC97C)
2162 #define AT91C_AC97C_UNRUN (0x1 << 2) // (AC97C)
2163 #define AT91C_AC97C_RXRDY (0x1 << 4) // (AC97C)
2164 #define AT91C_AC97C_OVRUN (0x1 << 5) // (AC97C)
2165 #define AT91C_AC97C_ENDTX (0x1 << 10) // (AC97C)
2166 #define AT91C_AC97C_TXBUFE (0x1 << 11) // (AC97C)
2167 #define AT91C_AC97C_ENDRX (0x1 << 14) // (AC97C)
2168 #define AT91C_AC97C_RXBUFF (0x1 << 15) // (AC97C)
2169 // -------- AC97C_CAMR : (AC97C Offset: 0x2c) AC97C Channel A Mode Register --------
2170 #define AT91C_AC97C_SIZE (0x3 << 16) // (AC97C)
2171 #define AT91C_AC97C_SIZE_20_BITS (0x0 << 16) // (AC97C) Data size is 20 bits
2172 #define AT91C_AC97C_SIZE_18_BITS (0x1 << 16) // (AC97C) Data size is 18 bits
2173 #define AT91C_AC97C_SIZE_16_BITS (0x2 << 16) // (AC97C) Data size is 16 bits
2174 #define AT91C_AC97C_SIZE_10_BITS (0x3 << 16) // (AC97C) Data size is 10 bits
2175 #define AT91C_AC97C_CEM (0x1 << 18) // (AC97C)
2176 #define AT91C_AC97C_CEN (0x1 << 21) // (AC97C)
2177 #define AT91C_AC97C_PDCEN (0x1 << 22) // (AC97C)
2178 // -------- AC97C_CBRHR : (AC97C Offset: 0x30) AC97C Channel B Receive Holding Register --------
2179 // -------- AC97C_CBTHR : (AC97C Offset: 0x34) AC97C Channel B Transmit Holding Register --------
2180 // -------- AC97C_CBSR : (AC97C Offset: 0x38) AC97C Channel B Status Register --------
2181 // -------- AC97C_CBMR : (AC97C Offset: 0x3c) AC97C Channel B Mode Register --------
2182 // -------- AC97C_CORHR : (AC97C Offset: 0x40) AC97C Codec Channel Receive Holding Register --------
2183 #define AT91C_AC97C_SDATA (0xFFFF << 0) // (AC97C) Status Data
2184 // -------- AC97C_COTHR : (AC97C Offset: 0x44) AC97C Codec Channel Transmit Holding Register --------
2185 #define AT91C_AC97C_CDATA (0xFFFF << 0) // (AC97C) Command Data
2186 #define AT91C_AC97C_CADDR (0x7F << 16) // (AC97C) COdec control register index
2187 #define AT91C_AC97C_READ (0x1 << 23) // (AC97C) Read/Write command
2188 // -------- AC97C_COSR : (AC97C Offset: 0x48) AC97C CODEC Status Register --------
2189 // -------- AC97C_COMR : (AC97C Offset: 0x4c) AC97C CODEC Mode Register --------
2190 // -------- AC97C_SR : (AC97C Offset: 0x50) AC97C Status Register --------
2191 #define AT91C_AC97C_SOF (0x1 << 0) // (AC97C)
2192 #define AT91C_AC97C_WKUP (0x1 << 1) // (AC97C)
2193 #define AT91C_AC97C_COEVT (0x1 << 2) // (AC97C)
2194 #define AT91C_AC97C_CAEVT (0x1 << 3) // (AC97C)
2195 #define AT91C_AC97C_CBEVT (0x1 << 4) // (AC97C)
2196 // -------- AC97C_IER : (AC97C Offset: 0x54) AC97C Interrupt Enable Register --------
2197 // -------- AC97C_IDR : (AC97C Offset: 0x58) AC97C Interrupt Disable Register --------
2198 // -------- AC97C_IMR : (AC97C Offset: 0x5c) AC97C Interrupt Mask Register --------
2200 // *****************************************************************************
2201 // SOFTWARE API DEFINITION FOR Serial Parallel Interface
2202 // *****************************************************************************
2203 // *** Register offset in AT91S_SPI structure ***
2204 #define SPI_CR ( 0) // Control Register
2205 #define SPI_MR ( 4) // Mode Register
2206 #define SPI_RDR ( 8) // Receive Data Register
2207 #define SPI_TDR (12) // Transmit Data Register
2208 #define SPI_SR (16) // Status Register
2209 #define SPI_IER (20) // Interrupt Enable Register
2210 #define SPI_IDR (24) // Interrupt Disable Register
2211 #define SPI_IMR (28) // Interrupt Mask Register
2212 #define SPI_CSR (48) // Chip Select Register
2213 #define SPI_RPR (256) // Receive Pointer Register
2214 #define SPI_RCR (260) // Receive Counter Register
2215 #define SPI_TPR (264) // Transmit Pointer Register
2216 #define SPI_TCR (268) // Transmit Counter Register
2217 #define SPI_RNPR (272) // Receive Next Pointer Register
2218 #define SPI_RNCR (276) // Receive Next Counter Register
2219 #define SPI_TNPR (280) // Transmit Next Pointer Register
2220 #define SPI_TNCR (284) // Transmit Next Counter Register
2221 #define SPI_PTCR (288) // PDC Transfer Control Register
2222 #define SPI_PTSR (292) // PDC Transfer Status Register
2223 // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
2224 #define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
2225 #define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
2226 #define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
2227 #define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
2228 // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
2229 #define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
2230 #define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
2231 #define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
2232 #define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
2233 #define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
2234 #define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
2235 #define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
2236 #define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
2237 #define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
2238 #define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
2239 // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
2240 #define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
2241 #define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
2242 // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
2243 #define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
2244 #define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
2245 // -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
2246 #define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
2247 #define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
2248 #define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
2249 #define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
2250 #define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
2251 #define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
2252 #define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
2253 #define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
2254 #define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
2255 #define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
2256 #define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
2257 // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
2258 // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
2259 // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
2260 // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
2261 #define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
2262 #define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
2263 #define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
2264 #define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
2265 #define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
2266 #define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
2267 #define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
2268 #define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
2269 #define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
2270 #define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
2271 #define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
2272 #define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
2273 #define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
2274 #define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
2275 #define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
2276 #define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
2278 // *****************************************************************************
2279 // SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
2280 // *****************************************************************************
2281 // *** Register offset in AT91S_CAN_MB structure ***
2282 #define CAN_MB_MMR ( 0) // MailBox Mode Register
2283 #define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register
2284 #define CAN_MB_MID ( 8) // MailBox ID Register
2285 #define CAN_MB_MFID (12) // MailBox Family ID Register
2286 #define CAN_MB_MSR (16) // MailBox Status Register
2287 #define CAN_MB_MDL (20) // MailBox Data Low Register
2288 #define CAN_MB_MDH (24) // MailBox Data High Register
2289 #define CAN_MB_MCR (28) // MailBox Control Register
2290 // -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
2291 #define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
2292 #define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
2293 #define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
2294 #define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
2295 #define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
2296 #define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
2297 #define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
2298 #define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
2299 #define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
2300 // -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
2301 #define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
2302 #define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
2303 #define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
2304 // -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
2305 // -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
2306 // -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
2307 #define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
2308 #define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
2309 #define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
2310 #define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
2311 #define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
2312 #define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
2313 // -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
2314 // -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
2315 // -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
2316 #define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
2317 #define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
2319 // *****************************************************************************
2320 // SOFTWARE API DEFINITION FOR Control Area Network Interface
2321 // *****************************************************************************
2322 // *** Register offset in AT91S_CAN structure ***
2323 #define CAN_MR ( 0) // Mode Register
2324 #define CAN_IER ( 4) // Interrupt Enable Register
2325 #define CAN_IDR ( 8) // Interrupt Disable Register
2326 #define CAN_IMR (12) // Interrupt Mask Register
2327 #define CAN_SR (16) // Status Register
2328 #define CAN_BR (20) // Baudrate Register
2329 #define CAN_TIM (24) // Timer Register
2330 #define CAN_TIMESTP (28) // Time Stamp Register
2331 #define CAN_ECR (32) // Error Counter Register
2332 #define CAN_TCR (36) // Transfer Command Register
2333 #define CAN_ACR (40) // Abort Command Register
2334 #define CAN_VR (252) // Version Register
2335 #define CAN_MB0 (512) // CAN Mailbox 0
2336 #define CAN_MB1 (544) // CAN Mailbox 1
2337 #define CAN_MB2 (576) // CAN Mailbox 2
2338 #define CAN_MB3 (608) // CAN Mailbox 3
2339 #define CAN_MB4 (640) // CAN Mailbox 4
2340 #define CAN_MB5 (672) // CAN Mailbox 5
2341 #define CAN_MB6 (704) // CAN Mailbox 6
2342 #define CAN_MB7 (736) // CAN Mailbox 7
2343 #define CAN_MB8 (768) // CAN Mailbox 8
2344 #define CAN_MB9 (800) // CAN Mailbox 9
2345 #define CAN_MB10 (832) // CAN Mailbox 10
2346 #define CAN_MB11 (864) // CAN Mailbox 11
2347 #define CAN_MB12 (896) // CAN Mailbox 12
2348 #define CAN_MB13 (928) // CAN Mailbox 13
2349 #define CAN_MB14 (960) // CAN Mailbox 14
2350 #define CAN_MB15 (992) // CAN Mailbox 15
2351 // -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
2352 #define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
2353 #define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
2354 #define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
2355 #define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
2356 #define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
2357 #define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
2358 #define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
2359 #define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
2360 // -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
2361 #define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
2362 #define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
2363 #define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
2364 #define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
2365 #define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
2366 #define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
2367 #define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
2368 #define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
2369 #define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
2370 #define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
2371 #define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
2372 #define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
2373 #define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
2374 #define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
2375 #define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
2376 #define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
2377 #define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
2378 #define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
2379 #define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
2380 #define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
2381 #define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
2382 #define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
2383 #define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
2384 #define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
2385 #define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
2386 #define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
2387 #define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
2388 #define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
2389 #define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
2390 // -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
2391 // -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
2392 // -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
2393 #define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
2394 #define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
2395 #define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
2396 // -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
2397 #define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
2398 #define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
2399 #define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
2400 #define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
2401 #define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
2402 #define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
2403 // -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
2404 #define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
2405 // -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
2406 // -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
2407 #define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
2408 #define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
2409 // -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
2410 #define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
2411 // -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
2413 // *****************************************************************************
2414 // SOFTWARE API DEFINITION FOR Advanced Encryption Standard
2415 // *****************************************************************************
2416 // *** Register offset in AT91S_AES structure ***
2417 #define AES_CR ( 0) // Control Register
2418 #define AES_MR ( 4) // Mode Register
2419 #define AES_IER (16) // Interrupt Enable Register
2420 #define AES_IDR (20) // Interrupt Disable Register
2421 #define AES_IMR (24) // Interrupt Mask Register
2422 #define AES_ISR (28) // Interrupt Status Register
2423 #define AES_KEYWxR (32) // Key Word x Register
2424 #define AES_IDATAxR (64) // Input Data x Register
2425 #define AES_ODATAxR (80) // Output Data x Register
2426 #define AES_IVxR (96) // Initialization Vector x Register
2427 #define AES_VR (252) // AES Version Register
2428 #define AES_RPR (256) // Receive Pointer Register
2429 #define AES_RCR (260) // Receive Counter Register
2430 #define AES_TPR (264) // Transmit Pointer Register
2431 #define AES_TCR (268) // Transmit Counter Register
2432 #define AES_RNPR (272) // Receive Next Pointer Register
2433 #define AES_RNCR (276) // Receive Next Counter Register
2434 #define AES_TNPR (280) // Transmit Next Pointer Register
2435 #define AES_TNCR (284) // Transmit Next Counter Register
2436 #define AES_PTCR (288) // PDC Transfer Control Register
2437 #define AES_PTSR (292) // PDC Transfer Status Register
2438 // -------- AES_CR : (AES Offset: 0x0) Control Register --------
2439 #define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing
2440 #define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset
2441 #define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading
2442 // -------- AES_MR : (AES Offset: 0x4) Mode Register --------
2443 #define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode
2444 #define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay
2445 #define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode
2446 #define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
2447 #define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
2448 #define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet).
2449 #define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode
2450 #define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
2451 #define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
2452 #define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode.
2453 #define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode.
2454 #define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode.
2455 #define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode
2456 #define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size
2457 #define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit.
2458 #define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit.
2459 #define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit.
2460 #define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit.
2461 #define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit.
2462 #define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key
2463 #define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type
2464 #define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
2465 #define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
2466 #define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
2467 #define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
2468 #define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
2469 // -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
2470 #define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY
2471 #define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End
2472 #define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End
2473 #define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full
2474 #define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty
2475 #define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection
2476 // -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
2477 // -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
2478 // -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
2479 #define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status
2480 #define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
2481 #define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
2482 #define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
2483 #define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
2484 #define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
2485 #define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access.
2487 // *****************************************************************************
2488 // SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
2489 // *****************************************************************************
2490 // *** Register offset in AT91S_TDES structure ***
2491 #define TDES_CR ( 0) // Control Register
2492 #define TDES_MR ( 4) // Mode Register
2493 #define TDES_IER (16) // Interrupt Enable Register
2494 #define TDES_IDR (20) // Interrupt Disable Register
2495 #define TDES_IMR (24) // Interrupt Mask Register
2496 #define TDES_ISR (28) // Interrupt Status Register
2497 #define TDES_KEY1WxR (32) // Key 1 Word x Register
2498 #define TDES_KEY2WxR (40) // Key 2 Word x Register
2499 #define TDES_KEY3WxR (48) // Key 3 Word x Register
2500 #define TDES_IDATAxR (64) // Input Data x Register
2501 #define TDES_ODATAxR (80) // Output Data x Register
2502 #define TDES_IVxR (96) // Initialization Vector x Register
2503 #define TDES_VR (252) // TDES Version Register
2504 #define TDES_RPR (256) // Receive Pointer Register
2505 #define TDES_RCR (260) // Receive Counter Register
2506 #define TDES_TPR (264) // Transmit Pointer Register
2507 #define TDES_TCR (268) // Transmit Counter Register
2508 #define TDES_RNPR (272) // Receive Next Pointer Register
2509 #define TDES_RNCR (276) // Receive Next Counter Register
2510 #define TDES_TNPR (280) // Transmit Next Pointer Register
2511 #define TDES_TNCR (284) // Transmit Next Counter Register
2512 #define TDES_PTCR (288) // PDC Transfer Control Register
2513 #define TDES_PTSR (292) // PDC Transfer Status Register
2514 // -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
2515 #define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing
2516 #define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset
2517 // -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
2518 #define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode
2519 #define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode
2520 #define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode
2521 #define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode
2522 #define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
2523 #define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
2524 #define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet).
2525 #define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode
2526 #define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
2527 #define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
2528 #define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode.
2529 #define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
2530 #define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode
2531 #define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size
2532 #define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit.
2533 #define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit.
2534 #define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit.
2535 #define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit.
2536 // -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
2537 #define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY
2538 #define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End
2539 #define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End
2540 #define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full
2541 #define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty
2542 #define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection
2543 // -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
2544 // -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
2545 // -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
2546 #define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status
2547 #define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
2548 #define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
2549 #define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
2550 #define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access.
2552 // *****************************************************************************
2553 // SOFTWARE API DEFINITION FOR PWMC Channel Interface
2554 // *****************************************************************************
2555 // *** Register offset in AT91S_PWMC_CH structure ***
2556 #define PWMC_CMR ( 0) // Channel Mode Register
2557 #define PWMC_CDTYR ( 4) // Channel Duty Cycle Register
2558 #define PWMC_CPRDR ( 8) // Channel Period Register
2559 #define PWMC_CCNTR (12) // Channel Counter Register
2560 #define PWMC_CUPDR (16) // Channel Update Register
2561 #define PWMC_Reserved (20) // Reserved
2562 // -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
2563 #define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
2564 #define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
2565 #define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
2566 #define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
2567 #define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
2568 #define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
2569 #define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
2570 // -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
2571 #define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
2572 // -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
2573 #define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
2574 // -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
2575 #define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
2576 // -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
2577 #define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
2579 // *****************************************************************************
2580 // SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
2581 // *****************************************************************************
2582 // *** Register offset in AT91S_PWMC structure ***
2583 #define PWMC_MR ( 0) // PWMC Mode Register
2584 #define PWMC_ENA ( 4) // PWMC Enable Register
2585 #define PWMC_DIS ( 8) // PWMC Disable Register
2586 #define PWMC_SR (12) // PWMC Status Register
2587 #define PWMC_IER (16) // PWMC Interrupt Enable Register
2588 #define PWMC_IDR (20) // PWMC Interrupt Disable Register
2589 #define PWMC_IMR (24) // PWMC Interrupt Mask Register
2590 #define PWMC_ISR (28) // PWMC Interrupt Status Register
2591 #define PWMC_VR (252) // PWMC Version Register
2592 #define PWMC_CH (512) // PWMC Channel
2593 // -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
2594 #define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
2595 #define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
2596 #define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
2597 #define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
2598 #define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
2599 #define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
2600 // -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
2601 #define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
2602 #define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
2603 #define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
2604 #define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
2605 #define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4
2606 #define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5
2607 #define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6
2608 #define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7
2609 // -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
2610 // -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
2611 // -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
2612 // -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
2613 // -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
2614 // -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
2616 // *****************************************************************************
2617 // SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
2618 // *****************************************************************************
2619 // *** Register offset in AT91S_EMAC structure ***
2620 #define EMAC_NCR ( 0) // Network Control Register
2621 #define EMAC_NCFGR ( 4) // Network Configuration Register
2622 #define EMAC_NSR ( 8) // Network Status Register
2623 #define EMAC_TSR (20) // Transmit Status Register
2624 #define EMAC_RBQP (24) // Receive Buffer Queue Pointer
2625 #define EMAC_TBQP (28) // Transmit Buffer Queue Pointer
2626 #define EMAC_RSR (32) // Receive Status Register
2627 #define EMAC_ISR (36) // Interrupt Status Register
2628 #define EMAC_IER (40) // Interrupt Enable Register
2629 #define EMAC_IDR (44) // Interrupt Disable Register
2630 #define EMAC_IMR (48) // Interrupt Mask Register
2631 #define EMAC_MAN (52) // PHY Maintenance Register
2632 #define EMAC_PTR (56) // Pause Time Register
2633 #define EMAC_PFR (60) // Pause Frames received Register
2634 #define EMAC_FTO (64) // Frames Transmitted OK Register
2635 #define EMAC_SCF (68) // Single Collision Frame Register
2636 #define EMAC_MCF (72) // Multiple Collision Frame Register
2637 #define EMAC_FRO (76) // Frames Received OK Register
2638 #define EMAC_FCSE (80) // Frame Check Sequence Error Register
2639 #define EMAC_ALE (84) // Alignment Error Register
2640 #define EMAC_DTF (88) // Deferred Transmission Frame Register
2641 #define EMAC_LCOL (92) // Late Collision Register
2642 #define EMAC_ECOL (96) // Excessive Collision Register
2643 #define EMAC_TUND (100) // Transmit Underrun Error Register
2644 #define EMAC_CSE (104) // Carrier Sense Error Register
2645 #define EMAC_RRE (108) // Receive Ressource Error Register
2646 #define EMAC_ROV (112) // Receive Overrun Errors Register
2647 #define EMAC_RSE (116) // Receive Symbol Errors Register
2648 #define EMAC_ELE (120) // Excessive Length Errors Register
2649 #define EMAC_RJA (124) // Receive Jabbers Register
2650 #define EMAC_USF (128) // Undersize Frames Register
2651 #define EMAC_STE (132) // SQE Test Error Register
2652 #define EMAC_RLE (136) // Receive Length Field Mismatch Register
2653 #define EMAC_TPF (140) // Transmitted Pause Frames Register
2654 #define EMAC_HRB (144) // Hash Address Bottom[31:0]
2655 #define EMAC_HRT (148) // Hash Address Top[63:32]
2656 #define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes
2657 #define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes
2658 #define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes
2659 #define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes
2660 #define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes
2661 #define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes
2662 #define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes
2663 #define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes
2664 #define EMAC_TID (184) // Type ID Checking Register
2665 #define EMAC_TPQ (188) // Transmit Pause Quantum Register
2666 #define EMAC_USRIO (192) // USER Input/Output Register
2667 #define EMAC_WOL (196) // Wake On LAN Register
2668 #define EMAC_REV (252) // Revision Register
2669 // -------- EMAC_NCR : (EMAC Offset: 0x0) --------
2670 #define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
2671 #define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
2672 #define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
2673 #define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
2674 #define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
2675 #define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
2676 #define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
2677 #define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
2678 #define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
2679 #define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
2680 #define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
2681 #define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
2682 #define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
2683 // -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
2684 #define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
2685 #define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
2686 #define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
2687 #define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
2688 #define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
2689 #define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
2690 #define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
2691 #define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
2692 #define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
2693 #define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
2694 #define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
2695 #define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
2696 #define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
2697 #define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
2698 #define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
2699 #define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
2700 #define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
2701 #define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
2702 #define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
2703 #define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
2704 #define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
2705 #define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
2706 #define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
2707 #define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
2708 #define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
2709 // -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
2710 #define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
2711 #define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
2712 #define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
2713 // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
2714 #define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
2715 #define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
2716 #define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
2717 #define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
2718 #define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
2719 #define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
2720 #define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
2721 // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
2722 #define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
2723 #define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
2724 #define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
2725 // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
2726 #define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
2727 #define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
2728 #define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
2729 #define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
2730 #define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
2731 #define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
2732 #define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
2733 #define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
2734 #define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
2735 #define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
2736 #define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
2737 #define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
2738 #define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
2739 // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
2740 // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
2741 // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
2742 // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
2743 #define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
2744 #define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
2745 #define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
2746 #define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
2747 #define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
2748 #define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
2749 // -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
2750 #define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
2751 #define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable
2752 // -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
2753 #define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
2754 #define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
2755 #define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
2756 #define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
2757 // -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
2758 #define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
2759 #define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
2761 // *****************************************************************************
2762 // SOFTWARE API DEFINITION FOR Analog to Digital Convertor
2763 // *****************************************************************************
2764 // *** Register offset in AT91S_ADC structure ***
2765 #define ADC_CR ( 0) // ADC Control Register
2766 #define ADC_MR ( 4) // ADC Mode Register
2767 #define ADC_CHER (16) // ADC Channel Enable Register
2768 #define ADC_CHDR (20) // ADC Channel Disable Register
2769 #define ADC_CHSR (24) // ADC Channel Status Register
2770 #define ADC_SR (28) // ADC Status Register
2771 #define ADC_LCDR (32) // ADC Last Converted Data Register
2772 #define ADC_IER (36) // ADC Interrupt Enable Register
2773 #define ADC_IDR (40) // ADC Interrupt Disable Register
2774 #define ADC_IMR (44) // ADC Interrupt Mask Register
2775 #define ADC_CDR0 (48) // ADC Channel Data Register 0
2776 #define ADC_CDR1 (52) // ADC Channel Data Register 1
2777 #define ADC_CDR2 (56) // ADC Channel Data Register 2
2778 #define ADC_CDR3 (60) // ADC Channel Data Register 3
2779 #define ADC_CDR4 (64) // ADC Channel Data Register 4
2780 #define ADC_CDR5 (68) // ADC Channel Data Register 5
2781 #define ADC_CDR6 (72) // ADC Channel Data Register 6
2782 #define ADC_CDR7 (76) // ADC Channel Data Register 7
2783 #define ADC_RPR (256) // Receive Pointer Register
2784 #define ADC_RCR (260) // Receive Counter Register
2785 #define ADC_TPR (264) // Transmit Pointer Register
2786 #define ADC_TCR (268) // Transmit Counter Register
2787 #define ADC_RNPR (272) // Receive Next Pointer Register
2788 #define ADC_RNCR (276) // Receive Next Counter Register
2789 #define ADC_TNPR (280) // Transmit Next Pointer Register
2790 #define ADC_TNCR (284) // Transmit Next Counter Register
2791 #define ADC_PTCR (288) // PDC Transfer Control Register
2792 #define ADC_PTSR (292) // PDC Transfer Status Register
2793 // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
2794 #define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
2795 #define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
2796 // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
2797 #define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
2798 #define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
2799 #define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
2800 #define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
2801 #define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
2802 #define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
2803 #define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
2804 #define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
2805 #define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
2806 #define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
2807 #define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
2808 #define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
2809 #define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
2810 #define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
2811 #define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
2812 #define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
2813 #define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
2814 #define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
2815 #define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
2816 #define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
2817 // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
2818 #define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
2819 #define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
2820 #define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
2821 #define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
2822 #define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
2823 #define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
2824 #define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
2825 #define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
2826 // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
2827 // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
2828 // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
2829 #define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
2830 #define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
2831 #define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
2832 #define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
2833 #define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
2834 #define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
2835 #define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
2836 #define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
2837 #define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
2838 #define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
2839 #define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
2840 #define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
2841 #define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
2842 #define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
2843 #define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
2844 #define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
2845 #define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
2846 #define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
2847 #define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
2848 #define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
2849 // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
2850 #define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
2851 // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
2852 // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
2853 // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
2854 // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
2855 #define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
2856 // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
2857 // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
2858 // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
2859 // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
2860 // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
2861 // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
2862 // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
2864 // *****************************************************************************
2865 // SOFTWARE API DEFINITION FOR Image Sensor Interface
2866 // *****************************************************************************
2867 // *** Register offset in AT91S_ISI structure ***
2868 #define ISI_CR1 ( 0) // Control Register 1
2869 #define ISI_CR2 ( 4) // Control Register 2
2870 #define ISI_SR ( 8) // Status Register
2871 #define ISI_IER (12) // Interrupt Enable Register
2872 #define ISI_IDR (16) // Interrupt Disable Register
2873 #define ISI_IMR (20) // Interrupt Mask Register
2874 #define ISI_PSIZE (32) // Preview Size Register
2875 #define ISI_PDECF (36) // Preview Decimation Factor Register
2876 #define ISI_PFBD (40) // Preview Frame Buffer Address Register
2877 #define ISI_CDBA (44) // Codec Dma Address Register
2878 #define ISI_Y2RSET0 (48) // Color Space Conversion Register
2879 #define ISI_Y2RSET1 (52) // Color Space Conversion Register
2880 #define ISI_R2YSET0 (56) // Color Space Conversion Register
2881 #define ISI_R2YSET1 (60) // Color Space Conversion Register
2882 #define ISI_R2YSET2 (64) // Color Space Conversion Register
2883 // -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 --------
2884 #define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset
2885 #define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable.
2886 #define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity
2887 #define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity
2888 #define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation
2889 #define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction
2890 #define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed
2891 #define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask
2892 #define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed
2893 #define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed
2894 #define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed
2895 #define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path
2896 #define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay
2897 #define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay
2898 // -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 --------
2899 #define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047]
2900 #define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode
2901 #define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode
2902 #define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits
2903 #define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits
2904 #define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits
2905 #define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode
2906 #define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap
2907 #define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data
2908 #define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]
2909 #define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)
2910 #define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)
2911 #define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)
2912 #define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)
2913 #define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration
2914 #define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B
2915 #define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R
2916 #define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB)
2917 #define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB)
2918 // -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register --------
2919 #define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame
2920 #define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable
2921 #define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset
2922 #define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error
2923 #define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow
2924 #define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow
2925 #define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty
2926 #define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty
2927 #define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun
2928 // -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register --------
2929 // -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register --------
2930 // -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register --------
2931 // -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register --------
2932 #define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path
2933 #define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path
2934 // -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register --------
2935 #define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0
2936 #define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1
2937 #define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2
2938 #define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3
2939 // -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register --------
2940 #define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4
2941 #define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset
2942 #define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset
2943 #define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset
2944 // -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register --------
2945 #define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0
2946 #define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1
2947 #define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2
2948 #define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset
2949 // -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register --------
2950 #define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3
2951 #define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4
2952 #define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5
2953 #define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset
2954 // -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register --------
2955 #define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6
2956 #define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7
2957 #define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8
2958 #define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset
2960 // *****************************************************************************
2961 // SOFTWARE API DEFINITION FOR LCD Controller
2962 // *****************************************************************************
2963 // *** Register offset in AT91S_LCDC structure ***
2964 #define LCDC_BA1 ( 0) // DMA Base Address Register 1
2965 #define LCDC_BA2 ( 4) // DMA Base Address Register 2
2966 #define LCDC_FRMP1 ( 8) // DMA Frame Pointer Register 1
2967 #define LCDC_FRMP2 (12) // DMA Frame Pointer Register 2
2968 #define LCDC_FRMA1 (16) // DMA Frame Address Register 1
2969 #define LCDC_FRMA2 (20) // DMA Frame Address Register 2
2970 #define LCDC_FRMCFG (24) // DMA Frame Configuration Register
2971 #define LCDC_DMACON (28) // DMA Control Register
2972 #define LCDC_DMA2DCFG (32) // DMA 2D addressing configuration
2973 #define LCDC_LCDCON1 (2048) // LCD Control 1 Register
2974 #define LCDC_LCDCON2 (2052) // LCD Control 2 Register
2975 #define LCDC_TIM1 (2056) // LCD Timing Config 1 Register
2976 #define LCDC_TIM2 (2060) // LCD Timing Config 2 Register
2977 #define LCDC_LCDFRCFG (2064) // LCD Frame Config Register
2978 #define LCDC_FIFO (2068) // LCD FIFO Register
2979 #define LCDC_MVAL (2072) // LCD Mode Toggle Rate Value Register
2980 #define LCDC_DP1_2 (2076) // Dithering Pattern DP1_2 Register
2981 #define LCDC_DP4_7 (2080) // Dithering Pattern DP4_7 Register
2982 #define LCDC_DP3_5 (2084) // Dithering Pattern DP3_5 Register
2983 #define LCDC_DP2_3 (2088) // Dithering Pattern DP2_3 Register
2984 #define LCDC_DP5_7 (2092) // Dithering Pattern DP5_7 Register
2985 #define LCDC_DP3_4 (2096) // Dithering Pattern DP3_4 Register
2986 #define LCDC_DP4_5 (2100) // Dithering Pattern DP4_5 Register
2987 #define LCDC_DP6_7 (2104) // Dithering Pattern DP6_7 Register
2988 #define LCDC_PWRCON (2108) // Power Control Register
2989 #define LCDC_CTRSTCON (2112) // Contrast Control Register
2990 #define LCDC_CTRSTVAL (2116) // Contrast Value Register
2991 #define LCDC_IER (2120) // Interrupt Enable Register
2992 #define LCDC_IDR (2124) // Interrupt Disable Register
2993 #define LCDC_IMR (2128) // Interrupt Mask Register
2994 #define LCDC_ISR (2132) // Interrupt Enable Register
2995 #define LCDC_ICR (2136) // Interrupt Clear Register
2996 #define LCDC_GPR (2140) // General Purpose Register
2997 #define LCDC_ITR (2144) // Interrupts Test Register
2998 #define LCDC_IRR (2148) // Interrupts Raw Status Register
2999 #define LCDC_LUT_ENTRY (3072) // LUT Entries Register
3000 // -------- LCDC_FRMP1 : (LCDC Offset: 0x8) DMA Frame Pointer 1 Register --------
3001 #define AT91C_LCDC_FRMPT1 (0x3FFFFF << 0) // (LCDC) Frame Pointer Address 1
3002 // -------- LCDC_FRMP2 : (LCDC Offset: 0xc) DMA Frame Pointer 2 Register --------
3003 #define AT91C_LCDC_FRMPT2 (0x1FFFFF << 0) // (LCDC) Frame Pointer Address 2
3004 // -------- LCDC_FRMCFG : (LCDC Offset: 0x18) DMA Frame Config Register --------
3005 #define AT91C_LCDC_FRSIZE (0x3FFFFF << 0) // (LCDC) FRAME SIZE
3006 #define AT91C_LCDC_BLENGTH (0xF << 24) // (LCDC) BURST LENGTH
3007 // -------- LCDC_DMACON : (LCDC Offset: 0x1c) DMA Control Register --------
3008 #define AT91C_LCDC_DMAEN (0x1 << 0) // (LCDC) DAM Enable
3009 #define AT91C_LCDC_DMARST (0x1 << 1) // (LCDC) DMA Reset (WO)
3010 #define AT91C_LCDC_DMABUSY (0x1 << 2) // (LCDC) DMA Reset (WO)
3011 // -------- LCDC_DMA2DCFG : (LCDC Offset: 0x20) DMA 2D addressing configuration Register --------
3012 #define AT91C_LCDC_ADDRINC (0xFFFF << 0) // (LCDC) Number of 32b words that the DMA must jump when going to the next line
3013 #define AT91C_LCDC_PIXELOFF (0x1F << 24) // (LCDC) Offset (in bits) of the first pixel of the screen in the memory word which contain it
3014 // -------- LCDC_LCDCON1 : (LCDC Offset: 0x800) LCD Control 1 Register --------
3015 #define AT91C_LCDC_BYPASS (0x1 << 0) // (LCDC) Bypass lcd_pccklk divider
3016 #define AT91C_LCDC_CLKVAL (0x1FF << 12) // (LCDC) 9-bit Divider for pixel clock frequency
3017 #define AT91C_LCDC_LINCNT (0x7FF << 21) // (LCDC) Line Counter (RO)
3018 // -------- LCDC_LCDCON2 : (LCDC Offset: 0x804) LCD Control 2 Register --------
3019 #define AT91C_LCDC_DISTYPE (0x3 << 0) // (LCDC) Display Type
3020 #define AT91C_LCDC_DISTYPE_STNMONO (0x0) // (LCDC) STN Mono
3021 #define AT91C_LCDC_DISTYPE_STNCOLOR (0x1) // (LCDC) STN Color
3022 #define AT91C_LCDC_DISTYPE_TFT (0x2) // (LCDC) TFT
3023 #define AT91C_LCDC_SCANMOD (0x1 << 2) // (LCDC) Scan Mode
3024 #define AT91C_LCDC_SCANMOD_SINGLESCAN (0x0 << 2) // (LCDC) Single Scan
3025 #define AT91C_LCDC_SCANMOD_DUALSCAN (0x1 << 2) // (LCDC) Dual Scan
3026 #define AT91C_LCDC_IFWIDTH (0x3 << 3) // (LCDC) Interface Width
3027 #define AT91C_LCDC_IFWIDTH_FOURBITSWIDTH (0x0 << 3) // (LCDC) 4 Bits
3028 #define AT91C_LCDC_IFWIDTH_EIGTHBITSWIDTH (0x1 << 3) // (LCDC) 8 Bits
3029 #define AT91C_LCDC_IFWIDTH_SIXTEENBITSWIDTH (0x2 << 3) // (LCDC) 16 Bits
3030 #define AT91C_LCDC_PIXELSIZE (0x7 << 5) // (LCDC) Bits per pixel
3031 #define AT91C_LCDC_PIXELSIZE_ONEBITSPERPIXEL (0x0 << 5) // (LCDC) 1 Bits
3032 #define AT91C_LCDC_PIXELSIZE_TWOBITSPERPIXEL (0x1 << 5) // (LCDC) 2 Bits
3033 #define AT91C_LCDC_PIXELSIZE_FOURBITSPERPIXEL (0x2 << 5) // (LCDC) 4 Bits
3034 #define AT91C_LCDC_PIXELSIZE_EIGTHBITSPERPIXEL (0x3 << 5) // (LCDC) 8 Bits
3035 #define AT91C_LCDC_PIXELSIZE_SIXTEENBITSPERPIXEL (0x4 << 5) // (LCDC) 16 Bits
3036 #define AT91C_LCDC_PIXELSIZE_TWENTYFOURBITSPERPIXEL (0x5 << 5) // (LCDC) 24 Bits
3037 #define AT91C_LCDC_INVVD (0x1 << 8) // (LCDC) lcd datas polarity
3038 #define AT91C_LCDC_INVVD_NORMALPOL (0x0 << 8) // (LCDC) Normal Polarity
3039 #define AT91C_LCDC_INVVD_INVERTEDPOL (0x1 << 8) // (LCDC) Inverted Polarity
3040 #define AT91C_LCDC_INVFRAME (0x1 << 9) // (LCDC) lcd vsync polarity
3041 #define AT91C_LCDC_INVFRAME_NORMALPOL (0x0 << 9) // (LCDC) Normal Polarity
3042 #define AT91C_LCDC_INVFRAME_INVERTEDPOL (0x1 << 9) // (LCDC) Inverted Polarity
3043 #define AT91C_LCDC_INVLINE (0x1 << 10) // (LCDC) lcd hsync polarity
3044 #define AT91C_LCDC_INVLINE_NORMALPOL (0x0 << 10) // (LCDC) Normal Polarity
3045 #define AT91C_LCDC_INVLINE_INVERTEDPOL (0x1 << 10) // (LCDC) Inverted Polarity
3046 #define AT91C_LCDC_INVCLK (0x1 << 11) // (LCDC) lcd pclk polarity
3047 #define AT91C_LCDC_INVCLK_NORMALPOL (0x0 << 11) // (LCDC) Normal Polarity
3048 #define AT91C_LCDC_INVCLK_INVERTEDPOL (0x1 << 11) // (LCDC) Inverted Polarity
3049 #define AT91C_LCDC_INVDVAL (0x1 << 12) // (LCDC) lcd dval polarity
3050 #define AT91C_LCDC_INVDVAL_NORMALPOL (0x0 << 12) // (LCDC) Normal Polarity
3051 #define AT91C_LCDC_INVDVAL_INVERTEDPOL (0x1 << 12) // (LCDC) Inverted Polarity
3052 #define AT91C_LCDC_CLKMOD (0x1 << 15) // (LCDC) lcd pclk Mode
3053 #define AT91C_LCDC_CLKMOD_ACTIVEONLYDISP (0x0 << 15) // (LCDC) Active during display period
3054 #define AT91C_LCDC_CLKMOD_ALWAYSACTIVE (0x1 << 15) // (LCDC) Always Active
3055 #define AT91C_LCDC_MEMOR (0x1 << 31) // (LCDC) lcd pclk Mode
3056 #define AT91C_LCDC_MEMOR_BIGIND (0x0 << 31) // (LCDC) Big Endian
3057 #define AT91C_LCDC_MEMOR_LITTLEIND (0x1 << 31) // (LCDC) Little Endian
3058 // -------- LCDC_TIM1 : (LCDC Offset: 0x808) LCDC Timing Config 1 Register --------
3059 #define AT91C_LCDC_VFP (0xFF << 0) // (LCDC) Vertical Front Porch
3060 #define AT91C_LCDC_VBP (0xFF << 8) // (LCDC) Vertical Back Porch
3061 #define AT91C_LCDC_VPW (0x3F << 16) // (LCDC) Vertical Synchronization Pulse Width
3062 #define AT91C_LCDC_VHDLY (0xF << 24) // (LCDC) Vertical to Horizontal Delay
3063 // -------- LCDC_TIM2 : (LCDC Offset: 0x80c) LCDC Timing Config 2 Register --------
3064 #define AT91C_LCDC_HBP (0xFF << 0) // (LCDC) Horizontal Back Porch
3065 #define AT91C_LCDC_HPW (0x3F << 8) // (LCDC) Horizontal Synchronization Pulse Width
3066 #define AT91C_LCDC_HFP (0x3FF << 22) // (LCDC) Horizontal Front Porch
3067 // -------- LCDC_LCDFRCFG : (LCDC Offset: 0x810) LCD Frame Config Register --------
3068 #define AT91C_LCDC_LINEVAL (0x7FF << 0) // (LCDC) Vertical Size of LCD Module
3069 #define AT91C_LCDC_HOZVAL (0x7FF << 21) // (LCDC) Horizontal Size of LCD Module
3070 // -------- LCDC_FIFO : (LCDC Offset: 0x814) LCD FIFO Register --------
3071 #define AT91C_LCDC_FIFOTH (0xFFFF << 0) // (LCDC) FIFO Threshold
3072 // -------- LCDC_MVAL : (LCDC Offset: 0x818) LCD Mode Toggle Rate Value Register --------
3073 #define AT91C_LCDC_MVALUE (0xFF << 0) // (LCDC) Toggle Rate Value
3074 #define AT91C_LCDC_MMODE (0x1 << 31) // (LCDC) Toggle Rate Sel
3075 #define AT91C_LCDC_MMODE_EACHFRAME (0x0 << 31) // (LCDC) Each Frame
3076 #define AT91C_LCDC_MMODE_MVALDEFINED (0x1 << 31) // (LCDC) Defined by MVAL
3077 // -------- LCDC_DP1_2 : (LCDC Offset: 0x81c) Dithering Pattern 1/2 --------
3078 #define AT91C_LCDC_DP1_2_FIELD (0xFF << 0) // (LCDC) Ratio
3079 // -------- LCDC_DP4_7 : (LCDC Offset: 0x820) Dithering Pattern 4/7 --------
3080 #define AT91C_LCDC_DP4_7_FIELD (0xFFFFFFF << 0) // (LCDC) Ratio
3081 // -------- LCDC_DP3_5 : (LCDC Offset: 0x824) Dithering Pattern 3/5 --------
3082 #define AT91C_LCDC_DP3_5_FIELD (0xFFFFF << 0) // (LCDC) Ratio
3083 // -------- LCDC_DP2_3 : (LCDC Offset: 0x828) Dithering Pattern 2/3 --------
3084 #define AT91C_LCDC_DP2_3_FIELD (0xFFF << 0) // (LCDC) Ratio
3085 // -------- LCDC_DP5_7 : (LCDC Offset: 0x82c) Dithering Pattern 5/7 --------
3086 #define AT91C_LCDC_DP5_7_FIELD (0xFFFFFFF << 0) // (LCDC) Ratio
3087 // -------- LCDC_DP3_4 : (LCDC Offset: 0x830) Dithering Pattern 3/4 --------
3088 #define AT91C_LCDC_DP3_4_FIELD (0xFFFF << 0) // (LCDC) Ratio
3089 // -------- LCDC_DP4_5 : (LCDC Offset: 0x834) Dithering Pattern 4/5 --------
3090 #define AT91C_LCDC_DP4_5_FIELD (0xFFFFF << 0) // (LCDC) Ratio
3091 // -------- LCDC_DP6_7 : (LCDC Offset: 0x838) Dithering Pattern 6/7 --------
3092 #define AT91C_LCDC_DP6_7_FIELD (0xFFFFFFF << 0) // (LCDC) Ratio
3093 // -------- LCDC_PWRCON : (LCDC Offset: 0x83c) LCDC Power Control Register --------
3094 #define AT91C_LCDC_PWR (0x1 << 0) // (LCDC) LCD Module Power Control
3095 #define AT91C_LCDC_GUARDT (0x7F << 1) // (LCDC) Delay in Frame Period
3096 #define AT91C_LCDC_BUSY (0x1 << 31) // (LCDC) Read Only : 1 indicates that LCDC is busy
3097 #define AT91C_LCDC_BUSY_LCDNOTBUSY (0x0 << 31) // (LCDC) LCD is Not Busy
3098 #define AT91C_LCDC_BUSY_LCDBUSY (0x1 << 31) // (LCDC) LCD is Busy
3099 // -------- LCDC_CTRSTCON : (LCDC Offset: 0x840) LCDC Contrast Control Register --------
3100 #define AT91C_LCDC_PS (0x3 << 0) // (LCDC) LCD Contrast Counter Prescaler
3101 #define AT91C_LCDC_PS_NOTDIVIDED (0x0) // (LCDC) Counter Freq is System Freq.
3102 #define AT91C_LCDC_PS_DIVIDEDBYTWO (0x1) // (LCDC) Counter Freq is System Freq divided by 2.
3103 #define AT91C_LCDC_PS_DIVIDEDBYFOUR (0x2) // (LCDC) Counter Freq is System Freq divided by 4.
3104 #define AT91C_LCDC_PS_DIVIDEDBYEIGHT (0x3) // (LCDC) Counter Freq is System Freq divided by 8.
3105 #define AT91C_LCDC_POL (0x1 << 2) // (LCDC) Polarity of output Pulse
3106 #define AT91C_LCDC_POL_NEGATIVEPULSE (0x0 << 2) // (LCDC) Negative Pulse
3107 #define AT91C_LCDC_POL_POSITIVEPULSE (0x1 << 2) // (LCDC) Positive Pulse
3108 #define AT91C_LCDC_ENA (0x1 << 3) // (LCDC) PWM generator Control
3109 #define AT91C_LCDC_ENA_PWMGEMDISABLED (0x0 << 3) // (LCDC) PWM Generator Disabled
3110 #define AT91C_LCDC_ENA_PWMGEMENABLED (0x1 << 3) // (LCDC) PWM Generator Disabled
3111 // -------- LCDC_CTRSTVAL : (LCDC Offset: 0x844) Contrast Value Register --------
3112 #define AT91C_LCDC_CVAL (0xFF << 0) // (LCDC) PWM Compare Value
3113 // -------- LCDC_IER : (LCDC Offset: 0x848) LCDC Interrupt Enable Register --------
3114 #define AT91C_LCDC_LNI (0x1 << 0) // (LCDC) Line Interrupt
3115 #define AT91C_LCDC_LSTLNI (0x1 << 1) // (LCDC) Last Line Interrupt
3116 #define AT91C_LCDC_EOFI (0x1 << 2) // (LCDC) End Of Frame Interrupt
3117 #define AT91C_LCDC_UFLWI (0x1 << 4) // (LCDC) FIFO Underflow Interrupt
3118 #define AT91C_LCDC_OWRI (0x1 << 5) // (LCDC) Over Write Interrupt
3119 #define AT91C_LCDC_MERI (0x1 << 6) // (LCDC) Memory Error Interrupt
3120 // -------- LCDC_IDR : (LCDC Offset: 0x84c) LCDC Interrupt Disable Register --------
3121 // -------- LCDC_IMR : (LCDC Offset: 0x850) LCDC Interrupt Mask Register --------
3122 // -------- LCDC_ISR : (LCDC Offset: 0x854) LCDC Interrupt Status Register --------
3123 // -------- LCDC_ICR : (LCDC Offset: 0x858) LCDC Interrupt Clear Register --------
3124 // -------- LCDC_GPR : (LCDC Offset: 0x85c) LCDC General Purpose Register --------
3125 #define AT91C_LCDC_GPRBUS (0xFF << 0) // (LCDC) 8 bits available
3126 // -------- LCDC_ITR : (LCDC Offset: 0x860) Interrupts Test Register --------
3127 // -------- LCDC_IRR : (LCDC Offset: 0x864) Interrupts Raw Status Register --------
3129 // *****************************************************************************
3130 // SOFTWARE API DEFINITION FOR HDMA Channel structure
3131 // *****************************************************************************
3132 // *** Register offset in AT91S_HDMA_CH structure ***
3133 #define HDMA_SADDR ( 0) // HDMA Channel Source Address Register
3134 #define HDMA_DADDR ( 4) // HDMA Channel Destination Address Register
3135 #define HDMA_DSCR ( 8) // HDMA Channel Descriptor Address Register
3136 #define HDMA_CTRLA (12) // HDMA Channel Control A Register
3137 #define HDMA_CTRLB (16) // HDMA Channel Control B Register
3138 #define HDMA_CFG (20) // HDMA Channel Configuration Register
3139 #define HDMA_SPIP (24) // HDMA Channel Source Picture in Picture Configuration Register
3140 #define HDMA_DPIP (28) // HDMA Channel Destination Picture in Picture Configuration Register
3141 // -------- HDMA_SADDR : (HDMA_CH Offset: 0x0) --------
3142 #define AT91C_SADDR (0x0 << 0) // (HDMA_CH)
3143 // -------- HDMA_DADDR : (HDMA_CH Offset: 0x4) --------
3144 #define AT91C_DADDR (0x0 << 0) // (HDMA_CH)
3145 // -------- HDMA_DSCR : (HDMA_CH Offset: 0x8) --------
3146 #define AT91C_DSCR_IF (0x3 << 0) // (HDMA_CH)
3147 #define AT91C_DSCR (0x3FFFFFFF << 2) // (HDMA_CH)
3148 // -------- HDMA_CTRLA : (HDMA_CH Offset: 0xc) --------
3149 #define AT91C_BTSIZE (0xFFFF << 0) // (HDMA_CH)
3150 #define AT91C_SCSIZE (0x7 << 16) // (HDMA_CH)
3151 #define AT91C_DCSIZE (0x7 << 20) // (HDMA_CH)
3152 #define AT91C_SRC_WIDTH (0x3 << 24) // (HDMA_CH)
3153 #define AT91C_DST_WIDTH (0x3 << 28) // (HDMA_CH)
3154 #define AT91C_DONE (0x1 << 31) // (HDMA_CH)
3155 // -------- HDMA_CTRLB : (HDMA_CH Offset: 0x10) --------
3156 #define AT91C_SIF (0x3 << 0) // (HDMA_CH)
3157 #define AT91C_DIF (0x3 << 4) // (HDMA_CH)
3158 #define AT91C_SRC_PIP (0x1 << 8) // (HDMA_CH)
3159 #define AT91C_DST_PIP (0x1 << 12) // (HDMA_CH)
3160 #define AT91C_SRC_DSCR (0x1 << 16) // (HDMA_CH)
3161 #define AT91C_DST_DSCR (0x1 << 20) // (HDMA_CH)
3162 #define AT91C_FC (0x7 << 21) // (HDMA_CH)
3163 #define AT91C_SRC_INCR (0x3 << 24) // (HDMA_CH)
3164 #define AT91C_DST_INCR (0x3 << 28) // (HDMA_CH)
3165 #define AT91C_AUTO (0x1 << 31) // (HDMA_CH)
3166 // -------- HDMA_CFG : (HDMA_CH Offset: 0x14) --------
3167 #define AT91C_SRC_PER (0xF << 0) // (HDMA_CH)
3168 #define AT91C_DST_PER (0xF << 4) // (HDMA_CH)
3169 #define AT91C_SRC_REP (0x1 << 8) // (HDMA_CH)
3170 #define AT91C_SRC_H2SEL (0x1 << 9) // (HDMA_CH)
3171 #define AT91C_DST_REP (0x1 << 12) // (HDMA_CH)
3172 #define AT91C_DST_H2SEL (0x1 << 13) // (HDMA_CH)
3173 #define AT91C_SOD (0x1 << 16) // (HDMA_CH)
3174 #define AT91C_LOCK_IF (0x1 << 20) // (HDMA_CH)
3175 #define AT91C_LOCK_B (0x1 << 21) // (HDMA_CH)
3176 #define AT91C_LOCK_IF_L (0x1 << 22) // (HDMA_CH)
3177 #define AT91C_AHB_PROT (0x7 << 24) // (HDMA_CH)
3178 // -------- HDMA_SPIP : (HDMA_CH Offset: 0x18) --------
3179 #define AT91C_SPIP_HOLE (0xFFFF << 0) // (HDMA_CH)
3180 #define AT91C_SPIP_BOUNDARY (0x3FF << 16) // (HDMA_CH)
3181 // -------- HDMA_DPIP : (HDMA_CH Offset: 0x1c) --------
3182 #define AT91C_DPIP_HOLE (0xFFFF << 0) // (HDMA_CH)
3183 #define AT91C_DPIP_BOUNDARY (0x3FF << 16) // (HDMA_CH)
3185 // *****************************************************************************
3186 // SOFTWARE API DEFINITION FOR HDMA controller
3187 // *****************************************************************************
3188 // *** Register offset in AT91S_HDMA structure ***
3189 #define HDMA_GCFG ( 0) // HDMA Global Configuration Register
3190 #define HDMA_EN ( 4) // HDMA Controller Enable Register
3191 #define HDMA_SREQ ( 8) // HDMA Software Single Request Register
3192 #define HDMA_BREQ (12) // HDMA Software Chunk Transfer Request Register
3193 #define HDMA_LAST (16) // HDMA Software Last Transfer Flag Register
3194 #define HDMA_SYNC (20) // HDMA Request Synchronization Register
3195 #define HDMA_EBCIER (24) // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register
3196 #define HDMA_EBCIDR (28) // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register
3197 #define HDMA_EBCIMR (32) // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register
3198 #define HDMA_EBCISR (36) // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register
3199 #define HDMA_CHER (40) // HDMA Channel Handler Enable Register
3200 #define HDMA_CHDR (44) // HDMA Channel Handler Disable Register
3201 #define HDMA_CHSR (48) // HDMA Channel Handler Status Register
3202 #define HDMA_CH (60) // HDMA Channel structure
3203 // -------- HDMA_GCFG : (HDMA Offset: 0x0) --------
3204 #define AT91C_IF0_BIGEND (0x1 << 0) // (HDMA)
3205 #define AT91C_IF1_BIGEND (0x1 << 1) // (HDMA)
3206 #define AT91C_IF2_BIGEND (0x1 << 2) // (HDMA)
3207 #define AT91C_IF3_BIGEND (0x1 << 3) // (HDMA)
3208 #define AT91C_ARB_CFG (0x1 << 4) // (HDMA)
3209 // -------- HDMA_EN : (HDMA Offset: 0x4) --------
3210 #define AT91C_HDMA_ENABLE (0x1 << 0) // (HDMA)
3211 // -------- HDMA_SREQ : (HDMA Offset: 0x8) --------
3212 #define AT91C_SOFT_SREQ (0xFFFF << 0) // (HDMA)
3213 // -------- HDMA_BREQ : (HDMA Offset: 0xc) --------
3214 #define AT91C_SOFT_BREQ (0xFFFF << 0) // (HDMA)
3215 // -------- HDMA_LAST : (HDMA Offset: 0x10) --------
3216 #define AT91C_SOFT_LAST (0xFFFF << 0) // (HDMA)
3217 // -------- HDMA_SYNC : (HDMA Offset: 0x14) --------
3218 #define AT91C_SYNC_REQ (0xFFFF << 0) // (HDMA)
3219 // -------- HDMA_EBCIER : (HDMA Offset: 0x18) --------
3220 #define AT91C_BTC (0xFF << 0) // (HDMA)
3221 #define AT91C_CBTC (0xFF << 8) // (HDMA)
3222 #define AT91C_ERR (0xFF << 16) // (HDMA)
3223 // -------- HDMA_EBCIDR : (HDMA Offset: 0x1c) --------
3224 // -------- HDMA_EBCIMR : (HDMA Offset: 0x20) --------
3225 // -------- HDMA_EBCISR : (HDMA Offset: 0x24) --------
3226 // -------- HDMA_CHER : (HDMA Offset: 0x28) --------
3227 #define AT91C_ENABLE (0xFF << 0) // (HDMA)
3228 #define AT91C_SUSPEND (0xFF << 8) // (HDMA)
3229 #define AT91C_KEEPON (0xFF << 24) // (HDMA)
3230 // -------- HDMA_CHDR : (HDMA Offset: 0x2c) --------
3231 #define AT91C_RESUME (0xFF << 8) // (HDMA)
3232 // -------- HDMA_CHSR : (HDMA Offset: 0x30) --------
3233 #define AT91C_STALLED (0xFF << 14) // (HDMA)
3234 #define AT91C_EMPTY (0xFF << 16) // (HDMA)
3236 // *****************************************************************************
3237 // SOFTWARE API DEFINITION FOR System Peripherals
3238 // *****************************************************************************
3239 // -------- GPBR : (SYS Offset: 0x1b50) GPBR General Purpose Register --------
3240 #define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value
3242 // *****************************************************************************
3243 // SOFTWARE API DEFINITION FOR USB Host Interface
3244 // *****************************************************************************
3245 // *** Register offset in AT91S_UHP structure ***
3246 #define UHP_HcRevision ( 0) // Revision
3247 #define UHP_HcControl ( 4) // Operating modes for the Host Controller
3248 #define UHP_HcCommandStatus ( 8) // Command & status Register
3249 #define UHP_HcInterruptStatus (12) // Interrupt Status Register
3250 #define UHP_HcInterruptEnable (16) // Interrupt Enable Register
3251 #define UHP_HcInterruptDisable (20) // Interrupt Disable Register
3252 #define UHP_HcHCCA (24) // Pointer to the Host Controller Communication Area
3253 #define UHP_HcPeriodCurrentED (28) // Current Isochronous or Interrupt Endpoint Descriptor
3254 #define UHP_HcControlHeadED (32) // First Endpoint Descriptor of the Control list
3255 #define UHP_HcControlCurrentED (36) // Endpoint Control and Status Register
3256 #define UHP_HcBulkHeadED (40) // First endpoint register of the Bulk list
3257 #define UHP_HcBulkCurrentED (44) // Current endpoint of the Bulk list
3258 #define UHP_HcBulkDoneHead (48) // Last completed transfer descriptor
3259 #define UHP_HcFmInterval (52) // Bit time between 2 consecutive SOFs
3260 #define UHP_HcFmRemaining (56) // Bit time remaining in the current Frame
3261 #define UHP_HcFmNumber (60) // Frame number
3262 #define UHP_HcPeriodicStart (64) // Periodic Start
3263 #define UHP_HcLSThreshold (68) // LS Threshold
3264 #define UHP_HcRhDescriptorA (72) // Root Hub characteristics A
3265 #define UHP_HcRhDescriptorB (76) // Root Hub characteristics B
3266 #define UHP_HcRhStatus (80) // Root Hub Status register
3267 #define UHP_HcRhPortStatus (84) // Root Hub Port Status Register
3269 // *****************************************************************************
3270 // REGISTER ADDRESS DEFINITION FOR AT91CAP9
3271 // *****************************************************************************
3272 // ========== Register definition for HECC peripheral ==========
3273 #define AT91C_HECC_VR (0xFFFFE2FC) // (HECC) ECC Version register
3274 #define AT91C_HECC_SR (0xFFFFE208) // (HECC) ECC Status register
3275 #define AT91C_HECC_CR (0xFFFFE200) // (HECC) ECC reset register
3276 #define AT91C_HECC_NPR (0xFFFFE210) // (HECC) ECC Parity N register
3277 #define AT91C_HECC_PR (0xFFFFE20C) // (HECC) ECC Parity register
3278 #define AT91C_HECC_MR (0xFFFFE204) // (HECC) ECC Page size register
3279 // ========== Register definition for BCRAMC peripheral ==========
3280 #define AT91C_BCRAMC_IPNR1 (0xFFFFE4F0) // (BCRAMC) BCRAM IP Name Register 1
3281 #define AT91C_BCRAMC_HSR (0xFFFFE408) // (BCRAMC) BCRAM Controller High Speed Register
3282 #define AT91C_BCRAMC_CR (0xFFFFE400) // (BCRAMC) BCRAM Controller Configuration Register
3283 #define AT91C_BCRAMC_TPR (0xFFFFE404) // (BCRAMC) BCRAM Controller Timing Parameter Register
3284 #define AT91C_BCRAMC_LPR (0xFFFFE40C) // (BCRAMC) BCRAM Controller Low Power Register
3285 #define AT91C_BCRAMC_IPNR2 (0xFFFFE4F4) // (BCRAMC) BCRAM IP Name Register 2
3286 #define AT91C_BCRAMC_IPFR (0xFFFFE4F8) // (BCRAMC) BCRAM IP Features Register
3287 #define AT91C_BCRAMC_VR (0xFFFFE4FC) // (BCRAMC) BCRAM Version Register
3288 #define AT91C_BCRAMC_MDR (0xFFFFE410) // (BCRAMC) BCRAM Memory Device Register
3289 #define AT91C_BCRAMC_PADDSR (0xFFFFE4EC) // (BCRAMC) BCRAM PADDR Size Register
3290 // ========== Register definition for SDRAMC peripheral ==========
3291 #define AT91C_SDRAMC_TR (0xFFFFE604) // (SDRAMC) SDRAM Controller Refresh Timer Register
3292 #define AT91C_SDRAMC_ISR (0xFFFFE620) // (SDRAMC) SDRAM Controller Interrupt Mask Register
3293 #define AT91C_SDRAMC_HSR (0xFFFFE60C) // (SDRAMC) SDRAM Controller High Speed Register
3294 #define AT91C_SDRAMC_IMR (0xFFFFE61C) // (SDRAMC) SDRAM Controller Interrupt Mask Register
3295 #define AT91C_SDRAMC_IER (0xFFFFE614) // (SDRAMC) SDRAM Controller Interrupt Enable Register
3296 #define AT91C_SDRAMC_MR (0xFFFFE600) // (SDRAMC) SDRAM Controller Mode Register
3297 #define AT91C_SDRAMC_MDR (0xFFFFE624) // (SDRAMC) SDRAM Memory Device Register
3298 #define AT91C_SDRAMC_LPR (0xFFFFE610) // (SDRAMC) SDRAM Controller Low Power Register
3299 #define AT91C_SDRAMC_CR (0xFFFFE608) // (SDRAMC) SDRAM Controller Configuration Register
3300 #define AT91C_SDRAMC_IDR (0xFFFFE618) // (SDRAMC) SDRAM Controller Interrupt Disable Register
3301 // ========== Register definition for SDDRC peripheral ==========
3302 #define AT91C_SDDRC_RTR (0xFFFFE604) // (SDDRC)
3303 #define AT91C_SDDRC_T0PR (0xFFFFE60C) // (SDDRC)
3304 #define AT91C_SDDRC_MDR (0xFFFFE61C) // (SDDRC)
3305 #define AT91C_SDDRC_HS (0xFFFFE614) // (SDDRC)
3306 #define AT91C_SDDRC_VERSION (0xFFFFE6FC) // (SDDRC)
3307 #define AT91C_SDDRC_MR (0xFFFFE600) // (SDDRC)
3308 #define AT91C_SDDRC_T1PR (0xFFFFE610) // (SDDRC)
3309 #define AT91C_SDDRC_CR (0xFFFFE608) // (SDDRC)
3310 #define AT91C_SDDRC_LPR (0xFFFFE618) // (SDDRC)
3311 // ========== Register definition for SMC peripheral ==========
3312 #define AT91C_SMC_PULSE7 (0xFFFFE874) // (SMC) Pulse Register for CS 7
3313 #define AT91C_SMC_SETUP3 (0xFFFFE830) // (SMC) Setup Register for CS 3
3314 #define AT91C_SMC_CYCLE2 (0xFFFFE828) // (SMC) Cycle Register for CS 2
3315 #define AT91C_SMC_CTRL1 (0xFFFFE81C) // (SMC) Control Register for CS 1
3316 #define AT91C_SMC_CTRL0 (0xFFFFE80C) // (SMC) Control Register for CS 0
3317 #define AT91C_SMC_CYCLE7 (0xFFFFE878) // (SMC) Cycle Register for CS 7
3318 #define AT91C_SMC_PULSE2 (0xFFFFE824) // (SMC) Pulse Register for CS 2
3319 #define AT91C_SMC_SETUP6 (0xFFFFE860) // (SMC) Setup Register for CS 6
3320 #define AT91C_SMC_SETUP2 (0xFFFFE820) // (SMC) Setup Register for CS 2
3321 #define AT91C_SMC_CYCLE1 (0xFFFFE818) // (SMC) Cycle Register for CS 1
3322 #define AT91C_SMC_SETUP5 (0xFFFFE850) // (SMC) Setup Register for CS 5
3323 #define AT91C_SMC_PULSE1 (0xFFFFE814) // (SMC) Pulse Register for CS 1
3324 #define AT91C_SMC_CYCLE6 (0xFFFFE868) // (SMC) Cycle Register for CS 6
3325 #define AT91C_SMC_PULSE6 (0xFFFFE864) // (SMC) Pulse Register for CS 6
3326 #define AT91C_SMC_CTRL2 (0xFFFFE82C) // (SMC) Control Register for CS 2
3327 #define AT91C_SMC_CTRL5 (0xFFFFE85C) // (SMC) Control Register for CS 5
3328 #define AT91C_SMC_PULSE4 (0xFFFFE844) // (SMC) Pulse Register for CS 4
3329 #define AT91C_SMC_CTRL3 (0xFFFFE83C) // (SMC) Control Register for CS 3
3330 #define AT91C_SMC_CYCLE0 (0xFFFFE808) // (SMC) Cycle Register for CS 0
3331 #define AT91C_SMC_SETUP1 (0xFFFFE810) // (SMC) Setup Register for CS 1
3332 #define AT91C_SMC_SETUP4 (0xFFFFE840) // (SMC) Setup Register for CS 4
3333 #define AT91C_SMC_PULSE5 (0xFFFFE854) // (SMC) Pulse Register for CS 5
3334 #define AT91C_SMC_CYCLE3 (0xFFFFE838) // (SMC) Cycle Register for CS 3
3335 #define AT91C_SMC_SETUP7 (0xFFFFE870) // (SMC) Setup Register for CS 7
3336 #define AT91C_SMC_SETUP0 (0xFFFFE800) // (SMC) Setup Register for CS 0
3337 #define AT91C_SMC_CTRL4 (0xFFFFE84C) // (SMC) Control Register for CS 4
3338 #define AT91C_SMC_CYCLE5 (0xFFFFE858) // (SMC) Cycle Register for CS 5
3339 #define AT91C_SMC_PULSE0 (0xFFFFE804) // (SMC) Pulse Register for CS 0
3340 #define AT91C_SMC_PULSE3 (0xFFFFE834) // (SMC) Pulse Register for CS 3
3341 #define AT91C_SMC_CTRL6 (0xFFFFE86C) // (SMC) Control Register for CS 6
3342 #define AT91C_SMC_CYCLE4 (0xFFFFE848) // (SMC) Cycle Register for CS 4
3343 #define AT91C_SMC_CTRL7 (0xFFFFE87C) // (SMC) Control Register for CS 7
3344 // ========== Register definition for MATRIX_PRS peripheral ==========
3345 #define AT91C_MATRIX_PRS_PRAS (0xFFFFEA80) // (MATRIX_PRS) Slave Priority Registers A for Slave
3346 #define AT91C_MATRIX_PRS_PRBS (0xFFFFEA84) // (MATRIX_PRS) Slave Priority Registers B for Slave
3347 // ========== Register definition for MATRIX peripheral ==========
3348 #define AT91C_MATRIX_MCFG (0xFFFFEA00) // (MATRIX) Master Configuration Register
3349 #define AT91C_MATRIX_MRCR (0xFFFFEB00) // (MATRIX) Master Remp Control Register
3350 #define AT91C_MATRIX_SCFG (0xFFFFEA40) // (MATRIX) Slave Configuration Register
3351 // ========== Register definition for CCFG peripheral ==========
3352 #define AT91C_CCFG_MPBS1 (0xFFFFEB1C) // (CCFG) Slave 3 (MP Block Slave 1) Special Function Register
3353 #define AT91C_CCFG_BRIDGE (0xFFFFEB34) // (CCFG) Slave 8 (APB Bridge) Special Function Register
3354 #define AT91C_CCFG_MPBS3 (0xFFFFEB30) // (CCFG) Slave 7 (MP Block Slave 3) Special Function Register
3355 #define AT91C_CCFG_MPBS2 (0xFFFFEB2C) // (CCFG) Slave 7 (MP Block Slave 2) Special Function Register
3356 #define AT91C_CCFG_UDPHS (0xFFFFEB18) // (CCFG) Slave 2 (AHB Periphs) Special Function Register
3357 #define AT91C_CCFG_EBICSA (0xFFFFEB20) // (CCFG) EBI Chip Select Assignement Register
3358 #define AT91C_CCFG_MPBS0 (0xFFFFEB14) // (CCFG) Slave 1 (MP Block Slave 0) Special Function Register
3359 #define AT91C_CCFG_MATRIXVERSION (0xFFFFEBFC) // (CCFG) Version Register
3360 // ========== Register definition for PDC_DBGU peripheral ==========
3361 #define AT91C_DBGU_PTCR (0xFFFFEF20) // (PDC_DBGU) PDC Transfer Control Register
3362 #define AT91C_DBGU_RCR (0xFFFFEF04) // (PDC_DBGU) Receive Counter Register
3363 #define AT91C_DBGU_TCR (0xFFFFEF0C) // (PDC_DBGU) Transmit Counter Register
3364 #define AT91C_DBGU_RNCR (0xFFFFEF14) // (PDC_DBGU) Receive Next Counter Register
3365 #define AT91C_DBGU_TNPR (0xFFFFEF18) // (PDC_DBGU) Transmit Next Pointer Register
3366 #define AT91C_DBGU_RNPR (0xFFFFEF10) // (PDC_DBGU) Receive Next Pointer Register
3367 #define AT91C_DBGU_PTSR (0xFFFFEF24) // (PDC_DBGU) PDC Transfer Status Register
3368 #define AT91C_DBGU_RPR (0xFFFFEF00) // (PDC_DBGU) Receive Pointer Register
3369 #define AT91C_DBGU_TPR (0xFFFFEF08) // (PDC_DBGU) Transmit Pointer Register
3370 #define AT91C_DBGU_TNCR (0xFFFFEF1C) // (PDC_DBGU) Transmit Next Counter Register
3371 // ========== Register definition for DBGU peripheral ==========
3372 #define AT91C_DBGU_BRGR (0xFFFFEE20) // (DBGU) Baud Rate Generator Register
3373 #define AT91C_DBGU_CR (0xFFFFEE00) // (DBGU) Control Register
3374 #define AT91C_DBGU_THR (0xFFFFEE1C) // (DBGU) Transmitter Holding Register
3375 #define AT91C_DBGU_IDR (0xFFFFEE0C) // (DBGU) Interrupt Disable Register
3376 #define AT91C_DBGU_EXID (0xFFFFEE44) // (DBGU) Chip ID Extension Register
3377 #define AT91C_DBGU_IMR (0xFFFFEE10) // (DBGU) Interrupt Mask Register
3378 #define AT91C_DBGU_FNTR (0xFFFFEE48) // (DBGU) Force NTRST Register
3379 #define AT91C_DBGU_IER (0xFFFFEE08) // (DBGU) Interrupt Enable Register
3380 #define AT91C_DBGU_CSR (0xFFFFEE14) // (DBGU) Channel Status Register
3381 #define AT91C_DBGU_MR (0xFFFFEE04) // (DBGU) Mode Register
3382 #define AT91C_DBGU_RHR (0xFFFFEE18) // (DBGU) Receiver Holding Register
3383 #define AT91C_DBGU_CIDR (0xFFFFEE40) // (DBGU) Chip ID Register
3384 // ========== Register definition for AIC peripheral ==========
3385 #define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
3386 #define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register
3387 #define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
3388 #define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)
3389 #define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
3390 #define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register
3391 #define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register
3392 #define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
3393 #define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
3394 #define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
3395 #define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
3396 #define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register
3397 #define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
3398 #define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
3399 #define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register
3400 #define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
3401 #define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register
3402 #define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
3403 // ========== Register definition for PIOA peripheral ==========
3404 #define AT91C_PIOA_OWDR (0xFFFFF2A4) // (PIOA) Output Write Disable Register
3405 #define AT91C_PIOA_MDDR (0xFFFFF254) // (PIOA) Multi-driver Disable Register
3406 #define AT91C_PIOA_IFSR (0xFFFFF228) // (PIOA) Input Filter Status Register
3407 #define AT91C_PIOA_ISR (0xFFFFF24C) // (PIOA) Interrupt Status Register
3408 #define AT91C_PIOA_CODR (0xFFFFF234) // (PIOA) Clear Output Data Register
3409 #define AT91C_PIOA_PDR (0xFFFFF204) // (PIOA) PIO Disable Register
3410 #define AT91C_PIOA_OWSR (0xFFFFF2A8) // (PIOA) Output Write Status Register
3411 #define AT91C_PIOA_ASR (0xFFFFF270) // (PIOA) Select A Register
3412 #define AT91C_PIOA_PPUSR (0xFFFFF268) // (PIOA) Pull-up Status Register
3413 #define AT91C_PIOA_IMR (0xFFFFF248) // (PIOA) Interrupt Mask Register
3414 #define AT91C_PIOA_OSR (0xFFFFF218) // (PIOA) Output Status Register
3415 #define AT91C_PIOA_ABSR (0xFFFFF278) // (PIOA) AB Select Status Register
3416 #define AT91C_PIOA_MDER (0xFFFFF250) // (PIOA) Multi-driver Enable Register
3417 #define AT91C_PIOA_IFDR (0xFFFFF224) // (PIOA) Input Filter Disable Register
3418 #define AT91C_PIOA_PDSR (0xFFFFF23C) // (PIOA) Pin Data Status Register
3419 #define AT91C_PIOA_SODR (0xFFFFF230) // (PIOA) Set Output Data Register
3420 #define AT91C_PIOA_BSR (0xFFFFF274) // (PIOA) Select B Register
3421 #define AT91C_PIOA_OWER (0xFFFFF2A0) // (PIOA) Output Write Enable Register
3422 #define AT91C_PIOA_IFER (0xFFFFF220) // (PIOA) Input Filter Enable Register
3423 #define AT91C_PIOA_IDR (0xFFFFF244) // (PIOA) Interrupt Disable Register
3424 #define AT91C_PIOA_ODR (0xFFFFF214) // (PIOA) Output Disable Registerr
3425 #define AT91C_PIOA_IER (0xFFFFF240) // (PIOA) Interrupt Enable Register
3426 #define AT91C_PIOA_PPUER (0xFFFFF264) // (PIOA) Pull-up Enable Register
3427 #define AT91C_PIOA_MDSR (0xFFFFF258) // (PIOA) Multi-driver Status Register
3428 #define AT91C_PIOA_OER (0xFFFFF210) // (PIOA) Output Enable Register
3429 #define AT91C_PIOA_PER (0xFFFFF200) // (PIOA) PIO Enable Register
3430 #define AT91C_PIOA_PPUDR (0xFFFFF260) // (PIOA) Pull-up Disable Register
3431 #define AT91C_PIOA_ODSR (0xFFFFF238) // (PIOA) Output Data Status Register
3432 #define AT91C_PIOA_PSR (0xFFFFF208) // (PIOA) PIO Status Register
3433 // ========== Register definition for PIOB peripheral ==========
3434 #define AT91C_PIOB_ODR (0xFFFFF414) // (PIOB) Output Disable Registerr
3435 #define AT91C_PIOB_SODR (0xFFFFF430) // (PIOB) Set Output Data Register
3436 #define AT91C_PIOB_ISR (0xFFFFF44C) // (PIOB) Interrupt Status Register
3437 #define AT91C_PIOB_ABSR (0xFFFFF478) // (PIOB) AB Select Status Register
3438 #define AT91C_PIOB_IER (0xFFFFF440) // (PIOB) Interrupt Enable Register
3439 #define AT91C_PIOB_PPUDR (0xFFFFF460) // (PIOB) Pull-up Disable Register
3440 #define AT91C_PIOB_IMR (0xFFFFF448) // (PIOB) Interrupt Mask Register
3441 #define AT91C_PIOB_PER (0xFFFFF400) // (PIOB) PIO Enable Register
3442 #define AT91C_PIOB_IFDR (0xFFFFF424) // (PIOB) Input Filter Disable Register
3443 #define AT91C_PIOB_OWDR (0xFFFFF4A4) // (PIOB) Output Write Disable Register
3444 #define AT91C_PIOB_MDSR (0xFFFFF458) // (PIOB) Multi-driver Status Register
3445 #define AT91C_PIOB_IDR (0xFFFFF444) // (PIOB) Interrupt Disable Register
3446 #define AT91C_PIOB_ODSR (0xFFFFF438) // (PIOB) Output Data Status Register
3447 #define AT91C_PIOB_PPUSR (0xFFFFF468) // (PIOB) Pull-up Status Register
3448 #define AT91C_PIOB_OWSR (0xFFFFF4A8) // (PIOB) Output Write Status Register
3449 #define AT91C_PIOB_BSR (0xFFFFF474) // (PIOB) Select B Register
3450 #define AT91C_PIOB_OWER (0xFFFFF4A0) // (PIOB) Output Write Enable Register
3451 #define AT91C_PIOB_IFER (0xFFFFF420) // (PIOB) Input Filter Enable Register
3452 #define AT91C_PIOB_PDSR (0xFFFFF43C) // (PIOB) Pin Data Status Register
3453 #define AT91C_PIOB_PPUER (0xFFFFF464) // (PIOB) Pull-up Enable Register
3454 #define AT91C_PIOB_OSR (0xFFFFF418) // (PIOB) Output Status Register
3455 #define AT91C_PIOB_ASR (0xFFFFF470) // (PIOB) Select A Register
3456 #define AT91C_PIOB_MDDR (0xFFFFF454) // (PIOB) Multi-driver Disable Register
3457 #define AT91C_PIOB_CODR (0xFFFFF434) // (PIOB) Clear Output Data Register
3458 #define AT91C_PIOB_MDER (0xFFFFF450) // (PIOB) Multi-driver Enable Register
3459 #define AT91C_PIOB_PDR (0xFFFFF404) // (PIOB) PIO Disable Register
3460 #define AT91C_PIOB_IFSR (0xFFFFF428) // (PIOB) Input Filter Status Register
3461 #define AT91C_PIOB_OER (0xFFFFF410) // (PIOB) Output Enable Register
3462 #define AT91C_PIOB_PSR (0xFFFFF408) // (PIOB) PIO Status Register
3463 // ========== Register definition for PIOC peripheral ==========
3464 #define AT91C_PIOC_OWDR (0xFFFFF6A4) // (PIOC) Output Write Disable Register
3465 #define AT91C_PIOC_MDER (0xFFFFF650) // (PIOC) Multi-driver Enable Register
3466 #define AT91C_PIOC_PPUSR (0xFFFFF668) // (PIOC) Pull-up Status Register
3467 #define AT91C_PIOC_IMR (0xFFFFF648) // (PIOC) Interrupt Mask Register
3468 #define AT91C_PIOC_ASR (0xFFFFF670) // (PIOC) Select A Register
3469 #define AT91C_PIOC_PPUDR (0xFFFFF660) // (PIOC) Pull-up Disable Register
3470 #define AT91C_PIOC_PSR (0xFFFFF608) // (PIOC) PIO Status Register
3471 #define AT91C_PIOC_IER (0xFFFFF640) // (PIOC) Interrupt Enable Register
3472 #define AT91C_PIOC_CODR (0xFFFFF634) // (PIOC) Clear Output Data Register
3473 #define AT91C_PIOC_OWER (0xFFFFF6A0) // (PIOC) Output Write Enable Register
3474 #define AT91C_PIOC_ABSR (0xFFFFF678) // (PIOC) AB Select Status Register
3475 #define AT91C_PIOC_IFDR (0xFFFFF624) // (PIOC) Input Filter Disable Register
3476 #define AT91C_PIOC_PDSR (0xFFFFF63C) // (PIOC) Pin Data Status Register
3477 #define AT91C_PIOC_IDR (0xFFFFF644) // (PIOC) Interrupt Disable Register
3478 #define AT91C_PIOC_OWSR (0xFFFFF6A8) // (PIOC) Output Write Status Register
3479 #define AT91C_PIOC_PDR (0xFFFFF604) // (PIOC) PIO Disable Register
3480 #define AT91C_PIOC_ODR (0xFFFFF614) // (PIOC) Output Disable Registerr
3481 #define AT91C_PIOC_IFSR (0xFFFFF628) // (PIOC) Input Filter Status Register
3482 #define AT91C_PIOC_PPUER (0xFFFFF664) // (PIOC) Pull-up Enable Register
3483 #define AT91C_PIOC_SODR (0xFFFFF630) // (PIOC) Set Output Data Register
3484 #define AT91C_PIOC_ISR (0xFFFFF64C) // (PIOC) Interrupt Status Register
3485 #define AT91C_PIOC_ODSR (0xFFFFF638) // (PIOC) Output Data Status Register
3486 #define AT91C_PIOC_OSR (0xFFFFF618) // (PIOC) Output Status Register
3487 #define AT91C_PIOC_MDSR (0xFFFFF658) // (PIOC) Multi-driver Status Register
3488 #define AT91C_PIOC_IFER (0xFFFFF620) // (PIOC) Input Filter Enable Register
3489 #define AT91C_PIOC_BSR (0xFFFFF674) // (PIOC) Select B Register
3490 #define AT91C_PIOC_MDDR (0xFFFFF654) // (PIOC) Multi-driver Disable Register
3491 #define AT91C_PIOC_OER (0xFFFFF610) // (PIOC) Output Enable Register
3492 #define AT91C_PIOC_PER (0xFFFFF600) // (PIOC) PIO Enable Register
3493 // ========== Register definition for PIOD peripheral ==========
3494 #define AT91C_PIOD_OWDR (0xFFFFF8A4) // (PIOD) Output Write Disable Register
3495 #define AT91C_PIOD_SODR (0xFFFFF830) // (PIOD) Set Output Data Register
3496 #define AT91C_PIOD_PPUER (0xFFFFF864) // (PIOD) Pull-up Enable Register
3497 #define AT91C_PIOD_CODR (0xFFFFF834) // (PIOD) Clear Output Data Register
3498 #define AT91C_PIOD_PSR (0xFFFFF808) // (PIOD) PIO Status Register
3499 #define AT91C_PIOD_PDR (0xFFFFF804) // (PIOD) PIO Disable Register
3500 #define AT91C_PIOD_ODR (0xFFFFF814) // (PIOD) Output Disable Registerr
3501 #define AT91C_PIOD_PPUSR (0xFFFFF868) // (PIOD) Pull-up Status Register
3502 #define AT91C_PIOD_ABSR (0xFFFFF878) // (PIOD) AB Select Status Register
3503 #define AT91C_PIOD_IFSR (0xFFFFF828) // (PIOD) Input Filter Status Register
3504 #define AT91C_PIOD_OER (0xFFFFF810) // (PIOD) Output Enable Register
3505 #define AT91C_PIOD_IMR (0xFFFFF848) // (PIOD) Interrupt Mask Register
3506 #define AT91C_PIOD_ASR (0xFFFFF870) // (PIOD) Select A Register
3507 #define AT91C_PIOD_MDDR (0xFFFFF854) // (PIOD) Multi-driver Disable Register
3508 #define AT91C_PIOD_OWSR (0xFFFFF8A8) // (PIOD) Output Write Status Register
3509 #define AT91C_PIOD_PER (0xFFFFF800) // (PIOD) PIO Enable Register
3510 #define AT91C_PIOD_IDR (0xFFFFF844) // (PIOD) Interrupt Disable Register
3511 #define AT91C_PIOD_MDER (0xFFFFF850) // (PIOD) Multi-driver Enable Register
3512 #define AT91C_PIOD_PDSR (0xFFFFF83C) // (PIOD) Pin Data Status Register
3513 #define AT91C_PIOD_MDSR (0xFFFFF858) // (PIOD) Multi-driver Status Register
3514 #define AT91C_PIOD_OWER (0xFFFFF8A0) // (PIOD) Output Write Enable Register
3515 #define AT91C_PIOD_BSR (0xFFFFF874) // (PIOD) Select B Register
3516 #define AT91C_PIOD_PPUDR (0xFFFFF860) // (PIOD) Pull-up Disable Register
3517 #define AT91C_PIOD_IFDR (0xFFFFF824) // (PIOD) Input Filter Disable Register
3518 #define AT91C_PIOD_IER (0xFFFFF840) // (PIOD) Interrupt Enable Register
3519 #define AT91C_PIOD_OSR (0xFFFFF818) // (PIOD) Output Status Register
3520 #define AT91C_PIOD_ODSR (0xFFFFF838) // (PIOD) Output Data Status Register
3521 #define AT91C_PIOD_ISR (0xFFFFF84C) // (PIOD) Interrupt Status Register
3522 #define AT91C_PIOD_IFER (0xFFFFF820) // (PIOD) Input Filter Enable Register
3523 // ========== Register definition for CKGR peripheral ==========
3524 #define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register
3525 #define AT91C_CKGR_PLLBR (0xFFFFFC2C) // (CKGR) PLL B Register
3526 #define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register
3527 #define AT91C_CKGR_PLLAR (0xFFFFFC28) // (CKGR) PLL A Register
3528 #define AT91C_CKGR_UCKR (0xFFFFFC1C) // (CKGR) UTMI Clock Configuration Register
3529 // ========== Register definition for PMC peripheral ==========
3530 #define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
3531 #define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register
3532 #define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register
3533 #define AT91C_PMC_PLLAR (0xFFFFFC28) // (PMC) PLL A Register
3534 #define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
3535 #define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register
3536 #define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register
3537 #define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register
3538 #define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register
3539 #define AT91C_PMC_UCKR (0xFFFFFC1C) // (PMC) UTMI Clock Configuration Register
3540 #define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register
3541 #define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register
3542 #define AT91C_PMC_PLLBR (0xFFFFFC2C) // (PMC) PLL B Register
3543 #define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register
3544 #define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
3545 #define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register
3546 #define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register
3547 // ========== Register definition for RSTC peripheral ==========
3548 #define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register
3549 #define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register
3550 #define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register
3551 // ========== Register definition for SHDWC peripheral ==========
3552 #define AT91C_SHDWC_SHSR (0xFFFFFD18) // (SHDWC) Shut Down Status Register
3553 #define AT91C_SHDWC_SHMR (0xFFFFFD14) // (SHDWC) Shut Down Mode Register
3554 #define AT91C_SHDWC_SHCR (0xFFFFFD10) // (SHDWC) Shut Down Control Register
3555 // ========== Register definition for RTTC peripheral ==========
3556 #define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register
3557 #define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register
3558 #define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register
3559 #define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register
3560 // ========== Register definition for PITC peripheral ==========
3561 #define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register
3562 #define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register
3563 #define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register
3564 #define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register
3565 // ========== Register definition for WDTC peripheral ==========
3566 #define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register
3567 #define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register
3568 #define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register
3569 // ========== Register definition for UDP peripheral ==========
3570 #define AT91C_UDP_FDR (0xFFF78050) // (UDP) Endpoint FIFO Data Register
3571 #define AT91C_UDP_IER (0xFFF78010) // (UDP) Interrupt Enable Register
3572 #define AT91C_UDP_CSR (0xFFF78030) // (UDP) Endpoint Control and Status Register
3573 #define AT91C_UDP_RSTEP (0xFFF78028) // (UDP) Reset Endpoint Register
3574 #define AT91C_UDP_GLBSTATE (0xFFF78004) // (UDP) Global State Register
3575 #define AT91C_UDP_TXVC (0xFFF78074) // (UDP) Transceiver Control Register
3576 #define AT91C_UDP_IDR (0xFFF78014) // (UDP) Interrupt Disable Register
3577 #define AT91C_UDP_ISR (0xFFF7801C) // (UDP) Interrupt Status Register
3578 #define AT91C_UDP_IMR (0xFFF78018) // (UDP) Interrupt Mask Register
3579 #define AT91C_UDP_FADDR (0xFFF78008) // (UDP) Function Address Register
3580 #define AT91C_UDP_NUM (0xFFF78000) // (UDP) Frame Number Register
3581 #define AT91C_UDP_ICR (0xFFF78020) // (UDP) Interrupt Clear Register
3582 // ========== Register definition for UDPHS_EPTFIFO peripheral ==========
3583 #define AT91C_UDPHS_EPTFIFO_READEPTF (0x006F0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 15
3584 #define AT91C_UDPHS_EPTFIFO_READEPT5 (0x00650000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 5
3585 #define AT91C_UDPHS_EPTFIFO_READEPT1 (0x00610000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 1
3586 #define AT91C_UDPHS_EPTFIFO_READEPTE (0x006E0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 14
3587 #define AT91C_UDPHS_EPTFIFO_READEPT4 (0x00640000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 4
3588 #define AT91C_UDPHS_EPTFIFO_READEPTD (0x006D0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 13
3589 #define AT91C_UDPHS_EPTFIFO_READEPT2 (0x00620000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 2
3590 #define AT91C_UDPHS_EPTFIFO_READEPT6 (0x00660000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 6
3591 #define AT91C_UDPHS_EPTFIFO_READEPT9 (0x00690000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 9
3592 #define AT91C_UDPHS_EPTFIFO_READEPT0 (0x00600000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 0
3593 #define AT91C_UDPHS_EPTFIFO_READEPTA (0x006A0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 10
3594 #define AT91C_UDPHS_EPTFIFO_READEPT3 (0x00630000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 3
3595 #define AT91C_UDPHS_EPTFIFO_READEPTC (0x006C0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 12
3596 #define AT91C_UDPHS_EPTFIFO_READEPTB (0x006B0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 11
3597 #define AT91C_UDPHS_EPTFIFO_READEPT8 (0x00680000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 8
3598 #define AT91C_UDPHS_EPTFIFO_READEPT7 (0x00670000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 7
3599 // ========== Register definition for UDPHS_EPT_0 peripheral ==========
3600 #define AT91C_UDPHS_EPT_0_EPTSTA (0xFFF7811C) // (UDPHS_EPT_0) Endpoint Status Register
3601 #define AT91C_UDPHS_EPT_0_EPTCTL (0xFFF7810C) // (UDPHS_EPT_0) Endpoint Control Register
3602 #define AT91C_UDPHS_EPT_0_EPTCTLDIS (0xFFF78108) // (UDPHS_EPT_0) Endpoint Control Disable Register
3603 #define AT91C_UDPHS_EPT_0_EPTCFG (0xFFF78100) // (UDPHS_EPT_0) Endpoint Config Register
3604 #define AT91C_UDPHS_EPT_0_EPTCLRSTA (0xFFF78118) // (UDPHS_EPT_0) Endpoint Clear Status Register
3605 #define AT91C_UDPHS_EPT_0_EPTSETSTA (0xFFF78114) // (UDPHS_EPT_0) Endpoint Set Status Register
3606 #define AT91C_UDPHS_EPT_0_EPTCTLENB (0xFFF78104) // (UDPHS_EPT_0) Endpoint Control Enable Register
3607 // ========== Register definition for UDPHS_EPT_1 peripheral ==========
3608 #define AT91C_UDPHS_EPT_1_EPTCTLENB (0xFFF78124) // (UDPHS_EPT_1) Endpoint Control Enable Register
3609 #define AT91C_UDPHS_EPT_1_EPTCFG (0xFFF78120) // (UDPHS_EPT_1) Endpoint Config Register
3610 #define AT91C_UDPHS_EPT_1_EPTCTL (0xFFF7812C) // (UDPHS_EPT_1) Endpoint Control Register
3611 #define AT91C_UDPHS_EPT_1_EPTSTA (0xFFF7813C) // (UDPHS_EPT_1) Endpoint Status Register
3612 #define AT91C_UDPHS_EPT_1_EPTCLRSTA (0xFFF78138) // (UDPHS_EPT_1) Endpoint Clear Status Register
3613 #define AT91C_UDPHS_EPT_1_EPTSETSTA (0xFFF78134) // (UDPHS_EPT_1) Endpoint Set Status Register
3614 #define AT91C_UDPHS_EPT_1_EPTCTLDIS (0xFFF78128) // (UDPHS_EPT_1) Endpoint Control Disable Register
3615 // ========== Register definition for UDPHS_EPT_2 peripheral ==========
3616 #define AT91C_UDPHS_EPT_2_EPTCLRSTA (0xFFF78158) // (UDPHS_EPT_2) Endpoint Clear Status Register
3617 #define AT91C_UDPHS_EPT_2_EPTCTLDIS (0xFFF78148) // (UDPHS_EPT_2) Endpoint Control Disable Register
3618 #define AT91C_UDPHS_EPT_2_EPTSTA (0xFFF7815C) // (UDPHS_EPT_2) Endpoint Status Register
3619 #define AT91C_UDPHS_EPT_2_EPTSETSTA (0xFFF78154) // (UDPHS_EPT_2) Endpoint Set Status Register
3620 #define AT91C_UDPHS_EPT_2_EPTCTL (0xFFF7814C) // (UDPHS_EPT_2) Endpoint Control Register
3621 #define AT91C_UDPHS_EPT_2_EPTCFG (0xFFF78140) // (UDPHS_EPT_2) Endpoint Config Register
3622 #define AT91C_UDPHS_EPT_2_EPTCTLENB (0xFFF78144) // (UDPHS_EPT_2) Endpoint Control Enable Register
3623 // ========== Register definition for UDPHS_EPT_3 peripheral ==========
3624 #define AT91C_UDPHS_EPT_3_EPTCTL (0xFFF7816C) // (UDPHS_EPT_3) Endpoint Control Register
3625 #define AT91C_UDPHS_EPT_3_EPTCLRSTA (0xFFF78178) // (UDPHS_EPT_3) Endpoint Clear Status Register
3626 #define AT91C_UDPHS_EPT_3_EPTCTLDIS (0xFFF78168) // (UDPHS_EPT_3) Endpoint Control Disable Register
3627 #define AT91C_UDPHS_EPT_3_EPTSTA (0xFFF7817C) // (UDPHS_EPT_3) Endpoint Status Register
3628 #define AT91C_UDPHS_EPT_3_EPTSETSTA (0xFFF78174) // (UDPHS_EPT_3) Endpoint Set Status Register
3629 #define AT91C_UDPHS_EPT_3_EPTCTLENB (0xFFF78164) // (UDPHS_EPT_3) Endpoint Control Enable Register
3630 #define AT91C_UDPHS_EPT_3_EPTCFG (0xFFF78160) // (UDPHS_EPT_3) Endpoint Config Register
3631 // ========== Register definition for UDPHS_EPT_4 peripheral ==========
3632 #define AT91C_UDPHS_EPT_4_EPTCLRSTA (0xFFF78198) // (UDPHS_EPT_4) Endpoint Clear Status Register
3633 #define AT91C_UDPHS_EPT_4_EPTCTL (0xFFF7818C) // (UDPHS_EPT_4) Endpoint Control Register
3634 #define AT91C_UDPHS_EPT_4_EPTCTLENB (0xFFF78184) // (UDPHS_EPT_4) Endpoint Control Enable Register
3635 #define AT91C_UDPHS_EPT_4_EPTSTA (0xFFF7819C) // (UDPHS_EPT_4) Endpoint Status Register
3636 #define AT91C_UDPHS_EPT_4_EPTSETSTA (0xFFF78194) // (UDPHS_EPT_4) Endpoint Set Status Register
3637 #define AT91C_UDPHS_EPT_4_EPTCFG (0xFFF78180) // (UDPHS_EPT_4) Endpoint Config Register
3638 #define AT91C_UDPHS_EPT_4_EPTCTLDIS (0xFFF78188) // (UDPHS_EPT_4) Endpoint Control Disable Register
3639 // ========== Register definition for UDPHS_EPT_5 peripheral ==========
3640 #define AT91C_UDPHS_EPT_5_EPTSTA (0xFFF781BC) // (UDPHS_EPT_5) Endpoint Status Register
3641 #define AT91C_UDPHS_EPT_5_EPTCLRSTA (0xFFF781B8) // (UDPHS_EPT_5) Endpoint Clear Status Register
3642 #define AT91C_UDPHS_EPT_5_EPTCTLENB (0xFFF781A4) // (UDPHS_EPT_5) Endpoint Control Enable Register
3643 #define AT91C_UDPHS_EPT_5_EPTSETSTA (0xFFF781B4) // (UDPHS_EPT_5) Endpoint Set Status Register
3644 #define AT91C_UDPHS_EPT_5_EPTCTLDIS (0xFFF781A8) // (UDPHS_EPT_5) Endpoint Control Disable Register
3645 #define AT91C_UDPHS_EPT_5_EPTCFG (0xFFF781A0) // (UDPHS_EPT_5) Endpoint Config Register
3646 #define AT91C_UDPHS_EPT_5_EPTCTL (0xFFF781AC) // (UDPHS_EPT_5) Endpoint Control Register
3647 // ========== Register definition for UDPHS_EPT_6 peripheral ==========
3648 #define AT91C_UDPHS_EPT_6_EPTCLRSTA (0xFFF781D8) // (UDPHS_EPT_6) Endpoint Clear Status Register
3649 #define AT91C_UDPHS_EPT_6_EPTCTLENB (0xFFF781C4) // (UDPHS_EPT_6) Endpoint Control Enable Register
3650 #define AT91C_UDPHS_EPT_6_EPTCTL (0xFFF781CC) // (UDPHS_EPT_6) Endpoint Control Register
3651 #define AT91C_UDPHS_EPT_6_EPTSETSTA (0xFFF781D4) // (UDPHS_EPT_6) Endpoint Set Status Register
3652 #define AT91C_UDPHS_EPT_6_EPTCTLDIS (0xFFF781C8) // (UDPHS_EPT_6) Endpoint Control Disable Register
3653 #define AT91C_UDPHS_EPT_6_EPTSTA (0xFFF781DC) // (UDPHS_EPT_6) Endpoint Status Register
3654 #define AT91C_UDPHS_EPT_6_EPTCFG (0xFFF781C0) // (UDPHS_EPT_6) Endpoint Config Register
3655 // ========== Register definition for UDPHS_EPT_7 peripheral ==========
3656 #define AT91C_UDPHS_EPT_7_EPTSETSTA (0xFFF781F4) // (UDPHS_EPT_7) Endpoint Set Status Register
3657 #define AT91C_UDPHS_EPT_7_EPTCFG (0xFFF781E0) // (UDPHS_EPT_7) Endpoint Config Register
3658 #define AT91C_UDPHS_EPT_7_EPTSTA (0xFFF781FC) // (UDPHS_EPT_7) Endpoint Status Register
3659 #define AT91C_UDPHS_EPT_7_EPTCLRSTA (0xFFF781F8) // (UDPHS_EPT_7) Endpoint Clear Status Register
3660 #define AT91C_UDPHS_EPT_7_EPTCTL (0xFFF781EC) // (UDPHS_EPT_7) Endpoint Control Register
3661 #define AT91C_UDPHS_EPT_7_EPTCTLDIS (0xFFF781E8) // (UDPHS_EPT_7) Endpoint Control Disable Register
3662 #define AT91C_UDPHS_EPT_7_EPTCTLENB (0xFFF781E4) // (UDPHS_EPT_7) Endpoint Control Enable Register
3663 // ========== Register definition for UDPHS_EPT_8 peripheral ==========
3664 #define AT91C_UDPHS_EPT_8_EPTCTL (0xFFF7820C) // (UDPHS_EPT_8) Endpoint Control Register
3665 #define AT91C_UDPHS_EPT_8_EPTSTA (0xFFF7821C) // (UDPHS_EPT_8) Endpoint Status Register
3666 #define AT91C_UDPHS_EPT_8_EPTCLRSTA (0xFFF78218) // (UDPHS_EPT_8) Endpoint Clear Status Register
3667 #define AT91C_UDPHS_EPT_8_EPTCFG (0xFFF78200) // (UDPHS_EPT_8) Endpoint Config Register
3668 #define AT91C_UDPHS_EPT_8_EPTSETSTA (0xFFF78214) // (UDPHS_EPT_8) Endpoint Set Status Register
3669 #define AT91C_UDPHS_EPT_8_EPTCTLENB (0xFFF78204) // (UDPHS_EPT_8) Endpoint Control Enable Register
3670 #define AT91C_UDPHS_EPT_8_EPTCTLDIS (0xFFF78208) // (UDPHS_EPT_8) Endpoint Control Disable Register
3671 // ========== Register definition for UDPHS_EPT_9 peripheral ==========
3672 #define AT91C_UDPHS_EPT_9_EPTCLRSTA (0xFFF78238) // (UDPHS_EPT_9) Endpoint Clear Status Register
3673 #define AT91C_UDPHS_EPT_9_EPTSETSTA (0xFFF78234) // (UDPHS_EPT_9) Endpoint Set Status Register
3674 #define AT91C_UDPHS_EPT_9_EPTCFG (0xFFF78220) // (UDPHS_EPT_9) Endpoint Config Register
3675 #define AT91C_UDPHS_EPT_9_EPTSTA (0xFFF7823C) // (UDPHS_EPT_9) Endpoint Status Register
3676 #define AT91C_UDPHS_EPT_9_EPTCTLDIS (0xFFF78228) // (UDPHS_EPT_9) Endpoint Control Disable Register
3677 #define AT91C_UDPHS_EPT_9_EPTCTLENB (0xFFF78224) // (UDPHS_EPT_9) Endpoint Control Enable Register
3678 #define AT91C_UDPHS_EPT_9_EPTCTL (0xFFF7822C) // (UDPHS_EPT_9) Endpoint Control Register
3679 // ========== Register definition for UDPHS_EPT_10 peripheral ==========
3680 #define AT91C_UDPHS_EPT_10_EPTCTLDIS (0xFFF78248) // (UDPHS_EPT_10) Endpoint Control Disable Register
3681 #define AT91C_UDPHS_EPT_10_EPTCFG (0xFFF78240) // (UDPHS_EPT_10) Endpoint Config Register
3682 #define AT91C_UDPHS_EPT_10_EPTSTA (0xFFF7825C) // (UDPHS_EPT_10) Endpoint Status Register
3683 #define AT91C_UDPHS_EPT_10_EPTCLRSTA (0xFFF78258) // (UDPHS_EPT_10) Endpoint Clear Status Register
3684 #define AT91C_UDPHS_EPT_10_EPTCTLENB (0xFFF78244) // (UDPHS_EPT_10) Endpoint Control Enable Register
3685 #define AT91C_UDPHS_EPT_10_EPTSETSTA (0xFFF78254) // (UDPHS_EPT_10) Endpoint Set Status Register
3686 #define AT91C_UDPHS_EPT_10_EPTCTL (0xFFF7824C) // (UDPHS_EPT_10) Endpoint Control Register
3687 // ========== Register definition for UDPHS_EPT_11 peripheral ==========
3688 #define AT91C_UDPHS_EPT_11_EPTCTLDIS (0xFFF78268) // (UDPHS_EPT_11) Endpoint Control Disable Register
3689 #define AT91C_UDPHS_EPT_11_EPTCLRSTA (0xFFF78278) // (UDPHS_EPT_11) Endpoint Clear Status Register
3690 #define AT91C_UDPHS_EPT_11_EPTCTLENB (0xFFF78264) // (UDPHS_EPT_11) Endpoint Control Enable Register
3691 #define AT91C_UDPHS_EPT_11_EPTCTL (0xFFF7826C) // (UDPHS_EPT_11) Endpoint Control Register
3692 #define AT91C_UDPHS_EPT_11_EPTSTA (0xFFF7827C) // (UDPHS_EPT_11) Endpoint Status Register
3693 #define AT91C_UDPHS_EPT_11_EPTSETSTA (0xFFF78274) // (UDPHS_EPT_11) Endpoint Set Status Register
3694 #define AT91C_UDPHS_EPT_11_EPTCFG (0xFFF78260) // (UDPHS_EPT_11) Endpoint Config Register
3695 // ========== Register definition for UDPHS_EPT_12 peripheral ==========
3696 #define AT91C_UDPHS_EPT_12_EPTCTLENB (0xFFF78284) // (UDPHS_EPT_12) Endpoint Control Enable Register
3697 #define AT91C_UDPHS_EPT_12_EPTCLRSTA (0xFFF78298) // (UDPHS_EPT_12) Endpoint Clear Status Register
3698 #define AT91C_UDPHS_EPT_12_EPTCFG (0xFFF78280) // (UDPHS_EPT_12) Endpoint Config Register
3699 #define AT91C_UDPHS_EPT_12_EPTSTA (0xFFF7829C) // (UDPHS_EPT_12) Endpoint Status Register
3700 #define AT91C_UDPHS_EPT_12_EPTCTL (0xFFF7828C) // (UDPHS_EPT_12) Endpoint Control Register
3701 #define AT91C_UDPHS_EPT_12_EPTSETSTA (0xFFF78294) // (UDPHS_EPT_12) Endpoint Set Status Register
3702 #define AT91C_UDPHS_EPT_12_EPTCTLDIS (0xFFF78288) // (UDPHS_EPT_12) Endpoint Control Disable Register
3703 // ========== Register definition for UDPHS_EPT_13 peripheral ==========
3704 #define AT91C_UDPHS_EPT_13_EPTCTLENB (0xFFF782A4) // (UDPHS_EPT_13) Endpoint Control Enable Register
3705 #define AT91C_UDPHS_EPT_13_EPTCTL (0xFFF782AC) // (UDPHS_EPT_13) Endpoint Control Register
3706 #define AT91C_UDPHS_EPT_13_EPTCLRSTA (0xFFF782B8) // (UDPHS_EPT_13) Endpoint Clear Status Register
3707 #define AT91C_UDPHS_EPT_13_EPTCTLDIS (0xFFF782A8) // (UDPHS_EPT_13) Endpoint Control Disable Register
3708 #define AT91C_UDPHS_EPT_13_EPTSETSTA (0xFFF782B4) // (UDPHS_EPT_13) Endpoint Set Status Register
3709 #define AT91C_UDPHS_EPT_13_EPTCFG (0xFFF782A0) // (UDPHS_EPT_13) Endpoint Config Register
3710 #define AT91C_UDPHS_EPT_13_EPTSTA (0xFFF782BC) // (UDPHS_EPT_13) Endpoint Status Register
3711 // ========== Register definition for UDPHS_EPT_14 peripheral ==========
3712 #define AT91C_UDPHS_EPT_14_EPTSETSTA (0xFFF782D4) // (UDPHS_EPT_14) Endpoint Set Status Register
3713 #define AT91C_UDPHS_EPT_14_EPTSTA (0xFFF782DC) // (UDPHS_EPT_14) Endpoint Status Register
3714 #define AT91C_UDPHS_EPT_14_EPTCFG (0xFFF782C0) // (UDPHS_EPT_14) Endpoint Config Register
3715 #define AT91C_UDPHS_EPT_14_EPTCTL (0xFFF782CC) // (UDPHS_EPT_14) Endpoint Control Register
3716 #define AT91C_UDPHS_EPT_14_EPTCTLENB (0xFFF782C4) // (UDPHS_EPT_14) Endpoint Control Enable Register
3717 #define AT91C_UDPHS_EPT_14_EPTCLRSTA (0xFFF782D8) // (UDPHS_EPT_14) Endpoint Clear Status Register
3718 #define AT91C_UDPHS_EPT_14_EPTCTLDIS (0xFFF782C8) // (UDPHS_EPT_14) Endpoint Control Disable Register
3719 // ========== Register definition for UDPHS_EPT_15 peripheral ==========
3720 #define AT91C_UDPHS_EPT_15_EPTCTLDIS (0xFFF782E8) // (UDPHS_EPT_15) Endpoint Control Disable Register
3721 #define AT91C_UDPHS_EPT_15_EPTSETSTA (0xFFF782F4) // (UDPHS_EPT_15) Endpoint Set Status Register
3722 #define AT91C_UDPHS_EPT_15_EPTCTLENB (0xFFF782E4) // (UDPHS_EPT_15) Endpoint Control Enable Register
3723 #define AT91C_UDPHS_EPT_15_EPTCLRSTA (0xFFF782F8) // (UDPHS_EPT_15) Endpoint Clear Status Register
3724 #define AT91C_UDPHS_EPT_15_EPTSTA (0xFFF782FC) // (UDPHS_EPT_15) Endpoint Status Register
3725 #define AT91C_UDPHS_EPT_15_EPTCTL (0xFFF782EC) // (UDPHS_EPT_15) Endpoint Control Register
3726 #define AT91C_UDPHS_EPT_15_EPTCFG (0xFFF782E0) // (UDPHS_EPT_15) Endpoint Config Register
3727 // ========== Register definition for UDPHS_DMA_1 peripheral ==========
3728 #define AT91C_UDPHS_DMA_1_DMASTATUS (0xFFF7831C) // (UDPHS_DMA_1) DMA Channel Status Register
3729 #define AT91C_UDPHS_DMA_1_DMANXTDSC (0xFFF78310) // (UDPHS_DMA_1) DMA Channel Next Descriptor Address
3730 #define AT91C_UDPHS_DMA_1_DMACONTROL (0xFFF78318) // (UDPHS_DMA_1) DMA Channel Control Register
3731 #define AT91C_UDPHS_DMA_1_DMAADDRESS (0xFFF78314) // (UDPHS_DMA_1) DMA Channel AHB1 Address Register
3732 // ========== Register definition for UDPHS_DMA_2 peripheral ==========
3733 #define AT91C_UDPHS_DMA_2_DMACONTROL (0xFFF78328) // (UDPHS_DMA_2) DMA Channel Control Register
3734 #define AT91C_UDPHS_DMA_2_DMASTATUS (0xFFF7832C) // (UDPHS_DMA_2) DMA Channel Status Register
3735 #define AT91C_UDPHS_DMA_2_DMAADDRESS (0xFFF78324) // (UDPHS_DMA_2) DMA Channel AHB1 Address Register
3736 #define AT91C_UDPHS_DMA_2_DMANXTDSC (0xFFF78320) // (UDPHS_DMA_2) DMA Channel Next Descriptor Address
3737 // ========== Register definition for UDPHS_DMA_3 peripheral ==========
3738 #define AT91C_UDPHS_DMA_3_DMAADDRESS (0xFFF78334) // (UDPHS_DMA_3) DMA Channel AHB1 Address Register
3739 #define AT91C_UDPHS_DMA_3_DMANXTDSC (0xFFF78330) // (UDPHS_DMA_3) DMA Channel Next Descriptor Address
3740 #define AT91C_UDPHS_DMA_3_DMACONTROL (0xFFF78338) // (UDPHS_DMA_3) DMA Channel Control Register
3741 #define AT91C_UDPHS_DMA_3_DMASTATUS (0xFFF7833C) // (UDPHS_DMA_3) DMA Channel Status Register
3742 // ========== Register definition for UDPHS_DMA_4 peripheral ==========
3743 #define AT91C_UDPHS_DMA_4_DMANXTDSC (0xFFF78340) // (UDPHS_DMA_4) DMA Channel Next Descriptor Address
3744 #define AT91C_UDPHS_DMA_4_DMAADDRESS (0xFFF78344) // (UDPHS_DMA_4) DMA Channel AHB1 Address Register
3745 #define AT91C_UDPHS_DMA_4_DMACONTROL (0xFFF78348) // (UDPHS_DMA_4) DMA Channel Control Register
3746 #define AT91C_UDPHS_DMA_4_DMASTATUS (0xFFF7834C) // (UDPHS_DMA_4) DMA Channel Status Register
3747 // ========== Register definition for UDPHS_DMA_5 peripheral ==========
3748 #define AT91C_UDPHS_DMA_5_DMASTATUS (0xFFF7835C) // (UDPHS_DMA_5) DMA Channel Status Register
3749 #define AT91C_UDPHS_DMA_5_DMACONTROL (0xFFF78358) // (UDPHS_DMA_5) DMA Channel Control Register
3750 #define AT91C_UDPHS_DMA_5_DMANXTDSC (0xFFF78350) // (UDPHS_DMA_5) DMA Channel Next Descriptor Address
3751 #define AT91C_UDPHS_DMA_5_DMAADDRESS (0xFFF78354) // (UDPHS_DMA_5) DMA Channel AHB1 Address Register
3752 // ========== Register definition for UDPHS_DMA_6 peripheral ==========
3753 #define AT91C_UDPHS_DMA_6_DMANXTDSC (0xFFF78360) // (UDPHS_DMA_6) DMA Channel Next Descriptor Address
3754 #define AT91C_UDPHS_DMA_6_DMACONTROL (0xFFF78368) // (UDPHS_DMA_6) DMA Channel Control Register
3755 #define AT91C_UDPHS_DMA_6_DMASTATUS (0xFFF7836C) // (UDPHS_DMA_6) DMA Channel Status Register
3756 #define AT91C_UDPHS_DMA_6_DMAADDRESS (0xFFF78364) // (UDPHS_DMA_6) DMA Channel AHB1 Address Register
3757 // ========== Register definition for UDPHS_DMA_7 peripheral ==========
3758 #define AT91C_UDPHS_DMA_7_DMANXTDSC (0xFFF78370) // (UDPHS_DMA_7) DMA Channel Next Descriptor Address
3759 #define AT91C_UDPHS_DMA_7_DMAADDRESS (0xFFF78374) // (UDPHS_DMA_7) DMA Channel AHB1 Address Register
3760 #define AT91C_UDPHS_DMA_7_DMACONTROL (0xFFF78378) // (UDPHS_DMA_7) DMA Channel Control Register
3761 #define AT91C_UDPHS_DMA_7_DMASTATUS (0xFFF7837C) // (UDPHS_DMA_7) DMA Channel Status Register
3762 // ========== Register definition for UDPHS peripheral ==========
3763 #define AT91C_UDPHS_IEN (0xFFF78010) // (UDPHS) USB Interrupt Enable Register
3764 #define AT91C_UDPHS_IPFEATURES (0xFFF780F8) // (UDPHS) HUSB2DEV Features Register
3765 #define AT91C_UDPHS_TST (0xFFF780E0) // (UDPHS) USB Test Register
3766 #define AT91C_UDPHS_FNUM (0xFFF78004) // (UDPHS) USB Frame Number Register
3767 #define AT91C_UDPHS_TSTCNTB (0xFFF780D8) // (UDPHS) USB Test CounterB Register
3768 #define AT91C_UDPHS_IPPADDRSIZE (0xFFF780EC) // (UDPHS) HUSB2DEV PADDRSIZE Register
3769 #define AT91C_UDPHS_INTSTA (0xFFF78014) // (UDPHS) USB Interrupt Status Register
3770 #define AT91C_UDPHS_EPTRST (0xFFF7801C) // (UDPHS) USB Endpoints Reset Register
3771 #define AT91C_UDPHS_TSTCNTA (0xFFF780D4) // (UDPHS) USB Test CounterA Register
3772 #define AT91C_UDPHS_IPNAME2 (0xFFF780F4) // (UDPHS) HUSB2DEV Name2 Register
3773 #define AT91C_UDPHS_IPNAME1 (0xFFF780F0) // (UDPHS) HUSB2DEV Name1 Register
3774 #define AT91C_UDPHS_CLRINT (0xFFF78018) // (UDPHS) USB Clear Interrupt Register
3775 #define AT91C_UDPHS_IPVERSION (0xFFF780FC) // (UDPHS) HUSB2DEV Version Register
3776 #define AT91C_UDPHS_CTRL (0xFFF78000) // (UDPHS) USB Control Register
3777 // ========== Register definition for TC0 peripheral ==========
3778 #define AT91C_TC0_IER (0xFFF7C024) // (TC0) Interrupt Enable Register
3779 #define AT91C_TC0_IMR (0xFFF7C02C) // (TC0) Interrupt Mask Register
3780 #define AT91C_TC0_CCR (0xFFF7C000) // (TC0) Channel Control Register
3781 #define AT91C_TC0_RB (0xFFF7C018) // (TC0) Register B
3782 #define AT91C_TC0_CV (0xFFF7C010) // (TC0) Counter Value
3783 #define AT91C_TC0_SR (0xFFF7C020) // (TC0) Status Register
3784 #define AT91C_TC0_CMR (0xFFF7C004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
3785 #define AT91C_TC0_RA (0xFFF7C014) // (TC0) Register A
3786 #define AT91C_TC0_RC (0xFFF7C01C) // (TC0) Register C
3787 #define AT91C_TC0_IDR (0xFFF7C028) // (TC0) Interrupt Disable Register
3788 // ========== Register definition for TC1 peripheral ==========
3789 #define AT91C_TC1_IER (0xFFF7C064) // (TC1) Interrupt Enable Register
3790 #define AT91C_TC1_SR (0xFFF7C060) // (TC1) Status Register
3791 #define AT91C_TC1_RC (0xFFF7C05C) // (TC1) Register C
3792 #define AT91C_TC1_CV (0xFFF7C050) // (TC1) Counter Value
3793 #define AT91C_TC1_RA (0xFFF7C054) // (TC1) Register A
3794 #define AT91C_TC1_CMR (0xFFF7C044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
3795 #define AT91C_TC1_IDR (0xFFF7C068) // (TC1) Interrupt Disable Register
3796 #define AT91C_TC1_RB (0xFFF7C058) // (TC1) Register B
3797 #define AT91C_TC1_IMR (0xFFF7C06C) // (TC1) Interrupt Mask Register
3798 #define AT91C_TC1_CCR (0xFFF7C040) // (TC1) Channel Control Register
3799 // ========== Register definition for TC2 peripheral ==========
3800 #define AT91C_TC2_SR (0xFFF7C0A0) // (TC2) Status Register
3801 #define AT91C_TC2_IMR (0xFFF7C0AC) // (TC2) Interrupt Mask Register
3802 #define AT91C_TC2_IER (0xFFF7C0A4) // (TC2) Interrupt Enable Register
3803 #define AT91C_TC2_CV (0xFFF7C090) // (TC2) Counter Value
3804 #define AT91C_TC2_RB (0xFFF7C098) // (TC2) Register B
3805 #define AT91C_TC2_CCR (0xFFF7C080) // (TC2) Channel Control Register
3806 #define AT91C_TC2_CMR (0xFFF7C084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
3807 #define AT91C_TC2_RA (0xFFF7C094) // (TC2) Register A
3808 #define AT91C_TC2_IDR (0xFFF7C0A8) // (TC2) Interrupt Disable Register
3809 #define AT91C_TC2_RC (0xFFF7C09C) // (TC2) Register C
3810 // ========== Register definition for TCB0 peripheral ==========
3811 #define AT91C_TCB0_BCR (0xFFF7C0C0) // (TCB0) TC Block Control Register
3812 #define AT91C_TCB0_BMR (0xFFF7C0C4) // (TCB0) TC Block Mode Register
3813 // ========== Register definition for TCB1 peripheral ==========
3814 #define AT91C_TCB1_BMR (0xFFF7C104) // (TCB1) TC Block Mode Register
3815 #define AT91C_TCB1_BCR (0xFFF7C100) // (TCB1) TC Block Control Register
3816 // ========== Register definition for TCB2 peripheral ==========
3817 #define AT91C_TCB2_BCR (0xFFF7C140) // (TCB2) TC Block Control Register
3818 #define AT91C_TCB2_BMR (0xFFF7C144) // (TCB2) TC Block Mode Register
3819 // ========== Register definition for PDC_MCI0 peripheral ==========
3820 #define AT91C_MCI0_TCR (0xFFF8010C) // (PDC_MCI0) Transmit Counter Register
3821 #define AT91C_MCI0_TNCR (0xFFF8011C) // (PDC_MCI0) Transmit Next Counter Register
3822 #define AT91C_MCI0_RNPR (0xFFF80110) // (PDC_MCI0) Receive Next Pointer Register
3823 #define AT91C_MCI0_TPR (0xFFF80108) // (PDC_MCI0) Transmit Pointer Register
3824 #define AT91C_MCI0_TNPR (0xFFF80118) // (PDC_MCI0) Transmit Next Pointer Register
3825 #define AT91C_MCI0_PTSR (0xFFF80124) // (PDC_MCI0) PDC Transfer Status Register
3826 #define AT91C_MCI0_RCR (0xFFF80104) // (PDC_MCI0) Receive Counter Register
3827 #define AT91C_MCI0_PTCR (0xFFF80120) // (PDC_MCI0) PDC Transfer Control Register
3828 #define AT91C_MCI0_RPR (0xFFF80100) // (PDC_MCI0) Receive Pointer Register
3829 #define AT91C_MCI0_RNCR (0xFFF80114) // (PDC_MCI0) Receive Next Counter Register
3830 // ========== Register definition for MCI0 peripheral ==========
3831 #define AT91C_MCI0_CMDR (0xFFF80014) // (MCI0) MCI Command Register
3832 #define AT91C_MCI0_IMR (0xFFF8004C) // (MCI0) MCI Interrupt Mask Register
3833 #define AT91C_MCI0_MR (0xFFF80004) // (MCI0) MCI Mode Register
3834 #define AT91C_MCI0_CR (0xFFF80000) // (MCI0) MCI Control Register
3835 #define AT91C_MCI0_IER (0xFFF80044) // (MCI0) MCI Interrupt Enable Register
3836 #define AT91C_MCI0_RDR (0xFFF80030) // (MCI0) MCI Receive Data Register
3837 #define AT91C_MCI0_SR (0xFFF80040) // (MCI0) MCI Status Register
3838 #define AT91C_MCI0_DTOR (0xFFF80008) // (MCI0) MCI Data Timeout Register
3839 #define AT91C_MCI0_SDCR (0xFFF8000C) // (MCI0) MCI SD Card Register
3840 #define AT91C_MCI0_BLKR (0xFFF80018) // (MCI0) MCI Block Register
3841 #define AT91C_MCI0_VR (0xFFF800FC) // (MCI0) MCI Version Register
3842 #define AT91C_MCI0_TDR (0xFFF80034) // (MCI0) MCI Transmit Data Register
3843 #define AT91C_MCI0_ARGR (0xFFF80010) // (MCI0) MCI Argument Register
3844 #define AT91C_MCI0_RSPR (0xFFF80020) // (MCI0) MCI Response Register
3845 #define AT91C_MCI0_IDR (0xFFF80048) // (MCI0) MCI Interrupt Disable Register
3846 // ========== Register definition for PDC_MCI1 peripheral ==========
3847 #define AT91C_MCI1_PTCR (0xFFF84120) // (PDC_MCI1) PDC Transfer Control Register
3848 #define AT91C_MCI1_PTSR (0xFFF84124) // (PDC_MCI1) PDC Transfer Status Register
3849 #define AT91C_MCI1_TPR (0xFFF84108) // (PDC_MCI1) Transmit Pointer Register
3850 #define AT91C_MCI1_RPR (0xFFF84100) // (PDC_MCI1) Receive Pointer Register
3851 #define AT91C_MCI1_TNCR (0xFFF8411C) // (PDC_MCI1) Transmit Next Counter Register
3852 #define AT91C_MCI1_RCR (0xFFF84104) // (PDC_MCI1) Receive Counter Register
3853 #define AT91C_MCI1_TNPR (0xFFF84118) // (PDC_MCI1) Transmit Next Pointer Register
3854 #define AT91C_MCI1_TCR (0xFFF8410C) // (PDC_MCI1) Transmit Counter Register
3855 #define AT91C_MCI1_RNPR (0xFFF84110) // (PDC_MCI1) Receive Next Pointer Register
3856 #define AT91C_MCI1_RNCR (0xFFF84114) // (PDC_MCI1) Receive Next Counter Register
3857 // ========== Register definition for MCI1 peripheral ==========
3858 #define AT91C_MCI1_SR (0xFFF84040) // (MCI1) MCI Status Register
3859 #define AT91C_MCI1_RDR (0xFFF84030) // (MCI1) MCI Receive Data Register
3860 #define AT91C_MCI1_RSPR (0xFFF84020) // (MCI1) MCI Response Register
3861 #define AT91C_MCI1_CMDR (0xFFF84014) // (MCI1) MCI Command Register
3862 #define AT91C_MCI1_IMR (0xFFF8404C) // (MCI1) MCI Interrupt Mask Register
3863 #define AT91C_MCI1_DTOR (0xFFF84008) // (MCI1) MCI Data Timeout Register
3864 #define AT91C_MCI1_SDCR (0xFFF8400C) // (MCI1) MCI SD Card Register
3865 #define AT91C_MCI1_IDR (0xFFF84048) // (MCI1) MCI Interrupt Disable Register
3866 #define AT91C_MCI1_ARGR (0xFFF84010) // (MCI1) MCI Argument Register
3867 #define AT91C_MCI1_TDR (0xFFF84034) // (MCI1) MCI Transmit Data Register
3868 #define AT91C_MCI1_BLKR (0xFFF84018) // (MCI1) MCI Block Register
3869 #define AT91C_MCI1_VR (0xFFF840FC) // (MCI1) MCI Version Register
3870 #define AT91C_MCI1_CR (0xFFF84000) // (MCI1) MCI Control Register
3871 #define AT91C_MCI1_MR (0xFFF84004) // (MCI1) MCI Mode Register
3872 #define AT91C_MCI1_IER (0xFFF84044) // (MCI1) MCI Interrupt Enable Register
3873 // ========== Register definition for PDC_TWI peripheral ==========
3874 #define AT91C_TWI_PTSR (0xFFF88124) // (PDC_TWI) PDC Transfer Status Register
3875 #define AT91C_TWI_RNCR (0xFFF88114) // (PDC_TWI) Receive Next Counter Register
3876 #define AT91C_TWI_RCR (0xFFF88104) // (PDC_TWI) Receive Counter Register
3877 #define AT91C_TWI_RNPR (0xFFF88110) // (PDC_TWI) Receive Next Pointer Register
3878 #define AT91C_TWI_TCR (0xFFF8810C) // (PDC_TWI) Transmit Counter Register
3879 #define AT91C_TWI_RPR (0xFFF88100) // (PDC_TWI) Receive Pointer Register
3880 #define AT91C_TWI_PTCR (0xFFF88120) // (PDC_TWI) PDC Transfer Control Register
3881 #define AT91C_TWI_TPR (0xFFF88108) // (PDC_TWI) Transmit Pointer Register
3882 #define AT91C_TWI_TNPR (0xFFF88118) // (PDC_TWI) Transmit Next Pointer Register
3883 #define AT91C_TWI_TNCR (0xFFF8811C) // (PDC_TWI) Transmit Next Counter Register
3884 // ========== Register definition for TWI peripheral ==========
3885 #define AT91C_TWI_IDR (0xFFF88028) // (TWI) Interrupt Disable Register
3886 #define AT91C_TWI_RHR (0xFFF88030) // (TWI) Receive Holding Register
3887 #define AT91C_TWI_IMR (0xFFF8802C) // (TWI) Interrupt Mask Register
3888 #define AT91C_TWI_THR (0xFFF88034) // (TWI) Transmit Holding Register
3889 #define AT91C_TWI_IER (0xFFF88024) // (TWI) Interrupt Enable Register
3890 #define AT91C_TWI_IADR (0xFFF8800C) // (TWI) Internal Address Register
3891 #define AT91C_TWI_SMR (0xFFF88008) // (TWI) Slave Mode Register
3892 #define AT91C_TWI_MMR (0xFFF88004) // (TWI) Master Mode Register
3893 #define AT91C_TWI_CR (0xFFF88000) // (TWI) Control Register
3894 #define AT91C_TWI_SR (0xFFF88020) // (TWI) Status Register
3895 #define AT91C_TWI_CWGR (0xFFF88010) // (TWI) Clock Waveform Generator Register
3896 // ========== Register definition for PDC_US0 peripheral ==========
3897 #define AT91C_US0_TNPR (0xFFF8C118) // (PDC_US0) Transmit Next Pointer Register
3898 #define AT91C_US0_PTSR (0xFFF8C124) // (PDC_US0) PDC Transfer Status Register
3899 #define AT91C_US0_PTCR (0xFFF8C120) // (PDC_US0) PDC Transfer Control Register
3900 #define AT91C_US0_RNCR (0xFFF8C114) // (PDC_US0) Receive Next Counter Register
3901 #define AT91C_US0_RCR (0xFFF8C104) // (PDC_US0) Receive Counter Register
3902 #define AT91C_US0_TNCR (0xFFF8C11C) // (PDC_US0) Transmit Next Counter Register
3903 #define AT91C_US0_TCR (0xFFF8C10C) // (PDC_US0) Transmit Counter Register
3904 #define AT91C_US0_RNPR (0xFFF8C110) // (PDC_US0) Receive Next Pointer Register
3905 #define AT91C_US0_RPR (0xFFF8C100) // (PDC_US0) Receive Pointer Register
3906 #define AT91C_US0_TPR (0xFFF8C108) // (PDC_US0) Transmit Pointer Register
3907 // ========== Register definition for US0 peripheral ==========
3908 #define AT91C_US0_RTOR (0xFFF8C024) // (US0) Receiver Time-out Register
3909 #define AT91C_US0_NER (0xFFF8C044) // (US0) Nb Errors Register
3910 #define AT91C_US0_THR (0xFFF8C01C) // (US0) Transmitter Holding Register
3911 #define AT91C_US0_MR (0xFFF8C004) // (US0) Mode Register
3912 #define AT91C_US0_RHR (0xFFF8C018) // (US0) Receiver Holding Register
3913 #define AT91C_US0_CSR (0xFFF8C014) // (US0) Channel Status Register
3914 #define AT91C_US0_IMR (0xFFF8C010) // (US0) Interrupt Mask Register
3915 #define AT91C_US0_IDR (0xFFF8C00C) // (US0) Interrupt Disable Register
3916 #define AT91C_US0_FIDI (0xFFF8C040) // (US0) FI_DI_Ratio Register
3917 #define AT91C_US0_CR (0xFFF8C000) // (US0) Control Register
3918 #define AT91C_US0_IER (0xFFF8C008) // (US0) Interrupt Enable Register
3919 #define AT91C_US0_TTGR (0xFFF8C028) // (US0) Transmitter Time-guard Register
3920 #define AT91C_US0_BRGR (0xFFF8C020) // (US0) Baud Rate Generator Register
3921 #define AT91C_US0_IF (0xFFF8C04C) // (US0) IRDA_FILTER Register
3922 // ========== Register definition for PDC_US1 peripheral ==========
3923 #define AT91C_US1_PTCR (0xFFF90120) // (PDC_US1) PDC Transfer Control Register
3924 #define AT91C_US1_TNCR (0xFFF9011C) // (PDC_US1) Transmit Next Counter Register
3925 #define AT91C_US1_RCR (0xFFF90104) // (PDC_US1) Receive Counter Register
3926 #define AT91C_US1_RPR (0xFFF90100) // (PDC_US1) Receive Pointer Register
3927 #define AT91C_US1_TPR (0xFFF90108) // (PDC_US1) Transmit Pointer Register
3928 #define AT91C_US1_TCR (0xFFF9010C) // (PDC_US1) Transmit Counter Register
3929 #define AT91C_US1_RNPR (0xFFF90110) // (PDC_US1) Receive Next Pointer Register
3930 #define AT91C_US1_TNPR (0xFFF90118) // (PDC_US1) Transmit Next Pointer Register
3931 #define AT91C_US1_RNCR (0xFFF90114) // (PDC_US1) Receive Next Counter Register
3932 #define AT91C_US1_PTSR (0xFFF90124) // (PDC_US1) PDC Transfer Status Register
3933 // ========== Register definition for US1 peripheral ==========
3934 #define AT91C_US1_NER (0xFFF90044) // (US1) Nb Errors Register
3935 #define AT91C_US1_RHR (0xFFF90018) // (US1) Receiver Holding Register
3936 #define AT91C_US1_RTOR (0xFFF90024) // (US1) Receiver Time-out Register
3937 #define AT91C_US1_IER (0xFFF90008) // (US1) Interrupt Enable Register
3938 #define AT91C_US1_IF (0xFFF9004C) // (US1) IRDA_FILTER Register
3939 #define AT91C_US1_CR (0xFFF90000) // (US1) Control Register
3940 #define AT91C_US1_IMR (0xFFF90010) // (US1) Interrupt Mask Register
3941 #define AT91C_US1_TTGR (0xFFF90028) // (US1) Transmitter Time-guard Register
3942 #define AT91C_US1_MR (0xFFF90004) // (US1) Mode Register
3943 #define AT91C_US1_IDR (0xFFF9000C) // (US1) Interrupt Disable Register
3944 #define AT91C_US1_FIDI (0xFFF90040) // (US1) FI_DI_Ratio Register
3945 #define AT91C_US1_CSR (0xFFF90014) // (US1) Channel Status Register
3946 #define AT91C_US1_THR (0xFFF9001C) // (US1) Transmitter Holding Register
3947 #define AT91C_US1_BRGR (0xFFF90020) // (US1) Baud Rate Generator Register
3948 // ========== Register definition for PDC_US2 peripheral ==========
3949 #define AT91C_US2_RNCR (0xFFF94114) // (PDC_US2) Receive Next Counter Register
3950 #define AT91C_US2_PTCR (0xFFF94120) // (PDC_US2) PDC Transfer Control Register
3951 #define AT91C_US2_TNPR (0xFFF94118) // (PDC_US2) Transmit Next Pointer Register
3952 #define AT91C_US2_TNCR (0xFFF9411C) // (PDC_US2) Transmit Next Counter Register
3953 #define AT91C_US2_TPR (0xFFF94108) // (PDC_US2) Transmit Pointer Register
3954 #define AT91C_US2_RCR (0xFFF94104) // (PDC_US2) Receive Counter Register
3955 #define AT91C_US2_PTSR (0xFFF94124) // (PDC_US2) PDC Transfer Status Register
3956 #define AT91C_US2_TCR (0xFFF9410C) // (PDC_US2) Transmit Counter Register
3957 #define AT91C_US2_RPR (0xFFF94100) // (PDC_US2) Receive Pointer Register
3958 #define AT91C_US2_RNPR (0xFFF94110) // (PDC_US2) Receive Next Pointer Register
3959 // ========== Register definition for US2 peripheral ==========
3960 #define AT91C_US2_TTGR (0xFFF94028) // (US2) Transmitter Time-guard Register
3961 #define AT91C_US2_RHR (0xFFF94018) // (US2) Receiver Holding Register
3962 #define AT91C_US2_IMR (0xFFF94010) // (US2) Interrupt Mask Register
3963 #define AT91C_US2_IER (0xFFF94008) // (US2) Interrupt Enable Register
3964 #define AT91C_US2_NER (0xFFF94044) // (US2) Nb Errors Register
3965 #define AT91C_US2_CR (0xFFF94000) // (US2) Control Register
3966 #define AT91C_US2_FIDI (0xFFF94040) // (US2) FI_DI_Ratio Register
3967 #define AT91C_US2_MR (0xFFF94004) // (US2) Mode Register
3968 #define AT91C_US2_IDR (0xFFF9400C) // (US2) Interrupt Disable Register
3969 #define AT91C_US2_THR (0xFFF9401C) // (US2) Transmitter Holding Register
3970 #define AT91C_US2_IF (0xFFF9404C) // (US2) IRDA_FILTER Register
3971 #define AT91C_US2_BRGR (0xFFF94020) // (US2) Baud Rate Generator Register
3972 #define AT91C_US2_CSR (0xFFF94014) // (US2) Channel Status Register
3973 #define AT91C_US2_RTOR (0xFFF94024) // (US2) Receiver Time-out Register
3974 // ========== Register definition for PDC_SSC0 peripheral ==========
3975 #define AT91C_SSC0_PTSR (0xFFF98124) // (PDC_SSC0) PDC Transfer Status Register
3976 #define AT91C_SSC0_TCR (0xFFF9810C) // (PDC_SSC0) Transmit Counter Register
3977 #define AT91C_SSC0_RNPR (0xFFF98110) // (PDC_SSC0) Receive Next Pointer Register
3978 #define AT91C_SSC0_RNCR (0xFFF98114) // (PDC_SSC0) Receive Next Counter Register
3979 #define AT91C_SSC0_TNPR (0xFFF98118) // (PDC_SSC0) Transmit Next Pointer Register
3980 #define AT91C_SSC0_RPR (0xFFF98100) // (PDC_SSC0) Receive Pointer Register
3981 #define AT91C_SSC0_TPR (0xFFF98108) // (PDC_SSC0) Transmit Pointer Register
3982 #define AT91C_SSC0_RCR (0xFFF98104) // (PDC_SSC0) Receive Counter Register
3983 #define AT91C_SSC0_TNCR (0xFFF9811C) // (PDC_SSC0) Transmit Next Counter Register
3984 #define AT91C_SSC0_PTCR (0xFFF98120) // (PDC_SSC0) PDC Transfer Control Register
3985 // ========== Register definition for SSC0 peripheral ==========
3986 #define AT91C_SSC0_RFMR (0xFFF98014) // (SSC0) Receive Frame Mode Register
3987 #define AT91C_SSC0_RHR (0xFFF98020) // (SSC0) Receive Holding Register
3988 #define AT91C_SSC0_THR (0xFFF98024) // (SSC0) Transmit Holding Register
3989 #define AT91C_SSC0_CMR (0xFFF98004) // (SSC0) Clock Mode Register
3990 #define AT91C_SSC0_IMR (0xFFF9804C) // (SSC0) Interrupt Mask Register
3991 #define AT91C_SSC0_IDR (0xFFF98048) // (SSC0) Interrupt Disable Register
3992 #define AT91C_SSC0_IER (0xFFF98044) // (SSC0) Interrupt Enable Register
3993 #define AT91C_SSC0_TSHR (0xFFF98034) // (SSC0) Transmit Sync Holding Register
3994 #define AT91C_SSC0_SR (0xFFF98040) // (SSC0) Status Register
3995 #define AT91C_SSC0_CR (0xFFF98000) // (SSC0) Control Register
3996 #define AT91C_SSC0_RCMR (0xFFF98010) // (SSC0) Receive Clock ModeRegister
3997 #define AT91C_SSC0_TFMR (0xFFF9801C) // (SSC0) Transmit Frame Mode Register
3998 #define AT91C_SSC0_RSHR (0xFFF98030) // (SSC0) Receive Sync Holding Register
3999 #define AT91C_SSC0_TCMR (0xFFF98018) // (SSC0) Transmit Clock Mode Register
4000 // ========== Register definition for PDC_SSC1 peripheral ==========
4001 #define AT91C_SSC1_TNPR (0xFFF9C118) // (PDC_SSC1) Transmit Next Pointer Register
4002 #define AT91C_SSC1_PTSR (0xFFF9C124) // (PDC_SSC1) PDC Transfer Status Register
4003 #define AT91C_SSC1_TNCR (0xFFF9C11C) // (PDC_SSC1) Transmit Next Counter Register
4004 #define AT91C_SSC1_RNCR (0xFFF9C114) // (PDC_SSC1) Receive Next Counter Register
4005 #define AT91C_SSC1_TPR (0xFFF9C108) // (PDC_SSC1) Transmit Pointer Register
4006 #define AT91C_SSC1_RCR (0xFFF9C104) // (PDC_SSC1) Receive Counter Register
4007 #define AT91C_SSC1_PTCR (0xFFF9C120) // (PDC_SSC1) PDC Transfer Control Register
4008 #define AT91C_SSC1_RNPR (0xFFF9C110) // (PDC_SSC1) Receive Next Pointer Register
4009 #define AT91C_SSC1_TCR (0xFFF9C10C) // (PDC_SSC1) Transmit Counter Register
4010 #define AT91C_SSC1_RPR (0xFFF9C100) // (PDC_SSC1) Receive Pointer Register
4011 // ========== Register definition for SSC1 peripheral ==========
4012 #define AT91C_SSC1_CMR (0xFFF9C004) // (SSC1) Clock Mode Register
4013 #define AT91C_SSC1_SR (0xFFF9C040) // (SSC1) Status Register
4014 #define AT91C_SSC1_TSHR (0xFFF9C034) // (SSC1) Transmit Sync Holding Register
4015 #define AT91C_SSC1_TCMR (0xFFF9C018) // (SSC1) Transmit Clock Mode Register
4016 #define AT91C_SSC1_IMR (0xFFF9C04C) // (SSC1) Interrupt Mask Register
4017 #define AT91C_SSC1_IDR (0xFFF9C048) // (SSC1) Interrupt Disable Register
4018 #define AT91C_SSC1_RCMR (0xFFF9C010) // (SSC1) Receive Clock ModeRegister
4019 #define AT91C_SSC1_IER (0xFFF9C044) // (SSC1) Interrupt Enable Register
4020 #define AT91C_SSC1_RSHR (0xFFF9C030) // (SSC1) Receive Sync Holding Register
4021 #define AT91C_SSC1_CR (0xFFF9C000) // (SSC1) Control Register
4022 #define AT91C_SSC1_RHR (0xFFF9C020) // (SSC1) Receive Holding Register
4023 #define AT91C_SSC1_THR (0xFFF9C024) // (SSC1) Transmit Holding Register
4024 #define AT91C_SSC1_RFMR (0xFFF9C014) // (SSC1) Receive Frame Mode Register
4025 #define AT91C_SSC1_TFMR (0xFFF9C01C) // (SSC1) Transmit Frame Mode Register
4026 // ========== Register definition for PDC_AC97C peripheral ==========
4027 #define AT91C_AC97C_RNPR (0xFFFA0110) // (PDC_AC97C) Receive Next Pointer Register
4028 #define AT91C_AC97C_TCR (0xFFFA010C) // (PDC_AC97C) Transmit Counter Register
4029 #define AT91C_AC97C_TNCR (0xFFFA011C) // (PDC_AC97C) Transmit Next Counter Register
4030 #define AT91C_AC97C_RCR (0xFFFA0104) // (PDC_AC97C) Receive Counter Register
4031 #define AT91C_AC97C_RNCR (0xFFFA0114) // (PDC_AC97C) Receive Next Counter Register
4032 #define AT91C_AC97C_PTCR (0xFFFA0120) // (PDC_AC97C) PDC Transfer Control Register
4033 #define AT91C_AC97C_TPR (0xFFFA0108) // (PDC_AC97C) Transmit Pointer Register
4034 #define AT91C_AC97C_RPR (0xFFFA0100) // (PDC_AC97C) Receive Pointer Register
4035 #define AT91C_AC97C_PTSR (0xFFFA0124) // (PDC_AC97C) PDC Transfer Status Register
4036 #define AT91C_AC97C_TNPR (0xFFFA0118) // (PDC_AC97C) Transmit Next Pointer Register
4037 // ========== Register definition for AC97C peripheral ==========
4038 #define AT91C_AC97C_CORHR (0xFFFA0040) // (AC97C) COdec Transmit Holding Register
4039 #define AT91C_AC97C_MR (0xFFFA0008) // (AC97C) Mode Register
4040 #define AT91C_AC97C_CATHR (0xFFFA0024) // (AC97C) Channel A Transmit Holding Register
4041 #define AT91C_AC97C_IER (0xFFFA0054) // (AC97C) Interrupt Enable Register
4042 #define AT91C_AC97C_CASR (0xFFFA0028) // (AC97C) Channel A Status Register
4043 #define AT91C_AC97C_CBTHR (0xFFFA0034) // (AC97C) Channel B Transmit Holding Register (optional)
4044 #define AT91C_AC97C_ICA (0xFFFA0010) // (AC97C) Input Channel AssignementRegister
4045 #define AT91C_AC97C_IMR (0xFFFA005C) // (AC97C) Interrupt Mask Register
4046 #define AT91C_AC97C_IDR (0xFFFA0058) // (AC97C) Interrupt Disable Register
4047 #define AT91C_AC97C_CARHR (0xFFFA0020) // (AC97C) Channel A Receive Holding Register
4048 #define AT91C_AC97C_VERSION (0xFFFA00FC) // (AC97C) Version Register
4049 #define AT91C_AC97C_CBRHR (0xFFFA0030) // (AC97C) Channel B Receive Holding Register (optional)
4050 #define AT91C_AC97C_COTHR (0xFFFA0044) // (AC97C) COdec Transmit Holding Register
4051 #define AT91C_AC97C_OCA (0xFFFA0014) // (AC97C) Output Channel Assignement Register
4052 #define AT91C_AC97C_CBMR (0xFFFA003C) // (AC97C) Channel B Mode Register
4053 #define AT91C_AC97C_COMR (0xFFFA004C) // (AC97C) CODEC Mask Status Register
4054 #define AT91C_AC97C_CBSR (0xFFFA0038) // (AC97C) Channel B Status Register
4055 #define AT91C_AC97C_COSR (0xFFFA0048) // (AC97C) CODEC Status Register
4056 #define AT91C_AC97C_CAMR (0xFFFA002C) // (AC97C) Channel A Mode Register
4057 #define AT91C_AC97C_SR (0xFFFA0050) // (AC97C) Status Register
4058 // ========== Register definition for PDC_SPI0 peripheral ==========
4059 #define AT91C_SPI0_TPR (0xFFFA4108) // (PDC_SPI0) Transmit Pointer Register
4060 #define AT91C_SPI0_PTCR (0xFFFA4120) // (PDC_SPI0) PDC Transfer Control Register
4061 #define AT91C_SPI0_RNPR (0xFFFA4110) // (PDC_SPI0) Receive Next Pointer Register
4062 #define AT91C_SPI0_TNCR (0xFFFA411C) // (PDC_SPI0) Transmit Next Counter Register
4063 #define AT91C_SPI0_TCR (0xFFFA410C) // (PDC_SPI0) Transmit Counter Register
4064 #define AT91C_SPI0_RCR (0xFFFA4104) // (PDC_SPI0) Receive Counter Register
4065 #define AT91C_SPI0_RNCR (0xFFFA4114) // (PDC_SPI0) Receive Next Counter Register
4066 #define AT91C_SPI0_TNPR (0xFFFA4118) // (PDC_SPI0) Transmit Next Pointer Register
4067 #define AT91C_SPI0_RPR (0xFFFA4100) // (PDC_SPI0) Receive Pointer Register
4068 #define AT91C_SPI0_PTSR (0xFFFA4124) // (PDC_SPI0) PDC Transfer Status Register
4069 // ========== Register definition for SPI0 peripheral ==========
4070 #define AT91C_SPI0_MR (0xFFFA4004) // (SPI0) Mode Register
4071 #define AT91C_SPI0_RDR (0xFFFA4008) // (SPI0) Receive Data Register
4072 #define AT91C_SPI0_CR (0xFFFA4000) // (SPI0) Control Register
4073 #define AT91C_SPI0_IER (0xFFFA4014) // (SPI0) Interrupt Enable Register
4074 #define AT91C_SPI0_TDR (0xFFFA400C) // (SPI0) Transmit Data Register
4075 #define AT91C_SPI0_IDR (0xFFFA4018) // (SPI0) Interrupt Disable Register
4076 #define AT91C_SPI0_CSR (0xFFFA4030) // (SPI0) Chip Select Register
4077 #define AT91C_SPI0_SR (0xFFFA4010) // (SPI0) Status Register
4078 #define AT91C_SPI0_IMR (0xFFFA401C) // (SPI0) Interrupt Mask Register
4079 // ========== Register definition for PDC_SPI1 peripheral ==========
4080 #define AT91C_SPI1_RNCR (0xFFFA8114) // (PDC_SPI1) Receive Next Counter Register
4081 #define AT91C_SPI1_TCR (0xFFFA810C) // (PDC_SPI1) Transmit Counter Register
4082 #define AT91C_SPI1_RCR (0xFFFA8104) // (PDC_SPI1) Receive Counter Register
4083 #define AT91C_SPI1_TNPR (0xFFFA8118) // (PDC_SPI1) Transmit Next Pointer Register
4084 #define AT91C_SPI1_RNPR (0xFFFA8110) // (PDC_SPI1) Receive Next Pointer Register
4085 #define AT91C_SPI1_RPR (0xFFFA8100) // (PDC_SPI1) Receive Pointer Register
4086 #define AT91C_SPI1_TNCR (0xFFFA811C) // (PDC_SPI1) Transmit Next Counter Register
4087 #define AT91C_SPI1_TPR (0xFFFA8108) // (PDC_SPI1) Transmit Pointer Register
4088 #define AT91C_SPI1_PTSR (0xFFFA8124) // (PDC_SPI1) PDC Transfer Status Register
4089 #define AT91C_SPI1_PTCR (0xFFFA8120) // (PDC_SPI1) PDC Transfer Control Register
4090 // ========== Register definition for SPI1 peripheral ==========
4091 #define AT91C_SPI1_CSR (0xFFFA8030) // (SPI1) Chip Select Register
4092 #define AT91C_SPI1_IER (0xFFFA8014) // (SPI1) Interrupt Enable Register
4093 #define AT91C_SPI1_RDR (0xFFFA8008) // (SPI1) Receive Data Register
4094 #define AT91C_SPI1_IDR (0xFFFA8018) // (SPI1) Interrupt Disable Register
4095 #define AT91C_SPI1_MR (0xFFFA8004) // (SPI1) Mode Register
4096 #define AT91C_SPI1_CR (0xFFFA8000) // (SPI1) Control Register
4097 #define AT91C_SPI1_SR (0xFFFA8010) // (SPI1) Status Register
4098 #define AT91C_SPI1_TDR (0xFFFA800C) // (SPI1) Transmit Data Register
4099 #define AT91C_SPI1_IMR (0xFFFA801C) // (SPI1) Interrupt Mask Register
4100 // ========== Register definition for CAN_MB0 peripheral ==========
4101 #define AT91C_CAN_MB0_MID (0xFFFAC208) // (CAN_MB0) MailBox ID Register
4102 #define AT91C_CAN_MB0_MFID (0xFFFAC20C) // (CAN_MB0) MailBox Family ID Register
4103 #define AT91C_CAN_MB0_MAM (0xFFFAC204) // (CAN_MB0) MailBox Acceptance Mask Register
4104 #define AT91C_CAN_MB0_MCR (0xFFFAC21C) // (CAN_MB0) MailBox Control Register
4105 #define AT91C_CAN_MB0_MMR (0xFFFAC200) // (CAN_MB0) MailBox Mode Register
4106 #define AT91C_CAN_MB0_MDL (0xFFFAC214) // (CAN_MB0) MailBox Data Low Register
4107 #define AT91C_CAN_MB0_MDH (0xFFFAC218) // (CAN_MB0) MailBox Data High Register
4108 #define AT91C_CAN_MB0_MSR (0xFFFAC210) // (CAN_MB0) MailBox Status Register
4109 // ========== Register definition for CAN_MB1 peripheral ==========
4110 #define AT91C_CAN_MB1_MDL (0xFFFAC234) // (CAN_MB1) MailBox Data Low Register
4111 #define AT91C_CAN_MB1_MAM (0xFFFAC224) // (CAN_MB1) MailBox Acceptance Mask Register
4112 #define AT91C_CAN_MB1_MID (0xFFFAC228) // (CAN_MB1) MailBox ID Register
4113 #define AT91C_CAN_MB1_MMR (0xFFFAC220) // (CAN_MB1) MailBox Mode Register
4114 #define AT91C_CAN_MB1_MCR (0xFFFAC23C) // (CAN_MB1) MailBox Control Register
4115 #define AT91C_CAN_MB1_MFID (0xFFFAC22C) // (CAN_MB1) MailBox Family ID Register
4116 #define AT91C_CAN_MB1_MSR (0xFFFAC230) // (CAN_MB1) MailBox Status Register
4117 #define AT91C_CAN_MB1_MDH (0xFFFAC238) // (CAN_MB1) MailBox Data High Register
4118 // ========== Register definition for CAN_MB2 peripheral ==========
4119 #define AT91C_CAN_MB2_MID (0xFFFAC248) // (CAN_MB2) MailBox ID Register
4120 #define AT91C_CAN_MB2_MSR (0xFFFAC250) // (CAN_MB2) MailBox Status Register
4121 #define AT91C_CAN_MB2_MDL (0xFFFAC254) // (CAN_MB2) MailBox Data Low Register
4122 #define AT91C_CAN_MB2_MCR (0xFFFAC25C) // (CAN_MB2) MailBox Control Register
4123 #define AT91C_CAN_MB2_MDH (0xFFFAC258) // (CAN_MB2) MailBox Data High Register
4124 #define AT91C_CAN_MB2_MAM (0xFFFAC244) // (CAN_MB2) MailBox Acceptance Mask Register
4125 #define AT91C_CAN_MB2_MMR (0xFFFAC240) // (CAN_MB2) MailBox Mode Register
4126 #define AT91C_CAN_MB2_MFID (0xFFFAC24C) // (CAN_MB2) MailBox Family ID Register
4127 // ========== Register definition for CAN_MB3 peripheral ==========
4128 #define AT91C_CAN_MB3_MDL (0xFFFAC274) // (CAN_MB3) MailBox Data Low Register
4129 #define AT91C_CAN_MB3_MFID (0xFFFAC26C) // (CAN_MB3) MailBox Family ID Register
4130 #define AT91C_CAN_MB3_MID (0xFFFAC268) // (CAN_MB3) MailBox ID Register
4131 #define AT91C_CAN_MB3_MDH (0xFFFAC278) // (CAN_MB3) MailBox Data High Register
4132 #define AT91C_CAN_MB3_MAM (0xFFFAC264) // (CAN_MB3) MailBox Acceptance Mask Register
4133 #define AT91C_CAN_MB3_MMR (0xFFFAC260) // (CAN_MB3) MailBox Mode Register
4134 #define AT91C_CAN_MB3_MCR (0xFFFAC27C) // (CAN_MB3) MailBox Control Register
4135 #define AT91C_CAN_MB3_MSR (0xFFFAC270) // (CAN_MB3) MailBox Status Register
4136 // ========== Register definition for CAN_MB4 peripheral ==========
4137 #define AT91C_CAN_MB4_MCR (0xFFFAC29C) // (CAN_MB4) MailBox Control Register
4138 #define AT91C_CAN_MB4_MDH (0xFFFAC298) // (CAN_MB4) MailBox Data High Register
4139 #define AT91C_CAN_MB4_MID (0xFFFAC288) // (CAN_MB4) MailBox ID Register
4140 #define AT91C_CAN_MB4_MMR (0xFFFAC280) // (CAN_MB4) MailBox Mode Register
4141 #define AT91C_CAN_MB4_MSR (0xFFFAC290) // (CAN_MB4) MailBox Status Register
4142 #define AT91C_CAN_MB4_MFID (0xFFFAC28C) // (CAN_MB4) MailBox Family ID Register
4143 #define AT91C_CAN_MB4_MAM (0xFFFAC284) // (CAN_MB4) MailBox Acceptance Mask Register
4144 #define AT91C_CAN_MB4_MDL (0xFFFAC294) // (CAN_MB4) MailBox Data Low Register
4145 // ========== Register definition for CAN_MB5 peripheral ==========
4146 #define AT91C_CAN_MB5_MDH (0xFFFAC2B8) // (CAN_MB5) MailBox Data High Register
4147 #define AT91C_CAN_MB5_MID (0xFFFAC2A8) // (CAN_MB5) MailBox ID Register
4148 #define AT91C_CAN_MB5_MCR (0xFFFAC2BC) // (CAN_MB5) MailBox Control Register
4149 #define AT91C_CAN_MB5_MSR (0xFFFAC2B0) // (CAN_MB5) MailBox Status Register
4150 #define AT91C_CAN_MB5_MDL (0xFFFAC2B4) // (CAN_MB5) MailBox Data Low Register
4151 #define AT91C_CAN_MB5_MMR (0xFFFAC2A0) // (CAN_MB5) MailBox Mode Register
4152 #define AT91C_CAN_MB5_MAM (0xFFFAC2A4) // (CAN_MB5) MailBox Acceptance Mask Register
4153 #define AT91C_CAN_MB5_MFID (0xFFFAC2AC) // (CAN_MB5) MailBox Family ID Register
4154 // ========== Register definition for CAN_MB6 peripheral ==========
4155 #define AT91C_CAN_MB6_MSR (0xFFFAC2D0) // (CAN_MB6) MailBox Status Register
4156 #define AT91C_CAN_MB6_MMR (0xFFFAC2C0) // (CAN_MB6) MailBox Mode Register
4157 #define AT91C_CAN_MB6_MFID (0xFFFAC2CC) // (CAN_MB6) MailBox Family ID Register
4158 #define AT91C_CAN_MB6_MDL (0xFFFAC2D4) // (CAN_MB6) MailBox Data Low Register
4159 #define AT91C_CAN_MB6_MID (0xFFFAC2C8) // (CAN_MB6) MailBox ID Register
4160 #define AT91C_CAN_MB6_MCR (0xFFFAC2DC) // (CAN_MB6) MailBox Control Register
4161 #define AT91C_CAN_MB6_MAM (0xFFFAC2C4) // (CAN_MB6) MailBox Acceptance Mask Register
4162 #define AT91C_CAN_MB6_MDH (0xFFFAC2D8) // (CAN_MB6) MailBox Data High Register
4163 // ========== Register definition for CAN_MB7 peripheral ==========
4164 #define AT91C_CAN_MB7_MAM (0xFFFAC2E4) // (CAN_MB7) MailBox Acceptance Mask Register
4165 #define AT91C_CAN_MB7_MDH (0xFFFAC2F8) // (CAN_MB7) MailBox Data High Register
4166 #define AT91C_CAN_MB7_MID (0xFFFAC2E8) // (CAN_MB7) MailBox ID Register
4167 #define AT91C_CAN_MB7_MSR (0xFFFAC2F0) // (CAN_MB7) MailBox Status Register
4168 #define AT91C_CAN_MB7_MMR (0xFFFAC2E0) // (CAN_MB7) MailBox Mode Register
4169 #define AT91C_CAN_MB7_MCR (0xFFFAC2FC) // (CAN_MB7) MailBox Control Register
4170 #define AT91C_CAN_MB7_MFID (0xFFFAC2EC) // (CAN_MB7) MailBox Family ID Register
4171 #define AT91C_CAN_MB7_MDL (0xFFFAC2F4) // (CAN_MB7) MailBox Data Low Register
4172 // ========== Register definition for CAN_MB8 peripheral ==========
4173 #define AT91C_CAN_MB8_MDH (0xFFFAC318) // (CAN_MB8) MailBox Data High Register
4174 #define AT91C_CAN_MB8_MMR (0xFFFAC300) // (CAN_MB8) MailBox Mode Register
4175 #define AT91C_CAN_MB8_MCR (0xFFFAC31C) // (CAN_MB8) MailBox Control Register
4176 #define AT91C_CAN_MB8_MSR (0xFFFAC310) // (CAN_MB8) MailBox Status Register
4177 #define AT91C_CAN_MB8_MAM (0xFFFAC304) // (CAN_MB8) MailBox Acceptance Mask Register
4178 #define AT91C_CAN_MB8_MFID (0xFFFAC30C) // (CAN_MB8) MailBox Family ID Register
4179 #define AT91C_CAN_MB8_MID (0xFFFAC308) // (CAN_MB8) MailBox ID Register
4180 #define AT91C_CAN_MB8_MDL (0xFFFAC314) // (CAN_MB8) MailBox Data Low Register
4181 // ========== Register definition for CAN_MB9 peripheral ==========
4182 #define AT91C_CAN_MB9_MID (0xFFFAC328) // (CAN_MB9) MailBox ID Register
4183 #define AT91C_CAN_MB9_MMR (0xFFFAC320) // (CAN_MB9) MailBox Mode Register
4184 #define AT91C_CAN_MB9_MDH (0xFFFAC338) // (CAN_MB9) MailBox Data High Register
4185 #define AT91C_CAN_MB9_MSR (0xFFFAC330) // (CAN_MB9) MailBox Status Register
4186 #define AT91C_CAN_MB9_MAM (0xFFFAC324) // (CAN_MB9) MailBox Acceptance Mask Register
4187 #define AT91C_CAN_MB9_MDL (0xFFFAC334) // (CAN_MB9) MailBox Data Low Register
4188 #define AT91C_CAN_MB9_MFID (0xFFFAC32C) // (CAN_MB9) MailBox Family ID Register
4189 #define AT91C_CAN_MB9_MCR (0xFFFAC33C) // (CAN_MB9) MailBox Control Register
4190 // ========== Register definition for CAN_MB10 peripheral ==========
4191 #define AT91C_CAN_MB10_MCR (0xFFFAC35C) // (CAN_MB10) MailBox Control Register
4192 #define AT91C_CAN_MB10_MDH (0xFFFAC358) // (CAN_MB10) MailBox Data High Register
4193 #define AT91C_CAN_MB10_MAM (0xFFFAC344) // (CAN_MB10) MailBox Acceptance Mask Register
4194 #define AT91C_CAN_MB10_MID (0xFFFAC348) // (CAN_MB10) MailBox ID Register
4195 #define AT91C_CAN_MB10_MDL (0xFFFAC354) // (CAN_MB10) MailBox Data Low Register
4196 #define AT91C_CAN_MB10_MSR (0xFFFAC350) // (CAN_MB10) MailBox Status Register
4197 #define AT91C_CAN_MB10_MMR (0xFFFAC340) // (CAN_MB10) MailBox Mode Register
4198 #define AT91C_CAN_MB10_MFID (0xFFFAC34C) // (CAN_MB10) MailBox Family ID Register
4199 // ========== Register definition for CAN_MB11 peripheral ==========
4200 #define AT91C_CAN_MB11_MSR (0xFFFAC370) // (CAN_MB11) MailBox Status Register
4201 #define AT91C_CAN_MB11_MFID (0xFFFAC36C) // (CAN_MB11) MailBox Family ID Register
4202 #define AT91C_CAN_MB11_MDL (0xFFFAC374) // (CAN_MB11) MailBox Data Low Register
4203 #define AT91C_CAN_MB11_MDH (0xFFFAC378) // (CAN_MB11) MailBox Data High Register
4204 #define AT91C_CAN_MB11_MID (0xFFFAC368) // (CAN_MB11) MailBox ID Register
4205 #define AT91C_CAN_MB11_MCR (0xFFFAC37C) // (CAN_MB11) MailBox Control Register
4206 #define AT91C_CAN_MB11_MMR (0xFFFAC360) // (CAN_MB11) MailBox Mode Register
4207 #define AT91C_CAN_MB11_MAM (0xFFFAC364) // (CAN_MB11) MailBox Acceptance Mask Register
4208 // ========== Register definition for CAN_MB12 peripheral ==========
4209 #define AT91C_CAN_MB12_MAM (0xFFFAC384) // (CAN_MB12) MailBox Acceptance Mask Register
4210 #define AT91C_CAN_MB12_MDH (0xFFFAC398) // (CAN_MB12) MailBox Data High Register
4211 #define AT91C_CAN_MB12_MMR (0xFFFAC380) // (CAN_MB12) MailBox Mode Register
4212 #define AT91C_CAN_MB12_MSR (0xFFFAC390) // (CAN_MB12) MailBox Status Register
4213 #define AT91C_CAN_MB12_MFID (0xFFFAC38C) // (CAN_MB12) MailBox Family ID Register
4214 #define AT91C_CAN_MB12_MID (0xFFFAC388) // (CAN_MB12) MailBox ID Register
4215 #define AT91C_CAN_MB12_MCR (0xFFFAC39C) // (CAN_MB12) MailBox Control Register
4216 #define AT91C_CAN_MB12_MDL (0xFFFAC394) // (CAN_MB12) MailBox Data Low Register
4217 // ========== Register definition for CAN_MB13 peripheral ==========
4218 #define AT91C_CAN_MB13_MDH (0xFFFAC3B8) // (CAN_MB13) MailBox Data High Register
4219 #define AT91C_CAN_MB13_MFID (0xFFFAC3AC) // (CAN_MB13) MailBox Family ID Register
4220 #define AT91C_CAN_MB13_MSR (0xFFFAC3B0) // (CAN_MB13) MailBox Status Register
4221 #define AT91C_CAN_MB13_MID (0xFFFAC3A8) // (CAN_MB13) MailBox ID Register
4222 #define AT91C_CAN_MB13_MAM (0xFFFAC3A4) // (CAN_MB13) MailBox Acceptance Mask Register
4223 #define AT91C_CAN_MB13_MMR (0xFFFAC3A0) // (CAN_MB13) MailBox Mode Register
4224 #define AT91C_CAN_MB13_MCR (0xFFFAC3BC) // (CAN_MB13) MailBox Control Register
4225 #define AT91C_CAN_MB13_MDL (0xFFFAC3B4) // (CAN_MB13) MailBox Data Low Register
4226 // ========== Register definition for CAN_MB14 peripheral ==========
4227 #define AT91C_CAN_MB14_MDL (0xFFFAC3D4) // (CAN_MB14) MailBox Data Low Register
4228 #define AT91C_CAN_MB14_MMR (0xFFFAC3C0) // (CAN_MB14) MailBox Mode Register
4229 #define AT91C_CAN_MB14_MFID (0xFFFAC3CC) // (CAN_MB14) MailBox Family ID Register
4230 #define AT91C_CAN_MB14_MCR (0xFFFAC3DC) // (CAN_MB14) MailBox Control Register
4231 #define AT91C_CAN_MB14_MID (0xFFFAC3C8) // (CAN_MB14) MailBox ID Register
4232 #define AT91C_CAN_MB14_MDH (0xFFFAC3D8) // (CAN_MB14) MailBox Data High Register
4233 #define AT91C_CAN_MB14_MSR (0xFFFAC3D0) // (CAN_MB14) MailBox Status Register
4234 #define AT91C_CAN_MB14_MAM (0xFFFAC3C4) // (CAN_MB14) MailBox Acceptance Mask Register
4235 // ========== Register definition for CAN_MB15 peripheral ==========
4236 #define AT91C_CAN_MB15_MDL (0xFFFAC3F4) // (CAN_MB15) MailBox Data Low Register
4237 #define AT91C_CAN_MB15_MSR (0xFFFAC3F0) // (CAN_MB15) MailBox Status Register
4238 #define AT91C_CAN_MB15_MID (0xFFFAC3E8) // (CAN_MB15) MailBox ID Register
4239 #define AT91C_CAN_MB15_MAM (0xFFFAC3E4) // (CAN_MB15) MailBox Acceptance Mask Register
4240 #define AT91C_CAN_MB15_MCR (0xFFFAC3FC) // (CAN_MB15) MailBox Control Register
4241 #define AT91C_CAN_MB15_MFID (0xFFFAC3EC) // (CAN_MB15) MailBox Family ID Register
4242 #define AT91C_CAN_MB15_MMR (0xFFFAC3E0) // (CAN_MB15) MailBox Mode Register
4243 #define AT91C_CAN_MB15_MDH (0xFFFAC3F8) // (CAN_MB15) MailBox Data High Register
4244 // ========== Register definition for CAN peripheral ==========
4245 #define AT91C_CAN_ACR (0xFFFAC028) // (CAN) Abort Command Register
4246 #define AT91C_CAN_BR (0xFFFAC014) // (CAN) Baudrate Register
4247 #define AT91C_CAN_IDR (0xFFFAC008) // (CAN) Interrupt Disable Register
4248 #define AT91C_CAN_TIMESTP (0xFFFAC01C) // (CAN) Time Stamp Register
4249 #define AT91C_CAN_SR (0xFFFAC010) // (CAN) Status Register
4250 #define AT91C_CAN_IMR (0xFFFAC00C) // (CAN) Interrupt Mask Register
4251 #define AT91C_CAN_TCR (0xFFFAC024) // (CAN) Transfer Command Register
4252 #define AT91C_CAN_TIM (0xFFFAC018) // (CAN) Timer Register
4253 #define AT91C_CAN_IER (0xFFFAC004) // (CAN) Interrupt Enable Register
4254 #define AT91C_CAN_ECR (0xFFFAC020) // (CAN) Error Counter Register
4255 #define AT91C_CAN_VR (0xFFFAC0FC) // (CAN) Version Register
4256 #define AT91C_CAN_MR (0xFFFAC000) // (CAN) Mode Register
4257 // ========== Register definition for PDC_AES peripheral ==========
4258 #define AT91C_AES_TCR (0xFFFB010C) // (PDC_AES) Transmit Counter Register
4259 #define AT91C_AES_PTCR (0xFFFB0120) // (PDC_AES) PDC Transfer Control Register
4260 #define AT91C_AES_RNCR (0xFFFB0114) // (PDC_AES) Receive Next Counter Register
4261 #define AT91C_AES_PTSR (0xFFFB0124) // (PDC_AES) PDC Transfer Status Register
4262 #define AT91C_AES_TNCR (0xFFFB011C) // (PDC_AES) Transmit Next Counter Register
4263 #define AT91C_AES_RNPR (0xFFFB0110) // (PDC_AES) Receive Next Pointer Register
4264 #define AT91C_AES_RCR (0xFFFB0104) // (PDC_AES) Receive Counter Register
4265 #define AT91C_AES_TPR (0xFFFB0108) // (PDC_AES) Transmit Pointer Register
4266 #define AT91C_AES_TNPR (0xFFFB0118) // (PDC_AES) Transmit Next Pointer Register
4267 #define AT91C_AES_RPR (0xFFFB0100) // (PDC_AES) Receive Pointer Register
4268 // ========== Register definition for AES peripheral ==========
4269 #define AT91C_AES_VR (0xFFFB00FC) // (AES) AES Version Register
4270 #define AT91C_AES_IMR (0xFFFB0018) // (AES) Interrupt Mask Register
4271 #define AT91C_AES_CR (0xFFFB0000) // (AES) Control Register
4272 #define AT91C_AES_ODATAxR (0xFFFB0050) // (AES) Output Data x Register
4273 #define AT91C_AES_ISR (0xFFFB001C) // (AES) Interrupt Status Register
4274 #define AT91C_AES_IDR (0xFFFB0014) // (AES) Interrupt Disable Register
4275 #define AT91C_AES_KEYWxR (0xFFFB0020) // (AES) Key Word x Register
4276 #define AT91C_AES_IVxR (0xFFFB0060) // (AES) Initialization Vector x Register
4277 #define AT91C_AES_MR (0xFFFB0004) // (AES) Mode Register
4278 #define AT91C_AES_IDATAxR (0xFFFB0040) // (AES) Input Data x Register
4279 #define AT91C_AES_IER (0xFFFB0010) // (AES) Interrupt Enable Register
4280 // ========== Register definition for PDC_TDES peripheral ==========
4281 #define AT91C_TDES_TCR (0xFFFB010C) // (PDC_TDES) Transmit Counter Register
4282 #define AT91C_TDES_PTCR (0xFFFB0120) // (PDC_TDES) PDC Transfer Control Register
4283 #define AT91C_TDES_RNCR (0xFFFB0114) // (PDC_TDES) Receive Next Counter Register
4284 #define AT91C_TDES_PTSR (0xFFFB0124) // (PDC_TDES) PDC Transfer Status Register
4285 #define AT91C_TDES_TNCR (0xFFFB011C) // (PDC_TDES) Transmit Next Counter Register
4286 #define AT91C_TDES_RNPR (0xFFFB0110) // (PDC_TDES) Receive Next Pointer Register
4287 #define AT91C_TDES_RCR (0xFFFB0104) // (PDC_TDES) Receive Counter Register
4288 #define AT91C_TDES_TPR (0xFFFB0108) // (PDC_TDES) Transmit Pointer Register
4289 #define AT91C_TDES_TNPR (0xFFFB0118) // (PDC_TDES) Transmit Next Pointer Register
4290 #define AT91C_TDES_RPR (0xFFFB0100) // (PDC_TDES) Receive Pointer Register
4291 // ========== Register definition for TDES peripheral ==========
4292 #define AT91C_TDES_VR (0xFFFB00FC) // (TDES) TDES Version Register
4293 #define AT91C_TDES_IMR (0xFFFB0018) // (TDES) Interrupt Mask Register
4294 #define AT91C_TDES_CR (0xFFFB0000) // (TDES) Control Register
4295 #define AT91C_TDES_ODATAxR (0xFFFB0050) // (TDES) Output Data x Register
4296 #define AT91C_TDES_ISR (0xFFFB001C) // (TDES) Interrupt Status Register
4297 #define AT91C_TDES_KEY3WxR (0xFFFB0030) // (TDES) Key 3 Word x Register
4298 #define AT91C_TDES_IDR (0xFFFB0014) // (TDES) Interrupt Disable Register
4299 #define AT91C_TDES_KEY1WxR (0xFFFB0020) // (TDES) Key 1 Word x Register
4300 #define AT91C_TDES_KEY2WxR (0xFFFB0028) // (TDES) Key 2 Word x Register
4301 #define AT91C_TDES_IVxR (0xFFFB0060) // (TDES) Initialization Vector x Register
4302 #define AT91C_TDES_MR (0xFFFB0004) // (TDES) Mode Register
4303 #define AT91C_TDES_IDATAxR (0xFFFB0040) // (TDES) Input Data x Register
4304 #define AT91C_TDES_IER (0xFFFB0010) // (TDES) Interrupt Enable Register
4305 // ========== Register definition for PWMC_CH0 peripheral ==========
4306 #define AT91C_PWMC_CH0_CCNTR (0xFFFB820C) // (PWMC_CH0) Channel Counter Register
4307 #define AT91C_PWMC_CH0_CPRDR (0xFFFB8208) // (PWMC_CH0) Channel Period Register
4308 #define AT91C_PWMC_CH0_CUPDR (0xFFFB8210) // (PWMC_CH0) Channel Update Register
4309 #define AT91C_PWMC_CH0_CDTYR (0xFFFB8204) // (PWMC_CH0) Channel Duty Cycle Register
4310 #define AT91C_PWMC_CH0_CMR (0xFFFB8200) // (PWMC_CH0) Channel Mode Register
4311 #define AT91C_PWMC_CH0_Reserved (0xFFFB8214) // (PWMC_CH0) Reserved
4312 // ========== Register definition for PWMC_CH1 peripheral ==========
4313 #define AT91C_PWMC_CH1_CCNTR (0xFFFB822C) // (PWMC_CH1) Channel Counter Register
4314 #define AT91C_PWMC_CH1_CDTYR (0xFFFB8224) // (PWMC_CH1) Channel Duty Cycle Register
4315 #define AT91C_PWMC_CH1_CMR (0xFFFB8220) // (PWMC_CH1) Channel Mode Register
4316 #define AT91C_PWMC_CH1_CPRDR (0xFFFB8228) // (PWMC_CH1) Channel Period Register
4317 #define AT91C_PWMC_CH1_Reserved (0xFFFB8234) // (PWMC_CH1) Reserved
4318 #define AT91C_PWMC_CH1_CUPDR (0xFFFB8230) // (PWMC_CH1) Channel Update Register
4319 // ========== Register definition for PWMC_CH2 peripheral ==========
4320 #define AT91C_PWMC_CH2_CUPDR (0xFFFB8250) // (PWMC_CH2) Channel Update Register
4321 #define AT91C_PWMC_CH2_CMR (0xFFFB8240) // (PWMC_CH2) Channel Mode Register
4322 #define AT91C_PWMC_CH2_Reserved (0xFFFB8254) // (PWMC_CH2) Reserved
4323 #define AT91C_PWMC_CH2_CPRDR (0xFFFB8248) // (PWMC_CH2) Channel Period Register
4324 #define AT91C_PWMC_CH2_CDTYR (0xFFFB8244) // (PWMC_CH2) Channel Duty Cycle Register
4325 #define AT91C_PWMC_CH2_CCNTR (0xFFFB824C) // (PWMC_CH2) Channel Counter Register
4326 // ========== Register definition for PWMC_CH3 peripheral ==========
4327 #define AT91C_PWMC_CH3_CPRDR (0xFFFB8268) // (PWMC_CH3) Channel Period Register
4328 #define AT91C_PWMC_CH3_Reserved (0xFFFB8274) // (PWMC_CH3) Reserved
4329 #define AT91C_PWMC_CH3_CUPDR (0xFFFB8270) // (PWMC_CH3) Channel Update Register
4330 #define AT91C_PWMC_CH3_CDTYR (0xFFFB8264) // (PWMC_CH3) Channel Duty Cycle Register
4331 #define AT91C_PWMC_CH3_CCNTR (0xFFFB826C) // (PWMC_CH3) Channel Counter Register
4332 #define AT91C_PWMC_CH3_CMR (0xFFFB8260) // (PWMC_CH3) Channel Mode Register
4333 // ========== Register definition for PWMC peripheral ==========
4334 #define AT91C_PWMC_IDR (0xFFFB8014) // (PWMC) PWMC Interrupt Disable Register
4335 #define AT91C_PWMC_MR (0xFFFB8000) // (PWMC) PWMC Mode Register
4336 #define AT91C_PWMC_VR (0xFFFB80FC) // (PWMC) PWMC Version Register
4337 #define AT91C_PWMC_IMR (0xFFFB8018) // (PWMC) PWMC Interrupt Mask Register
4338 #define AT91C_PWMC_SR (0xFFFB800C) // (PWMC) PWMC Status Register
4339 #define AT91C_PWMC_ISR (0xFFFB801C) // (PWMC) PWMC Interrupt Status Register
4340 #define AT91C_PWMC_ENA (0xFFFB8004) // (PWMC) PWMC Enable Register
4341 #define AT91C_PWMC_IER (0xFFFB8010) // (PWMC) PWMC Interrupt Enable Register
4342 #define AT91C_PWMC_DIS (0xFFFB8008) // (PWMC) PWMC Disable Register
4343 // ========== Register definition for MACB peripheral ==========
4344 #define AT91C_MACB_ALE (0xFFFBC054) // (MACB) Alignment Error Register
4345 #define AT91C_MACB_RRE (0xFFFBC06C) // (MACB) Receive Ressource Error Register
4346 #define AT91C_MACB_SA4H (0xFFFBC0B4) // (MACB) Specific Address 4 Top, Last 2 bytes
4347 #define AT91C_MACB_TPQ (0xFFFBC0BC) // (MACB) Transmit Pause Quantum Register
4348 #define AT91C_MACB_RJA (0xFFFBC07C) // (MACB) Receive Jabbers Register
4349 #define AT91C_MACB_SA2H (0xFFFBC0A4) // (MACB) Specific Address 2 Top, Last 2 bytes
4350 #define AT91C_MACB_TPF (0xFFFBC08C) // (MACB) Transmitted Pause Frames Register
4351 #define AT91C_MACB_ROV (0xFFFBC070) // (MACB) Receive Overrun Errors Register
4352 #define AT91C_MACB_SA4L (0xFFFBC0B0) // (MACB) Specific Address 4 Bottom, First 4 bytes
4353 #define AT91C_MACB_MAN (0xFFFBC034) // (MACB) PHY Maintenance Register
4354 #define AT91C_MACB_TID (0xFFFBC0B8) // (MACB) Type ID Checking Register
4355 #define AT91C_MACB_TBQP (0xFFFBC01C) // (MACB) Transmit Buffer Queue Pointer
4356 #define AT91C_MACB_SA3L (0xFFFBC0A8) // (MACB) Specific Address 3 Bottom, First 4 bytes
4357 #define AT91C_MACB_DTF (0xFFFBC058) // (MACB) Deferred Transmission Frame Register
4358 #define AT91C_MACB_PTR (0xFFFBC038) // (MACB) Pause Time Register
4359 #define AT91C_MACB_CSE (0xFFFBC068) // (MACB) Carrier Sense Error Register
4360 #define AT91C_MACB_ECOL (0xFFFBC060) // (MACB) Excessive Collision Register
4361 #define AT91C_MACB_STE (0xFFFBC084) // (MACB) SQE Test Error Register
4362 #define AT91C_MACB_MCF (0xFFFBC048) // (MACB) Multiple Collision Frame Register
4363 #define AT91C_MACB_IER (0xFFFBC028) // (MACB) Interrupt Enable Register
4364 #define AT91C_MACB_ELE (0xFFFBC078) // (MACB) Excessive Length Errors Register
4365 #define AT91C_MACB_USRIO (0xFFFBC0C0) // (MACB) USER Input/Output Register
4366 #define AT91C_MACB_PFR (0xFFFBC03C) // (MACB) Pause Frames received Register
4367 #define AT91C_MACB_FCSE (0xFFFBC050) // (MACB) Frame Check Sequence Error Register
4368 #define AT91C_MACB_SA1L (0xFFFBC098) // (MACB) Specific Address 1 Bottom, First 4 bytes
4369 #define AT91C_MACB_NCR (0xFFFBC000) // (MACB) Network Control Register
4370 #define AT91C_MACB_HRT (0xFFFBC094) // (MACB) Hash Address Top[63:32]
4371 #define AT91C_MACB_NCFGR (0xFFFBC004) // (MACB) Network Configuration Register
4372 #define AT91C_MACB_SCF (0xFFFBC044) // (MACB) Single Collision Frame Register
4373 #define AT91C_MACB_LCOL (0xFFFBC05C) // (MACB) Late Collision Register
4374 #define AT91C_MACB_SA3H (0xFFFBC0AC) // (MACB) Specific Address 3 Top, Last 2 bytes
4375 #define AT91C_MACB_HRB (0xFFFBC090) // (MACB) Hash Address Bottom[31:0]
4376 #define AT91C_MACB_ISR (0xFFFBC024) // (MACB) Interrupt Status Register
4377 #define AT91C_MACB_IMR (0xFFFBC030) // (MACB) Interrupt Mask Register
4378 #define AT91C_MACB_WOL (0xFFFBC0C4) // (MACB) Wake On LAN Register
4379 #define AT91C_MACB_USF (0xFFFBC080) // (MACB) Undersize Frames Register
4380 #define AT91C_MACB_TSR (0xFFFBC014) // (MACB) Transmit Status Register
4381 #define AT91C_MACB_FRO (0xFFFBC04C) // (MACB) Frames Received OK Register
4382 #define AT91C_MACB_IDR (0xFFFBC02C) // (MACB) Interrupt Disable Register
4383 #define AT91C_MACB_SA1H (0xFFFBC09C) // (MACB) Specific Address 1 Top, Last 2 bytes
4384 #define AT91C_MACB_RLE (0xFFFBC088) // (MACB) Receive Length Field Mismatch Register
4385 #define AT91C_MACB_TUND (0xFFFBC064) // (MACB) Transmit Underrun Error Register
4386 #define AT91C_MACB_RSR (0xFFFBC020) // (MACB) Receive Status Register
4387 #define AT91C_MACB_SA2L (0xFFFBC0A0) // (MACB) Specific Address 2 Bottom, First 4 bytes
4388 #define AT91C_MACB_FTO (0xFFFBC040) // (MACB) Frames Transmitted OK Register
4389 #define AT91C_MACB_RSE (0xFFFBC074) // (MACB) Receive Symbol Errors Register
4390 #define AT91C_MACB_NSR (0xFFFBC008) // (MACB) Network Status Register
4391 #define AT91C_MACB_RBQP (0xFFFBC018) // (MACB) Receive Buffer Queue Pointer
4392 #define AT91C_MACB_REV (0xFFFBC0FC) // (MACB) Revision Register
4393 // ========== Register definition for PDC_ADC peripheral ==========
4394 #define AT91C_ADC_TNPR (0xFFFC0118) // (PDC_ADC) Transmit Next Pointer Register
4395 #define AT91C_ADC_RNPR (0xFFFC0110) // (PDC_ADC) Receive Next Pointer Register
4396 #define AT91C_ADC_TCR (0xFFFC010C) // (PDC_ADC) Transmit Counter Register
4397 #define AT91C_ADC_PTCR (0xFFFC0120) // (PDC_ADC) PDC Transfer Control Register
4398 #define AT91C_ADC_PTSR (0xFFFC0124) // (PDC_ADC) PDC Transfer Status Register
4399 #define AT91C_ADC_TNCR (0xFFFC011C) // (PDC_ADC) Transmit Next Counter Register
4400 #define AT91C_ADC_TPR (0xFFFC0108) // (PDC_ADC) Transmit Pointer Register
4401 #define AT91C_ADC_RCR (0xFFFC0104) // (PDC_ADC) Receive Counter Register
4402 #define AT91C_ADC_RPR (0xFFFC0100) // (PDC_ADC) Receive Pointer Register
4403 #define AT91C_ADC_RNCR (0xFFFC0114) // (PDC_ADC) Receive Next Counter Register
4404 // ========== Register definition for ADC peripheral ==========
4405 #define AT91C_ADC_CDR6 (0xFFFC0048) // (ADC) ADC Channel Data Register 6
4406 #define AT91C_ADC_IMR (0xFFFC002C) // (ADC) ADC Interrupt Mask Register
4407 #define AT91C_ADC_CHER (0xFFFC0010) // (ADC) ADC Channel Enable Register
4408 #define AT91C_ADC_CDR4 (0xFFFC0040) // (ADC) ADC Channel Data Register 4
4409 #define AT91C_ADC_CDR1 (0xFFFC0034) // (ADC) ADC Channel Data Register 1
4410 #define AT91C_ADC_IER (0xFFFC0024) // (ADC) ADC Interrupt Enable Register
4411 #define AT91C_ADC_CHDR (0xFFFC0014) // (ADC) ADC Channel Disable Register
4412 #define AT91C_ADC_CDR2 (0xFFFC0038) // (ADC) ADC Channel Data Register 2
4413 #define AT91C_ADC_LCDR (0xFFFC0020) // (ADC) ADC Last Converted Data Register
4414 #define AT91C_ADC_CR (0xFFFC0000) // (ADC) ADC Control Register
4415 #define AT91C_ADC_CDR5 (0xFFFC0044) // (ADC) ADC Channel Data Register 5
4416 #define AT91C_ADC_CDR3 (0xFFFC003C) // (ADC) ADC Channel Data Register 3
4417 #define AT91C_ADC_MR (0xFFFC0004) // (ADC) ADC Mode Register
4418 #define AT91C_ADC_IDR (0xFFFC0028) // (ADC) ADC Interrupt Disable Register
4419 #define AT91C_ADC_CDR0 (0xFFFC0030) // (ADC) ADC Channel Data Register 0
4420 #define AT91C_ADC_CHSR (0xFFFC0018) // (ADC) ADC Channel Status Register
4421 #define AT91C_ADC_SR (0xFFFC001C) // (ADC) ADC Status Register
4422 #define AT91C_ADC_CDR7 (0xFFFC004C) // (ADC) ADC Channel Data Register 7
4423 // ========== Register definition for HISI peripheral ==========
4424 #define AT91C_HISI_CDBA (0xFFFC402C) // (HISI) Codec Dma Address Register
4425 #define AT91C_HISI_PDECF (0xFFFC4024) // (HISI) Preview Decimation Factor Register
4426 #define AT91C_HISI_IMR (0xFFFC4014) // (HISI) Interrupt Mask Register
4427 #define AT91C_HISI_IER (0xFFFC400C) // (HISI) Interrupt Enable Register
4428 #define AT91C_HISI_SR (0xFFFC4008) // (HISI) Status Register
4429 #define AT91C_HISI_Y2RSET0 (0xFFFC4030) // (HISI) Color Space Conversion Register
4430 #define AT91C_HISI_PFBD (0xFFFC4028) // (HISI) Preview Frame Buffer Address Register
4431 #define AT91C_HISI_PSIZE (0xFFFC4020) // (HISI) Preview Size Register
4432 #define AT91C_HISI_IDR (0xFFFC4010) // (HISI) Interrupt Disable Register
4433 #define AT91C_HISI_R2YSET2 (0xFFFC4040) // (HISI) Color Space Conversion Register
4434 #define AT91C_HISI_R2YSET0 (0xFFFC4038) // (HISI) Color Space Conversion Register
4435 #define AT91C_HISI_CR1 (0xFFFC4000) // (HISI) Control Register 1
4436 #define AT91C_HISI_CR2 (0xFFFC4004) // (HISI) Control Register 2
4437 #define AT91C_HISI_Y2RSET1 (0xFFFC4034) // (HISI) Color Space Conversion Register
4438 #define AT91C_HISI_R2YSET1 (0xFFFC403C) // (HISI) Color Space Conversion Register
4439 // ========== Register definition for LCDC peripheral ==========
4440 #define AT91C_LCDC_MVAL (0x00500818) // (LCDC) LCD Mode Toggle Rate Value Register
4441 #define AT91C_LCDC_PWRCON (0x0050083C) // (LCDC) Power Control Register
4442 #define AT91C_LCDC_ISR (0x00500854) // (LCDC) Interrupt Enable Register
4443 #define AT91C_LCDC_FRMP1 (0x00500008) // (LCDC) DMA Frame Pointer Register 1
4444 #define AT91C_LCDC_CTRSTVAL (0x00500844) // (LCDC) Contrast Value Register
4445 #define AT91C_LCDC_ICR (0x00500858) // (LCDC) Interrupt Clear Register
4446 #define AT91C_LCDC_TIM1 (0x00500808) // (LCDC) LCD Timing Config 1 Register
4447 #define AT91C_LCDC_DMACON (0x0050001C) // (LCDC) DMA Control Register
4448 #define AT91C_LCDC_ITR (0x00500860) // (LCDC) Interrupts Test Register
4449 #define AT91C_LCDC_IDR (0x0050084C) // (LCDC) Interrupt Disable Register
4450 #define AT91C_LCDC_DP4_7 (0x00500820) // (LCDC) Dithering Pattern DP4_7 Register
4451 #define AT91C_LCDC_DP5_7 (0x0050082C) // (LCDC) Dithering Pattern DP5_7 Register
4452 #define AT91C_LCDC_IRR (0x00500864) // (LCDC) Interrupts Raw Status Register
4453 #define AT91C_LCDC_DP3_4 (0x00500830) // (LCDC) Dithering Pattern DP3_4 Register
4454 #define AT91C_LCDC_IMR (0x00500850) // (LCDC) Interrupt Mask Register
4455 #define AT91C_LCDC_LCDFRCFG (0x00500810) // (LCDC) LCD Frame Config Register
4456 #define AT91C_LCDC_CTRSTCON (0x00500840) // (LCDC) Contrast Control Register
4457 #define AT91C_LCDC_DP1_2 (0x0050081C) // (LCDC) Dithering Pattern DP1_2 Register
4458 #define AT91C_LCDC_FRMP2 (0x0050000C) // (LCDC) DMA Frame Pointer Register 2
4459 #define AT91C_LCDC_LCDCON1 (0x00500800) // (LCDC) LCD Control 1 Register
4460 #define AT91C_LCDC_DP4_5 (0x00500834) // (LCDC) Dithering Pattern DP4_5 Register
4461 #define AT91C_LCDC_FRMA2 (0x00500014) // (LCDC) DMA Frame Address Register 2
4462 #define AT91C_LCDC_BA1 (0x00500000) // (LCDC) DMA Base Address Register 1
4463 #define AT91C_LCDC_DMA2DCFG (0x00500020) // (LCDC) DMA 2D addressing configuration
4464 #define AT91C_LCDC_LUT_ENTRY (0x00500C00) // (LCDC) LUT Entries Register
4465 #define AT91C_LCDC_DP6_7 (0x00500838) // (LCDC) Dithering Pattern DP6_7 Register
4466 #define AT91C_LCDC_FRMCFG (0x00500018) // (LCDC) DMA Frame Configuration Register
4467 #define AT91C_LCDC_TIM2 (0x0050080C) // (LCDC) LCD Timing Config 2 Register
4468 #define AT91C_LCDC_DP3_5 (0x00500824) // (LCDC) Dithering Pattern DP3_5 Register
4469 #define AT91C_LCDC_FRMA1 (0x00500010) // (LCDC) DMA Frame Address Register 1
4470 #define AT91C_LCDC_IER (0x00500848) // (LCDC) Interrupt Enable Register
4471 #define AT91C_LCDC_DP2_3 (0x00500828) // (LCDC) Dithering Pattern DP2_3 Register
4472 #define AT91C_LCDC_FIFO (0x00500814) // (LCDC) LCD FIFO Register
4473 #define AT91C_LCDC_BA2 (0x00500004) // (LCDC) DMA Base Address Register 2
4474 #define AT91C_LCDC_LCDCON2 (0x00500804) // (LCDC) LCD Control 2 Register
4475 #define AT91C_LCDC_GPR (0x0050085C) // (LCDC) General Purpose Register
4476 // ========== Register definition for HDMA_CH_0 peripheral ==========
4477 #define AT91C_HDMA_CH_0_DADDR (0xFFFFEC40) // (HDMA_CH_0) HDMA Channel Destination Address Register
4478 #define AT91C_HDMA_CH_0_DPIP (0xFFFFEC58) // (HDMA_CH_0) HDMA Channel Destination Picture in Picture Configuration Register
4479 #define AT91C_HDMA_CH_0_DSCR (0xFFFFEC44) // (HDMA_CH_0) HDMA Channel Descriptor Address Register
4480 #define AT91C_HDMA_CH_0_CFG (0xFFFFEC50) // (HDMA_CH_0) HDMA Channel Configuration Register
4481 #define AT91C_HDMA_CH_0_SPIP (0xFFFFEC54) // (HDMA_CH_0) HDMA Channel Source Picture in Picture Configuration Register
4482 #define AT91C_HDMA_CH_0_CTRLA (0xFFFFEC48) // (HDMA_CH_0) HDMA Channel Control A Register
4483 #define AT91C_HDMA_CH_0_CTRLB (0xFFFFEC4C) // (HDMA_CH_0) HDMA Channel Control B Register
4484 #define AT91C_HDMA_CH_0_SADDR (0xFFFFEC3C) // (HDMA_CH_0) HDMA Channel Source Address Register
4485 // ========== Register definition for HDMA_CH_1 peripheral ==========
4486 #define AT91C_HDMA_CH_1_DPIP (0xFFFFEC80) // (HDMA_CH_1) HDMA Channel Destination Picture in Picture Configuration Register
4487 #define AT91C_HDMA_CH_1_CTRLB (0xFFFFEC74) // (HDMA_CH_1) HDMA Channel Control B Register
4488 #define AT91C_HDMA_CH_1_SADDR (0xFFFFEC64) // (HDMA_CH_1) HDMA Channel Source Address Register
4489 #define AT91C_HDMA_CH_1_CFG (0xFFFFEC78) // (HDMA_CH_1) HDMA Channel Configuration Register
4490 #define AT91C_HDMA_CH_1_DSCR (0xFFFFEC6C) // (HDMA_CH_1) HDMA Channel Descriptor Address Register
4491 #define AT91C_HDMA_CH_1_DADDR (0xFFFFEC68) // (HDMA_CH_1) HDMA Channel Destination Address Register
4492 #define AT91C_HDMA_CH_1_CTRLA (0xFFFFEC70) // (HDMA_CH_1) HDMA Channel Control A Register
4493 #define AT91C_HDMA_CH_1_SPIP (0xFFFFEC7C) // (HDMA_CH_1) HDMA Channel Source Picture in Picture Configuration Register
4494 // ========== Register definition for HDMA_CH_2 peripheral ==========
4495 #define AT91C_HDMA_CH_2_DSCR (0xFFFFEC94) // (HDMA_CH_2) HDMA Channel Descriptor Address Register
4496 #define AT91C_HDMA_CH_2_CTRLA (0xFFFFEC98) // (HDMA_CH_2) HDMA Channel Control A Register
4497 #define AT91C_HDMA_CH_2_SADDR (0xFFFFEC8C) // (HDMA_CH_2) HDMA Channel Source Address Register
4498 #define AT91C_HDMA_CH_2_CFG (0xFFFFECA0) // (HDMA_CH_2) HDMA Channel Configuration Register
4499 #define AT91C_HDMA_CH_2_DPIP (0xFFFFECA8) // (HDMA_CH_2) HDMA Channel Destination Picture in Picture Configuration Register
4500 #define AT91C_HDMA_CH_2_SPIP (0xFFFFECA4) // (HDMA_CH_2) HDMA Channel Source Picture in Picture Configuration Register
4501 #define AT91C_HDMA_CH_2_CTRLB (0xFFFFEC9C) // (HDMA_CH_2) HDMA Channel Control B Register
4502 #define AT91C_HDMA_CH_2_DADDR (0xFFFFEC90) // (HDMA_CH_2) HDMA Channel Destination Address Register
4503 // ========== Register definition for HDMA_CH_3 peripheral ==========
4504 #define AT91C_HDMA_CH_3_SPIP (0xFFFFECCC) // (HDMA_CH_3) HDMA Channel Source Picture in Picture Configuration Register
4505 #define AT91C_HDMA_CH_3_CTRLA (0xFFFFECC0) // (HDMA_CH_3) HDMA Channel Control A Register
4506 #define AT91C_HDMA_CH_3_DPIP (0xFFFFECD0) // (HDMA_CH_3) HDMA Channel Destination Picture in Picture Configuration Register
4507 #define AT91C_HDMA_CH_3_CTRLB (0xFFFFECC4) // (HDMA_CH_3) HDMA Channel Control B Register
4508 #define AT91C_HDMA_CH_3_DSCR (0xFFFFECBC) // (HDMA_CH_3) HDMA Channel Descriptor Address Register
4509 #define AT91C_HDMA_CH_3_CFG (0xFFFFECC8) // (HDMA_CH_3) HDMA Channel Configuration Register
4510 #define AT91C_HDMA_CH_3_DADDR (0xFFFFECB8) // (HDMA_CH_3) HDMA Channel Destination Address Register
4511 #define AT91C_HDMA_CH_3_SADDR (0xFFFFECB4) // (HDMA_CH_3) HDMA Channel Source Address Register
4512 // ========== Register definition for HDMA peripheral ==========
4513 #define AT91C_HDMA_EBCIDR (0xFFFFEC1C) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register
4514 #define AT91C_HDMA_LAST (0xFFFFEC10) // (HDMA) HDMA Software Last Transfer Flag Register
4515 #define AT91C_HDMA_SREQ (0xFFFFEC08) // (HDMA) HDMA Software Single Request Register
4516 #define AT91C_HDMA_EBCIER (0xFFFFEC18) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register
4517 #define AT91C_HDMA_GCFG (0xFFFFEC00) // (HDMA) HDMA Global Configuration Register
4518 #define AT91C_HDMA_CHER (0xFFFFEC28) // (HDMA) HDMA Channel Handler Enable Register
4519 #define AT91C_HDMA_CHDR (0xFFFFEC2C) // (HDMA) HDMA Channel Handler Disable Register
4520 #define AT91C_HDMA_EBCIMR (0xFFFFEC20) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register
4521 #define AT91C_HDMA_BREQ (0xFFFFEC0C) // (HDMA) HDMA Software Chunk Transfer Request Register
4522 #define AT91C_HDMA_SYNC (0xFFFFEC14) // (HDMA) HDMA Request Synchronization Register
4523 #define AT91C_HDMA_EN (0xFFFFEC04) // (HDMA) HDMA Controller Enable Register
4524 #define AT91C_HDMA_EBCISR (0xFFFFEC24) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register
4525 #define AT91C_HDMA_CHSR (0xFFFFEC30) // (HDMA) HDMA Channel Handler Status Register
4526 // ========== Register definition for SYS peripheral ==========
4527 #define AT91C_SYS_GPBR (0xFFFFFD50) // (SYS) General Purpose Register
4528 // ========== Register definition for UHP peripheral ==========
4529 #define AT91C_UHP_HcRhPortStatus (0x00700054) // (UHP) Root Hub Port Status Register
4530 #define AT91C_UHP_HcFmRemaining (0x00700038) // (UHP) Bit time remaining in the current Frame
4531 #define AT91C_UHP_HcInterruptEnable (0x00700010) // (UHP) Interrupt Enable Register
4532 #define AT91C_UHP_HcControl (0x00700004) // (UHP) Operating modes for the Host Controller
4533 #define AT91C_UHP_HcPeriodicStart (0x00700040) // (UHP) Periodic Start
4534 #define AT91C_UHP_HcInterruptStatus (0x0070000C) // (UHP) Interrupt Status Register
4535 #define AT91C_UHP_HcRhDescriptorB (0x0070004C) // (UHP) Root Hub characteristics B
4536 #define AT91C_UHP_HcInterruptDisable (0x00700014) // (UHP) Interrupt Disable Register
4537 #define AT91C_UHP_HcPeriodCurrentED (0x0070001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
4538 #define AT91C_UHP_HcRhDescriptorA (0x00700048) // (UHP) Root Hub characteristics A
4539 #define AT91C_UHP_HcRhStatus (0x00700050) // (UHP) Root Hub Status register
4540 #define AT91C_UHP_HcBulkCurrentED (0x0070002C) // (UHP) Current endpoint of the Bulk list
4541 #define AT91C_UHP_HcControlHeadED (0x00700020) // (UHP) First Endpoint Descriptor of the Control list
4542 #define AT91C_UHP_HcLSThreshold (0x00700044) // (UHP) LS Threshold
4543 #define AT91C_UHP_HcRevision (0x00700000) // (UHP) Revision
4544 #define AT91C_UHP_HcBulkDoneHead (0x00700030) // (UHP) Last completed transfer descriptor
4545 #define AT91C_UHP_HcFmNumber (0x0070003C) // (UHP) Frame number
4546 #define AT91C_UHP_HcFmInterval (0x00700034) // (UHP) Bit time between 2 consecutive SOFs
4547 #define AT91C_UHP_HcBulkHeadED (0x00700028) // (UHP) First endpoint register of the Bulk list
4548 #define AT91C_UHP_HcHCCA (0x00700018) // (UHP) Pointer to the Host Controller Communication Area
4549 #define AT91C_UHP_HcCommandStatus (0x00700008) // (UHP) Command & status Register
4550 #define AT91C_UHP_HcControlCurrentED (0x00700024) // (UHP) Endpoint Control and Status Register
4552 // *****************************************************************************
4553 // PIO DEFINITIONS FOR AT91CAP9
4554 // *****************************************************************************
4555 #define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
4556 #define AT91C_PA0_MCI0_DA0 (AT91C_PIO_PA0) //
4557 #define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) //
4558 #define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
4559 #define AT91C_PA1_MCI0_CDA (AT91C_PIO_PA1) //
4560 #define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) //
4561 #define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
4562 #define AT91C_PA10_IRQ0 (AT91C_PIO_PA10) //
4563 #define AT91C_PA10_PWM1 (AT91C_PIO_PA10) //
4564 #define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
4565 #define AT91C_PA11_DMARQ0 (AT91C_PIO_PA11) //
4566 #define AT91C_PA11_PWM3 (AT91C_PIO_PA11) //
4567 #define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
4568 #define AT91C_PA12_CANTX (AT91C_PIO_PA12) //
4569 #define AT91C_PA12_PCK0 (AT91C_PIO_PA12) //
4570 #define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
4571 #define AT91C_PA13_CANRX (AT91C_PIO_PA13) //
4572 #define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
4573 #define AT91C_PA14_TCLK2 (AT91C_PIO_PA14) //
4574 #define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) //
4575 #define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
4576 #define AT91C_PA15_DMARQ3 (AT91C_PIO_PA15) //
4577 #define AT91C_PA15_PCK2 (AT91C_PIO_PA15) //
4578 #define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
4579 #define AT91C_PA16_MCI1_CK (AT91C_PIO_PA16) //
4580 #define AT91C_PA16_ISI_D0 (AT91C_PIO_PA16) //
4581 #define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
4582 #define AT91C_PA17_MCI1_CDA (AT91C_PIO_PA17) //
4583 #define AT91C_PA17_ISI_D1 (AT91C_PIO_PA17) //
4584 #define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
4585 #define AT91C_PA18_MCI1_DA0 (AT91C_PIO_PA18) //
4586 #define AT91C_PA18_ISI_D2 (AT91C_PIO_PA18) //
4587 #define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
4588 #define AT91C_PA19_MCI1_DA1 (AT91C_PIO_PA19) //
4589 #define AT91C_PA19_ISI_D3 (AT91C_PIO_PA19) //
4590 #define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
4591 #define AT91C_PA2_MCI0_CK (AT91C_PIO_PA2) //
4592 #define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) //
4593 #define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
4594 #define AT91C_PA20_MCI1_DA2 (AT91C_PIO_PA20) //
4595 #define AT91C_PA20_ISI_D4 (AT91C_PIO_PA20) //
4596 #define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
4597 #define AT91C_PA21_MCI1_DA3 (AT91C_PIO_PA21) //
4598 #define AT91C_PA21_ISI_D5 (AT91C_PIO_PA21) //
4599 #define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
4600 #define AT91C_PA22_TXD0 (AT91C_PIO_PA22) //
4601 #define AT91C_PA22_ISI_D6 (AT91C_PIO_PA22) //
4602 #define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
4603 #define AT91C_PA23_RXD0 (AT91C_PIO_PA23) //
4604 #define AT91C_PA23_ISI_D7 (AT91C_PIO_PA23) //
4605 #define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
4606 #define AT91C_PA24_RTS0 (AT91C_PIO_PA24) //
4607 #define AT91C_PA24_ISI_PCK (AT91C_PIO_PA24) //
4608 #define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
4609 #define AT91C_PA25_CTS0 (AT91C_PIO_PA25) //
4610 #define AT91C_PA25_ISI_HSYNC (AT91C_PIO_PA25) //
4611 #define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
4612 #define AT91C_PA26_SCK0 (AT91C_PIO_PA26) //
4613 #define AT91C_PA26_ISI_VSYNC (AT91C_PIO_PA26) //
4614 #define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
4615 #define AT91C_PA27_PCK1 (AT91C_PIO_PA27) //
4616 #define AT91C_PA27_ISI_MCK (AT91C_PIO_PA27) //
4617 #define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
4618 #define AT91C_PA28_SPI0_NPCS3A (AT91C_PIO_PA28) //
4619 #define AT91C_PA28_ISI_D8 (AT91C_PIO_PA28) //
4620 #define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
4621 #define AT91C_PA29_TIOA0 (AT91C_PIO_PA29) //
4622 #define AT91C_PA29_ISI_D9 (AT91C_PIO_PA29) //
4623 #define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
4624 #define AT91C_PA3_MCI0_DA1 (AT91C_PIO_PA3) //
4625 #define AT91C_PA3_SPI0_NPCS1 (AT91C_PIO_PA3) //
4626 #define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
4627 #define AT91C_PA30_TIOB0 (AT91C_PIO_PA30) //
4628 #define AT91C_PA30_ISI_D10 (AT91C_PIO_PA30) //
4629 #define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
4630 #define AT91C_PA31_DMARQ1 (AT91C_PIO_PA31) //
4631 #define AT91C_PA31_ISI_D11 (AT91C_PIO_PA31) //
4632 #define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
4633 #define AT91C_PA4_MCI0_DA2 (AT91C_PIO_PA4) //
4634 #define AT91C_PA4_SPI0_NPCS2A (AT91C_PIO_PA4) //
4635 #define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
4636 #define AT91C_PA5_MCI0_DA3 (AT91C_PIO_PA5) //
4637 #define AT91C_PA5_SPI0_NPCS0 (AT91C_PIO_PA5) //
4638 #define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
4639 #define AT91C_PA6_AC97FS (AT91C_PIO_PA6) //
4640 #define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
4641 #define AT91C_PA7_AC97CK (AT91C_PIO_PA7) //
4642 #define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
4643 #define AT91C_PA8_AC97TX (AT91C_PIO_PA8) //
4644 #define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
4645 #define AT91C_PA9_AC97RX (AT91C_PIO_PA9) //
4646 #define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
4647 #define AT91C_PB0_TF0 (AT91C_PIO_PB0) //
4648 #define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
4649 #define AT91C_PB1_TK0 (AT91C_PIO_PB1) //
4650 #define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
4651 #define AT91C_PB10_RK1 (AT91C_PIO_PB10) //
4652 #define AT91C_PB10_PCK1 (AT91C_PIO_PB10) //
4653 #define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
4654 #define AT91C_PB11_RF1 (AT91C_PIO_PB11) //
4655 #define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
4656 #define AT91C_PB12_SPI1_MISO (AT91C_PIO_PB12) //
4657 #define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
4658 #define AT91C_PB13_SPI1_MOSI (AT91C_PIO_PB13) //
4659 #define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
4660 #define AT91C_PB14_SPI1_SPCK (AT91C_PIO_PB14) //
4661 #define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
4662 #define AT91C_PB15_SPI1_NPCS0 (AT91C_PIO_PB15) //
4663 #define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
4664 #define AT91C_PB16_SPI1_NPCS1 (AT91C_PIO_PB16) //
4665 #define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
4666 #define AT91C_PB17_SPI1_NPCS2B (AT91C_PIO_PB17) //
4667 #define AT91C_PB17_AD0 (AT91C_PIO_PB17) //
4668 #define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
4669 #define AT91C_PB18_SPI1_NPCS3B (AT91C_PIO_PB18) //
4670 #define AT91C_PB18_AD1 (AT91C_PIO_PB18) //
4671 #define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
4672 #define AT91C_PB19_PWM0 (AT91C_PIO_PB19) //
4673 #define AT91C_PB19_AD2 (AT91C_PIO_PB19) //
4674 #define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
4675 #define AT91C_PB2_TD0 (AT91C_PIO_PB2) //
4676 #define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
4677 #define AT91C_PB20_PWM1 (AT91C_PIO_PB20) //
4678 #define AT91C_PB20_AD3 (AT91C_PIO_PB20) //
4679 #define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
4680 #define AT91C_PB21_E_TXCK (AT91C_PIO_PB21) //
4681 #define AT91C_PB21_TIOA2 (AT91C_PIO_PB21) //
4682 #define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
4683 #define AT91C_PB22_E_RXDV (AT91C_PIO_PB22) //
4684 #define AT91C_PB22_TIOB2 (AT91C_PIO_PB22) //
4685 #define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
4686 #define AT91C_PB23_E_TX0 (AT91C_PIO_PB23) //
4687 #define AT91C_PB23_PCK3 (AT91C_PIO_PB23) //
4688 #define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
4689 #define AT91C_PB24_E_TX1 (AT91C_PIO_PB24) //
4690 #define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
4691 #define AT91C_PB25_E_RX0 (AT91C_PIO_PB25) //
4692 #define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
4693 #define AT91C_PB26_E_RX1 (AT91C_PIO_PB26) //
4694 #define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
4695 #define AT91C_PB27_E_RXER (AT91C_PIO_PB27) //
4696 #define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
4697 #define AT91C_PB28_E_TXEN (AT91C_PIO_PB28) //
4698 #define AT91C_PB28_TCLK0 (AT91C_PIO_PB28) //
4699 #define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
4700 #define AT91C_PB29_E_MDC (AT91C_PIO_PB29) //
4701 #define AT91C_PB29_PWM3 (AT91C_PIO_PB29) //
4702 #define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
4703 #define AT91C_PB3_RD0 (AT91C_PIO_PB3) //
4704 #define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
4705 #define AT91C_PB30_E_MDIO (AT91C_PIO_PB30) //
4706 #define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31
4707 #define AT91C_PB31_ADTRIG (AT91C_PIO_PB31) //
4708 #define AT91C_PB31_E_F100 (AT91C_PIO_PB31) //
4709 #define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
4710 #define AT91C_PB4_RK0 (AT91C_PIO_PB4) //
4711 #define AT91C_PB4_TWD (AT91C_PIO_PB4) //
4712 #define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
4713 #define AT91C_PB5_RF0 (AT91C_PIO_PB5) //
4714 #define AT91C_PB5_TWCK (AT91C_PIO_PB5) //
4715 #define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
4716 #define AT91C_PB6_TF1 (AT91C_PIO_PB6) //
4717 #define AT91C_PB6_TIOA1 (AT91C_PIO_PB6) //
4718 #define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
4719 #define AT91C_PB7_TK1 (AT91C_PIO_PB7) //
4720 #define AT91C_PB7_TIOB1 (AT91C_PIO_PB7) //
4721 #define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
4722 #define AT91C_PB8_TD1 (AT91C_PIO_PB8) //
4723 #define AT91C_PB8_PWM2 (AT91C_PIO_PB8) //
4724 #define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
4725 #define AT91C_PB9_RD1 (AT91C_PIO_PB9) //
4726 #define AT91C_PB9_LCDCC (AT91C_PIO_PB9) //
4727 #define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0
4728 #define AT91C_PC0_LCDVSYNC (AT91C_PIO_PC0) //
4729 #define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1
4730 #define AT91C_PC1_LCDHSYNC (AT91C_PIO_PC1) //
4731 #define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10
4732 #define AT91C_PC10_LCDD6 (AT91C_PIO_PC10) //
4733 #define AT91C_PC10_LCDD11B (AT91C_PIO_PC10) //
4734 #define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11
4735 #define AT91C_PC11_LCDD7 (AT91C_PIO_PC11) //
4736 #define AT91C_PC11_LCDD12B (AT91C_PIO_PC11) //
4737 #define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12
4738 #define AT91C_PC12_LCDD8 (AT91C_PIO_PC12) //
4739 #define AT91C_PC12_LCDD13B (AT91C_PIO_PC12) //
4740 #define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13
4741 #define AT91C_PC13_LCDD9 (AT91C_PIO_PC13) //
4742 #define AT91C_PC13_LCDD14B (AT91C_PIO_PC13) //
4743 #define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14
4744 #define AT91C_PC14_LCDD10 (AT91C_PIO_PC14) //
4745 #define AT91C_PC14_LCDD15B (AT91C_PIO_PC14) //
4746 #define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15
4747 #define AT91C_PC15_LCDD11 (AT91C_PIO_PC15) //
4748 #define AT91C_PC15_LCDD19B (AT91C_PIO_PC15) //
4749 #define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16
4750 #define AT91C_PC16_LCDD12 (AT91C_PIO_PC16) //
4751 #define AT91C_PC16_LCDD20B (AT91C_PIO_PC16) //
4752 #define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17
4753 #define AT91C_PC17_LCDD13 (AT91C_PIO_PC17) //
4754 #define AT91C_PC17_LCDD21B (AT91C_PIO_PC17) //
4755 #define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18
4756 #define AT91C_PC18_LCDD14 (AT91C_PIO_PC18) //
4757 #define AT91C_PC18_LCDD22B (AT91C_PIO_PC18) //
4758 #define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19
4759 #define AT91C_PC19_LCDD15 (AT91C_PIO_PC19) //
4760 #define AT91C_PC19_LCDD23B (AT91C_PIO_PC19) //
4761 #define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2
4762 #define AT91C_PC2_LCDDOTCK (AT91C_PIO_PC2) //
4763 #define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20
4764 #define AT91C_PC20_LCDD16 (AT91C_PIO_PC20) //
4765 #define AT91C_PC20_E_TX2 (AT91C_PIO_PC20) //
4766 #define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21
4767 #define AT91C_PC21_LCDD17 (AT91C_PIO_PC21) //
4768 #define AT91C_PC21_E_TX3 (AT91C_PIO_PC21) //
4769 #define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22
4770 #define AT91C_PC22_LCDD18 (AT91C_PIO_PC22) //
4771 #define AT91C_PC22_E_RX2 (AT91C_PIO_PC22) //
4772 #define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23
4773 #define AT91C_PC23_LCDD19 (AT91C_PIO_PC23) //
4774 #define AT91C_PC23_E_RX3 (AT91C_PIO_PC23) //
4775 #define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24
4776 #define AT91C_PC24_LCDD20 (AT91C_PIO_PC24) //
4777 #define AT91C_PC24_E_TXER (AT91C_PIO_PC24) //
4778 #define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25
4779 #define AT91C_PC25_LCDD21 (AT91C_PIO_PC25) //
4780 #define AT91C_PC25_E_CRS (AT91C_PIO_PC25) //
4781 #define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26
4782 #define AT91C_PC26_LCDD22 (AT91C_PIO_PC26) //
4783 #define AT91C_PC26_E_COL (AT91C_PIO_PC26) //
4784 #define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27
4785 #define AT91C_PC27_LCDD23 (AT91C_PIO_PC27) //
4786 #define AT91C_PC27_E_RXCK (AT91C_PIO_PC27) //
4787 #define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28
4788 #define AT91C_PC28_PWM0 (AT91C_PIO_PC28) //
4789 #define AT91C_PC28_TCLK1 (AT91C_PIO_PC28) //
4790 #define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29
4791 #define AT91C_PC29_PCK0 (AT91C_PIO_PC29) //
4792 #define AT91C_PC29_PWM2 (AT91C_PIO_PC29) //
4793 #define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3
4794 #define AT91C_PC3_LCDDEN (AT91C_PIO_PC3) //
4795 #define AT91C_PC3_PWM1 (AT91C_PIO_PC3) //
4796 #define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30
4797 #define AT91C_PC30_DRXD (AT91C_PIO_PC30) //
4798 #define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31
4799 #define AT91C_PC31_DTXD (AT91C_PIO_PC31) //
4800 #define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4
4801 #define AT91C_PC4_LCDD0 (AT91C_PIO_PC4) //
4802 #define AT91C_PC4_LCDD3B (AT91C_PIO_PC4) //
4803 #define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5
4804 #define AT91C_PC5_LCDD1 (AT91C_PIO_PC5) //
4805 #define AT91C_PC5_LCDD4B (AT91C_PIO_PC5) //
4806 #define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6
4807 #define AT91C_PC6_LCDD2 (AT91C_PIO_PC6) //
4808 #define AT91C_PC6_LCDD5B (AT91C_PIO_PC6) //
4809 #define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7
4810 #define AT91C_PC7_LCDD3 (AT91C_PIO_PC7) //
4811 #define AT91C_PC7_LCDD6B (AT91C_PIO_PC7) //
4812 #define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8
4813 #define AT91C_PC8_LCDD4 (AT91C_PIO_PC8) //
4814 #define AT91C_PC8_LCDD7B (AT91C_PIO_PC8) //
4815 #define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9
4816 #define AT91C_PC9_LCDD5 (AT91C_PIO_PC9) //
4817 #define AT91C_PC9_LCDD10B (AT91C_PIO_PC9) //
4818 #define AT91C_PIO_PD0 (1 << 0) // Pin Controlled by PD0
4819 #define AT91C_PD0_TXD1 (AT91C_PIO_PD0) //
4820 #define AT91C_PD0_SPI0_NPCS2D (AT91C_PIO_PD0) //
4821 #define AT91C_PIO_PD1 (1 << 1) // Pin Controlled by PD1
4822 #define AT91C_PD1_RXD1 (AT91C_PIO_PD1) //
4823 #define AT91C_PD1_SPI0_NPCS3D (AT91C_PIO_PD1) //
4824 #define AT91C_PIO_PD10 (1 << 10) // Pin Controlled by PD10
4825 #define AT91C_PD10_EBI_CFCE2 (AT91C_PIO_PD10) //
4826 #define AT91C_PD10_SCK1 (AT91C_PIO_PD10) //
4827 #define AT91C_PIO_PD11 (1 << 11) // Pin Controlled by PD11
4828 #define AT91C_PD11_EBI_NCS2 (AT91C_PIO_PD11) //
4829 #define AT91C_PIO_PD12 (1 << 12) // Pin Controlled by PD12
4830 #define AT91C_PD12_EBI_A23 (AT91C_PIO_PD12) //
4831 #define AT91C_PIO_PD13 (1 << 13) // Pin Controlled by PD13
4832 #define AT91C_PD13_EBI_A24 (AT91C_PIO_PD13) //
4833 #define AT91C_PIO_PD14 (1 << 14) // Pin Controlled by PD14
4834 #define AT91C_PD14_EBI_A25_CFRNW (AT91C_PIO_PD14) //
4835 #define AT91C_PIO_PD15 (1 << 15) // Pin Controlled by PD15
4836 #define AT91C_PD15_EBI_NCS3_NANDCS (AT91C_PIO_PD15) //
4837 #define AT91C_PIO_PD16 (1 << 16) // Pin Controlled by PD16
4838 #define AT91C_PD16_EBI_D16 (AT91C_PIO_PD16) //
4839 #define AT91C_PIO_PD17 (1 << 17) // Pin Controlled by PD17
4840 #define AT91C_PD17_EBI_D17 (AT91C_PIO_PD17) //
4841 #define AT91C_PIO_PD18 (1 << 18) // Pin Controlled by PD18
4842 #define AT91C_PD18_EBI_D18 (AT91C_PIO_PD18) //
4843 #define AT91C_PIO_PD19 (1 << 19) // Pin Controlled by PD19
4844 #define AT91C_PD19_EBI_D19 (AT91C_PIO_PD19) //
4845 #define AT91C_PIO_PD2 (1 << 2) // Pin Controlled by PD2
4846 #define AT91C_PD2_TXD2 (AT91C_PIO_PD2) //
4847 #define AT91C_PD2_SPI1_NPCS2D (AT91C_PIO_PD2) //
4848 #define AT91C_PIO_PD20 (1 << 20) // Pin Controlled by PD20
4849 #define AT91C_PD20_EBI_D20 (AT91C_PIO_PD20) //
4850 #define AT91C_PIO_PD21 (1 << 21) // Pin Controlled by PD21
4851 #define AT91C_PD21_EBI_D21 (AT91C_PIO_PD21) //
4852 #define AT91C_PIO_PD22 (1 << 22) // Pin Controlled by PD22
4853 #define AT91C_PD22_EBI_D22 (AT91C_PIO_PD22) //
4854 #define AT91C_PIO_PD23 (1 << 23) // Pin Controlled by PD23
4855 #define AT91C_PD23_EBI_D23 (AT91C_PIO_PD23) //
4856 #define AT91C_PIO_PD24 (1 << 24) // Pin Controlled by PD24
4857 #define AT91C_PD24_EBI_D24 (AT91C_PIO_PD24) //
4858 #define AT91C_PIO_PD25 (1 << 25) // Pin Controlled by PD25
4859 #define AT91C_PD25_EBI_D25 (AT91C_PIO_PD25) //
4860 #define AT91C_PIO_PD26 (1 << 26) // Pin Controlled by PD26
4861 #define AT91C_PD26_EBI_D26 (AT91C_PIO_PD26) //
4862 #define AT91C_PIO_PD27 (1 << 27) // Pin Controlled by PD27
4863 #define AT91C_PD27_EBI_D27 (AT91C_PIO_PD27) //
4864 #define AT91C_PIO_PD28 (1 << 28) // Pin Controlled by PD28
4865 #define AT91C_PD28_EBI_D28 (AT91C_PIO_PD28) //
4866 #define AT91C_PIO_PD29 (1 << 29) // Pin Controlled by PD29
4867 #define AT91C_PD29_EBI_D29 (AT91C_PIO_PD29) //
4868 #define AT91C_PIO_PD3 (1 << 3) // Pin Controlled by PD3
4869 #define AT91C_PD3_RXD2 (AT91C_PIO_PD3) //
4870 #define AT91C_PD3_SPI1_NPCS3D (AT91C_PIO_PD3) //
4871 #define AT91C_PIO_PD30 (1 << 30) // Pin Controlled by PD30
4872 #define AT91C_PD30_EBI_D30 (AT91C_PIO_PD30) //
4873 #define AT91C_PIO_PD31 (1 << 31) // Pin Controlled by PD31
4874 #define AT91C_PD31_EBI_D31 (AT91C_PIO_PD31) //
4875 #define AT91C_PIO_PD4 (1 << 4) // Pin Controlled by PD4
4876 #define AT91C_PD4_FIQ (AT91C_PIO_PD4) //
4877 #define AT91C_PIO_PD5 (1 << 5) // Pin Controlled by PD5
4878 #define AT91C_PD5_DMARQ2 (AT91C_PIO_PD5) //
4879 #define AT91C_PD5_RTS2 (AT91C_PIO_PD5) //
4880 #define AT91C_PIO_PD6 (1 << 6) // Pin Controlled by PD6
4881 #define AT91C_PD6_EBI_NWAIT (AT91C_PIO_PD6) //
4882 #define AT91C_PD6_CTS2 (AT91C_PIO_PD6) //
4883 #define AT91C_PIO_PD7 (1 << 7) // Pin Controlled by PD7
4884 #define AT91C_PD7_EBI_NCS4_CFCS0 (AT91C_PIO_PD7) //
4885 #define AT91C_PD7_RTS1 (AT91C_PIO_PD7) //
4886 #define AT91C_PIO_PD8 (1 << 8) // Pin Controlled by PD8
4887 #define AT91C_PD8_EBI_NCS5_CFCS1 (AT91C_PIO_PD8) //
4888 #define AT91C_PD8_CTS1 (AT91C_PIO_PD8) //
4889 #define AT91C_PIO_PD9 (1 << 9) // Pin Controlled by PD9
4890 #define AT91C_PD9_EBI_CFCE1 (AT91C_PIO_PD9) //
4891 #define AT91C_PD9_SCK2 (AT91C_PIO_PD9) //
4893 // *****************************************************************************
4894 // PERIPHERAL ID DEFINITIONS FOR AT91CAP9
4895 // *****************************************************************************
4896 #define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
4897 #define AT91C_ID_SYS ( 1) // System Controller
4898 #define AT91C_ID_PIOABCDE ( 2) // Parallel IO Controller A, Parallel IO Controller B, Parallel IO Controller C, Parallel IO Controller D, Parallel IO Controller E
4899 #define AT91C_ID_MPB0 ( 3) // MP Block Peripheral 0
4900 #define AT91C_ID_MPB1 ( 4) // MP Block Peripheral 1
4901 #define AT91C_ID_MPB2 ( 5) // MP Block Peripheral 2
4902 #define AT91C_ID_MPB3 ( 6) // MP Block Peripheral 3
4903 #define AT91C_ID_MPB4 ( 7) // MP Block Peripheral 4
4904 #define AT91C_ID_US0 ( 8) // USART 0
4905 #define AT91C_ID_US1 ( 9) // USART 1
4906 #define AT91C_ID_US2 (10) // USART 2
4907 #define AT91C_ID_MCI0 (11) // Multimedia Card Interface 0
4908 #define AT91C_ID_MCI1 (12) // Multimedia Card Interface 1
4909 #define AT91C_ID_CAN (13) // CAN Controller
4910 #define AT91C_ID_TWI (14) // Two-Wire Interface
4911 #define AT91C_ID_SPI0 (15) // Serial Peripheral Interface 0
4912 #define AT91C_ID_SPI1 (16) // Serial Peripheral Interface 1
4913 #define AT91C_ID_SSC0 (17) // Serial Synchronous Controller 0
4914 #define AT91C_ID_SSC1 (18) // Serial Synchronous Controller 1
4915 #define AT91C_ID_AC97C (19) // AC97 Controller
4916 #define AT91C_ID_TC012 (20) // Timer Counter 0, Timer Counter 1, Timer Counter 2
4917 #define AT91C_ID_PWMC (21) // PWM Controller
4918 #define AT91C_ID_EMAC (22) // Ethernet Mac
4919 #define AT91C_ID_AESTDES (23) // Advanced Encryption Standard, Triple DES
4920 #define AT91C_ID_ADC (24) // ADC Controller
4921 #define AT91C_ID_HISI (25) // Image Sensor Interface
4922 #define AT91C_ID_LCDC (26) // LCD Controller
4923 #define AT91C_ID_HDMA (27) // HDMA Controller
4924 #define AT91C_ID_UDPHS (28) // USB High Speed Device Port
4925 #define AT91C_ID_UHP (29) // USB Host Port
4926 #define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
4927 #define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
4928 #define AT91C_ALL_INT (0xFFFFFFFF) // ALL VALID INTERRUPTS
4930 // *****************************************************************************
4931 // BASE ADDRESS DEFINITIONS FOR AT91CAP9
4932 // *****************************************************************************
4933 #define AT91C_BASE_HECC (0xFFFFE200) // (HECC) Base Address
4934 #define AT91C_BASE_BCRAMC (0xFFFFE400) // (BCRAMC) Base Address
4935 #define AT91C_BASE_SDRAMC (0xFFFFE600) // (SDRAMC) Base Address
4936 #define AT91C_BASE_SDDRC (0xFFFFE600) // (SDDRC) Base Address
4937 #define AT91C_BASE_SMC (0xFFFFE800) // (SMC) Base Address
4938 #define AT91C_BASE_MATRIX_PRS (0xFFFFEA80) // (MATRIX_PRS) Base Address
4939 #define AT91C_BASE_MATRIX (0xFFFFEA00) // (MATRIX) Base Address
4940 #define AT91C_BASE_CCFG (0xFFFFEB10) // (CCFG) Base Address
4941 #define AT91C_BASE_PDC_DBGU (0xFFFFEF00) // (PDC_DBGU) Base Address
4942 #define AT91C_BASE_DBGU (0xFFFFEE00) // (DBGU) Base Address
4943 #define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address
4944 #define AT91C_BASE_PIOA (0xFFFFF200) // (PIOA) Base Address
4945 #define AT91C_BASE_PIOB (0xFFFFF400) // (PIOB) Base Address
4946 #define AT91C_BASE_PIOC (0xFFFFF600) // (PIOC) Base Address
4947 #define AT91C_BASE_PIOD (0xFFFFF800) // (PIOD) Base Address
4948 #define AT91C_BASE_CKGR (0xFFFFFC1C) // (CKGR) Base Address
4949 #define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address
4950 #define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address
4951 #define AT91C_BASE_SHDWC (0xFFFFFD10) // (SHDWC) Base Address
4952 #define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address
4953 #define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address
4954 #define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address
4955 #define AT91C_BASE_UDP (0xFFF78000) // (UDP) Base Address
4956 #define AT91C_BASE_UDPHS_EPTFIFO (0x00600000) // (UDPHS_EPTFIFO) Base Address
4957 #define AT91C_BASE_UDPHS_EPT_0 (0xFFF78100) // (UDPHS_EPT_0) Base Address
4958 #define AT91C_BASE_UDPHS_EPT_1 (0xFFF78120) // (UDPHS_EPT_1) Base Address
4959 #define AT91C_BASE_UDPHS_EPT_2 (0xFFF78140) // (UDPHS_EPT_2) Base Address
4960 #define AT91C_BASE_UDPHS_EPT_3 (0xFFF78160) // (UDPHS_EPT_3) Base Address
4961 #define AT91C_BASE_UDPHS_EPT_4 (0xFFF78180) // (UDPHS_EPT_4) Base Address
4962 #define AT91C_BASE_UDPHS_EPT_5 (0xFFF781A0) // (UDPHS_EPT_5) Base Address
4963 #define AT91C_BASE_UDPHS_EPT_6 (0xFFF781C0) // (UDPHS_EPT_6) Base Address
4964 #define AT91C_BASE_UDPHS_EPT_7 (0xFFF781E0) // (UDPHS_EPT_7) Base Address
4965 #define AT91C_BASE_UDPHS_EPT_8 (0xFFF78200) // (UDPHS_EPT_8) Base Address
4966 #define AT91C_BASE_UDPHS_EPT_9 (0xFFF78220) // (UDPHS_EPT_9) Base Address
4967 #define AT91C_BASE_UDPHS_EPT_10 (0xFFF78240) // (UDPHS_EPT_10) Base Address
4968 #define AT91C_BASE_UDPHS_EPT_11 (0xFFF78260) // (UDPHS_EPT_11) Base Address
4969 #define AT91C_BASE_UDPHS_EPT_12 (0xFFF78280) // (UDPHS_EPT_12) Base Address
4970 #define AT91C_BASE_UDPHS_EPT_13 (0xFFF782A0) // (UDPHS_EPT_13) Base Address
4971 #define AT91C_BASE_UDPHS_EPT_14 (0xFFF782C0) // (UDPHS_EPT_14) Base Address
4972 #define AT91C_BASE_UDPHS_EPT_15 (0xFFF782E0) // (UDPHS_EPT_15) Base Address
4973 #define AT91C_BASE_UDPHS_DMA_1 (0xFFF78310) // (UDPHS_DMA_1) Base Address
4974 #define AT91C_BASE_UDPHS_DMA_2 (0xFFF78320) // (UDPHS_DMA_2) Base Address
4975 #define AT91C_BASE_UDPHS_DMA_3 (0xFFF78330) // (UDPHS_DMA_3) Base Address
4976 #define AT91C_BASE_UDPHS_DMA_4 (0xFFF78340) // (UDPHS_DMA_4) Base Address
4977 #define AT91C_BASE_UDPHS_DMA_5 (0xFFF78350) // (UDPHS_DMA_5) Base Address
4978 #define AT91C_BASE_UDPHS_DMA_6 (0xFFF78360) // (UDPHS_DMA_6) Base Address
4979 #define AT91C_BASE_UDPHS_DMA_7 (0xFFF78370) // (UDPHS_DMA_7) Base Address
4980 #define AT91C_BASE_UDPHS (0xFFF78000) // (UDPHS) Base Address
4981 #define AT91C_BASE_TC0 (0xFFF7C000) // (TC0) Base Address
4982 #define AT91C_BASE_TC1 (0xFFF7C040) // (TC1) Base Address
4983 #define AT91C_BASE_TC2 (0xFFF7C080) // (TC2) Base Address
4984 #define AT91C_BASE_TCB0 (0xFFF7C000) // (TCB0) Base Address
4985 #define AT91C_BASE_TCB1 (0xFFF7C040) // (TCB1) Base Address
4986 #define AT91C_BASE_TCB2 (0xFFF7C080) // (TCB2) Base Address
4987 #define AT91C_BASE_PDC_MCI0 (0xFFF80100) // (PDC_MCI0) Base Address
4988 #define AT91C_BASE_MCI0 (0xFFF80000) // (MCI0) Base Address
4989 #define AT91C_BASE_PDC_MCI1 (0xFFF84100) // (PDC_MCI1) Base Address
4990 #define AT91C_BASE_MCI1 (0xFFF84000) // (MCI1) Base Address
4991 #define AT91C_BASE_PDC_TWI (0xFFF88100) // (PDC_TWI) Base Address
4992 #define AT91C_BASE_TWI (0xFFF88000) // (TWI) Base Address
4993 #define AT91C_BASE_PDC_US0 (0xFFF8C100) // (PDC_US0) Base Address
4994 #define AT91C_BASE_US0 (0xFFF8C000) // (US0) Base Address
4995 #define AT91C_BASE_PDC_US1 (0xFFF90100) // (PDC_US1) Base Address
4996 #define AT91C_BASE_US1 (0xFFF90000) // (US1) Base Address
4997 #define AT91C_BASE_PDC_US2 (0xFFF94100) // (PDC_US2) Base Address
4998 #define AT91C_BASE_US2 (0xFFF94000) // (US2) Base Address
4999 #define AT91C_BASE_PDC_SSC0 (0xFFF98100) // (PDC_SSC0) Base Address
5000 #define AT91C_BASE_SSC0 (0xFFF98000) // (SSC0) Base Address
5001 #define AT91C_BASE_PDC_SSC1 (0xFFF9C100) // (PDC_SSC1) Base Address
5002 #define AT91C_BASE_SSC1 (0xFFF9C000) // (SSC1) Base Address
5003 #define AT91C_BASE_PDC_AC97C (0xFFFA0100) // (PDC_AC97C) Base Address
5004 #define AT91C_BASE_AC97C (0xFFFA0000) // (AC97C) Base Address
5005 #define AT91C_BASE_PDC_SPI0 (0xFFFA4100) // (PDC_SPI0) Base Address
5006 #define AT91C_BASE_SPI0 (0xFFFA4000) // (SPI0) Base Address
5007 #define AT91C_BASE_PDC_SPI1 (0xFFFA8100) // (PDC_SPI1) Base Address
5008 #define AT91C_BASE_SPI1 (0xFFFA8000) // (SPI1) Base Address
5009 #define AT91C_BASE_CAN_MB0 (0xFFFAC200) // (CAN_MB0) Base Address
5010 #define AT91C_BASE_CAN_MB1 (0xFFFAC220) // (CAN_MB1) Base Address
5011 #define AT91C_BASE_CAN_MB2 (0xFFFAC240) // (CAN_MB2) Base Address
5012 #define AT91C_BASE_CAN_MB3 (0xFFFAC260) // (CAN_MB3) Base Address
5013 #define AT91C_BASE_CAN_MB4 (0xFFFAC280) // (CAN_MB4) Base Address
5014 #define AT91C_BASE_CAN_MB5 (0xFFFAC2A0) // (CAN_MB5) Base Address
5015 #define AT91C_BASE_CAN_MB6 (0xFFFAC2C0) // (CAN_MB6) Base Address
5016 #define AT91C_BASE_CAN_MB7 (0xFFFAC2E0) // (CAN_MB7) Base Address
5017 #define AT91C_BASE_CAN_MB8 (0xFFFAC300) // (CAN_MB8) Base Address
5018 #define AT91C_BASE_CAN_MB9 (0xFFFAC320) // (CAN_MB9) Base Address
5019 #define AT91C_BASE_CAN_MB10 (0xFFFAC340) // (CAN_MB10) Base Address
5020 #define AT91C_BASE_CAN_MB11 (0xFFFAC360) // (CAN_MB11) Base Address
5021 #define AT91C_BASE_CAN_MB12 (0xFFFAC380) // (CAN_MB12) Base Address
5022 #define AT91C_BASE_CAN_MB13 (0xFFFAC3A0) // (CAN_MB13) Base Address
5023 #define AT91C_BASE_CAN_MB14 (0xFFFAC3C0) // (CAN_MB14) Base Address
5024 #define AT91C_BASE_CAN_MB15 (0xFFFAC3E0) // (CAN_MB15) Base Address
5025 #define AT91C_BASE_CAN (0xFFFAC000) // (CAN) Base Address
5026 #define AT91C_BASE_PDC_AES (0xFFFB0100) // (PDC_AES) Base Address
5027 #define AT91C_BASE_AES (0xFFFB0000) // (AES) Base Address
5028 #define AT91C_BASE_PDC_TDES (0xFFFB0100) // (PDC_TDES) Base Address
5029 #define AT91C_BASE_TDES (0xFFFB0000) // (TDES) Base Address
5030 #define AT91C_BASE_PWMC_CH0 (0xFFFB8200) // (PWMC_CH0) Base Address
5031 #define AT91C_BASE_PWMC_CH1 (0xFFFB8220) // (PWMC_CH1) Base Address
5032 #define AT91C_BASE_PWMC_CH2 (0xFFFB8240) // (PWMC_CH2) Base Address
5033 #define AT91C_BASE_PWMC_CH3 (0xFFFB8260) // (PWMC_CH3) Base Address
5034 #define AT91C_BASE_PWMC (0xFFFB8000) // (PWMC) Base Address
5035 #define AT91C_BASE_MACB (0xFFFBC000) // (MACB) Base Address
5036 #define AT91C_BASE_PDC_ADC (0xFFFC0100) // (PDC_ADC) Base Address
5037 #define AT91C_BASE_ADC (0xFFFC0000) // (ADC) Base Address
5038 #define AT91C_BASE_HISI (0xFFFC4000) // (HISI) Base Address
5039 #define AT91C_BASE_LCDC (0x00500000) // (LCDC) Base Address
5040 #define AT91C_BASE_HDMA_CH_0 (0xFFFFEC3C) // (HDMA_CH_0) Base Address
5041 #define AT91C_BASE_HDMA_CH_1 (0xFFFFEC64) // (HDMA_CH_1) Base Address
5042 #define AT91C_BASE_HDMA_CH_2 (0xFFFFEC8C) // (HDMA_CH_2) Base Address
5043 #define AT91C_BASE_HDMA_CH_3 (0xFFFFECB4) // (HDMA_CH_3) Base Address
5044 #define AT91C_BASE_HDMA (0xFFFFEC00) // (HDMA) Base Address
5045 #define AT91C_BASE_SYS (0xFFFFE200) // (SYS) Base Address
5046 #define AT91C_BASE_UHP (0x00700000) // (UHP) Base Address
5048 // *****************************************************************************
5049 // MEMORY MAPPING DEFINITIONS FOR AT91CAP9
5050 // *****************************************************************************
5052 #define AT91C_IRAM (0x00100000) // 16-KBytes FAST SRAM base address
5053 #define AT91C_IRAM_SIZE (0x00004000) // 16-KBytes FAST SRAM size in byte (16 Kbytes)
5055 #define AT91C_IRAM_MIN (0x00100000) // Minimum Internal RAM base address
5056 #define AT91C_IRAM_MIN_SIZE (0x00004000) // Minimum Internal RAM size in byte (16 Kbytes)
5058 #define AT91C_DPR (0x00200000) // base address
5059 #define AT91C_DPR_SIZE (0x00004000) // size in byte (16 Kbytes)
5061 #define AT91C_IROM (0x00400000) // Internal ROM base address
5062 #define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes)
5064 #define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address
5065 #define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
5067 #define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address
5068 #define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
5070 #define AT91C_EBI_BCRAM (0x20000000) // BCRAM on EBI Chip Select 1 base address
5071 #define AT91C_EBI_BCRAM_SIZE (0x10000000) // BCRAM on EBI Chip Select 1 size in byte (262144 Kbytes)
5073 #define AT91C_EBI_BCRAM_16BIT (0x20000000) // BCRAM on EBI Chip Select 1 base address
5074 #define AT91C_EBI_BCRAM_16BIT_SIZE (0x02000000) // BCRAM on EBI Chip Select 1 size in byte (32768 Kbytes)
5076 #define AT91C_EBI_BCRAM_32BIT (0x20000000) // BCRAM on EBI Chip Select 1 base address
5077 #define AT91C_EBI_BCRAM_32BIT_SIZE (0x04000000) // BCRAM on EBI Chip Select 1 size in byte (65536 Kbytes)
5079 #define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address
5080 #define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
5082 #define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address
5083 #define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
5085 #define AT91C_EBI_SM (0x40000000) // SmartMedia on EBI Chip Select 3 base address
5086 #define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on EBI Chip Select 3 size in byte (262144 Kbytes)
5088 #define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address
5089 #define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
5091 #define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on EBI Chip Select 4 base address
5092 #define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on EBI Chip Select 4 size in byte (262144 Kbytes)
5094 #define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address
5095 #define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
5097 #define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on EBI Chip Select 5 base address
5098 #define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on EBI Chip Select 5 size in byte (262144 Kbytes)
5100 #define AT91C_EBI_SDRAM (0x70000000) // SDRAM on EBI Chip Select 6 base address
5101 #define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 6 size in byte (262144 Kbytes)
5103 #define AT91C_EBI_SDRAM_16BIT (0x70000000) // SDRAM on EBI Chip Select 6 base address
5104 #define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 6 size in byte (32768 Kbytes)
5106 #define AT91C_EBI_SDRAM_32BIT (0x70000000) // SDRAM on EBI Chip Select 6 base address
5107 #define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 6 size in byte (65536 Kbytes)
5109 #define AT91C_NR_PIO (32 * 4)
