2 * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
21 #include <mach/imx-regs.h>
26 #define CFG_MPCTL0_VAL 0x00321431
28 #define CFG_MPCTL0_VAL 0x040e200e
34 #define CFG_SPCTL0_VAL 0x04002400
38 #define CFG_SPCTL0_VAL 0x04001800
42 #define CFG_SPCTL0_VAL 0x08001800
45 /* Das ist der BCLK Divider, der aus der System PLL
46 BCLK und HCLK erzeugt:
47 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
48 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
49 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
50 0x2f001003 : 192MHz/5=38,4MHz
53 Bit 21: MPLL Restart */
56 #define CFG_CSCR_VAL 0x2f030003
60 #define CFG_CSCR_VAL 0x2f030403
62 /* Bit[0:3] contain PERCLK1DIV for UART 1
63 0x000b00b ->b<- -> 192MHz/12=16MHz
64 0x000b00b ->8<- -> 144MHz/09=16MHz
65 0x000b00b ->3<- -> 64MHz/4=16MHz */
68 #define CFG_PCDR_VAL 0x000b00b5
72 #define CFG_PCDR_VAL 0x000b00b3
76 #define CFG_PCDR_VAL 0x000b00b8
79 #define writel(val, reg) \
84 .globl board_init_lowlevel
89 /* Change PERCLK1DIV to 14 ie 14+1 */
90 writel(CFG_PCDR_VAL, PCDR)
92 /* set MCU PLL Control Register 0 */
93 writel(CFG_MPCTL0_VAL, MPCTL0)
95 /* set mpll restart bit */
111 /* set System PLL Control Register 0 */
112 writel(CFG_SPCTL0_VAL, SPCTL0)
114 /* set spll restart bit */
130 writel(CFG_CSCR_VAL, CSCR)
132 /* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
135 * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
136 * register 1, this stops it using the output of the PLL and thus runs at the
137 * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
138 * use the value set in the CM_OSC registers...regardless of what you set it
139 * too! Thus, although i thought i was running at 140MHz, i'm actually running
142 * Slapping this into my bootloader does the trick...
144 * MRC p15,0,r0,c1,c0,0 ; read core configuration register
145 * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
146 * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
150 ORR r0,r0,#0xC0000000
153 /* Skip SDRAM initialization if we run from RAM */
165 writel(0x910a8200, SDCTL0) /* Precharge cmd, CAS = 2 */
166 writel(0x0, 0x08200000) /* Issue Precharge all Command */
167 writel(0xa10a8200, SDCTL0) /* Autorefresh cmd, CAS = 2 */
170 ldr r1, =0x0 /* Issue AutoRefresh Command */
180 writel(0xb10a8300, SDCTL0)
181 writel(0x0, 0x08223000) /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */
182 writel(0x810a8200, SDCTL0) /* Set to Normal Mode CAS 2 */