add unified compile target
[avr_work.git] / common / spi_io_usi.c
bloba7c12cb6afc1c0991ea6de45a8d07d9255c8bd00
1 /*
2 ATtinyX61:
3 DI -> 0
4 DO -> 1
5 CLK-> 2
6 */
8 static inline void spi_isr_on (void) {USICR |= (1<<USIOIE);}
9 static inline void spi_isr_off(void) {USICR &= (uint8_t)~(1<<USIOIE);}
11 static void spi_io_init_hw(void) {
12 power_usi_enable();
14 // Clr the flags we interupt on + counter bits in same reg.
15 // (default is not raised)
16 //USISR = (1<<USIOIF);
18 // Clr datareg to avoid junk data being sent out. (defaults to 0)
19 //USIDR = 0;
21 #define B 0
22 #define A 1
24 #if ( SPI_PORT == B )
25 //#warning Using Port B (default)
26 //USIPP &= (uint8_t)~(1<<USIPOS);
27 #else
28 #error Using Port A
29 USIPP |= (1<<USIPOS);
30 #endif
32 #undef A
33 #undef B
35 DDR(SPI_PORT) |= (1<<SPI_MISO);
36 DDR(SPI_PORT) &= (uint8_t)~((1<<SPI_MOSI)|(1<<SPI_CLK));
37 PORT(SPI_PORT)&= (uint8_t)~( (1<<SPI_MOSI) | (1<<SPI_CLK) | (1<<SPI_MISO) );
39 // To resolve SPI_EDGE
40 #define NEGATIVE 1
41 #define POSITIVE 0
43 USICR = (0<<USISIE) | // Start IE(2w), CLK edge IE(3w)
44 (1<<USIOIE) | // Ovf interupt (to refil register)
45 (0<<USIWM1) | (1<<USIWM0) | // 01 = 3w, 00 = disable, 10&11 = 2w
46 (1<<USICS1) | (SPI_EDGE<<USICS0) | // 10 = positive edge, 11 = neg.
47 (0<<USICLK) | // 4bit timer : 0 = external, 1 = sw
48 (0<<USITC ); // Clock toggle
50 #undef NEGATIVE
51 #undef POSITIVE
54 ISR( SIG_USI_OVERFLOW ) {
55 USISR = (1<<USIOIF); // Clear interupt flag and counter.
57 //transmit (tx)
58 if (!q_empty(&tx)) {
59 USIDR = q_pop(&tx);
61 else USIDR = 0;
63 //recieve (rx)
64 uint8_t in = USIBR;
65 if (in != 0 && !q_full(&rx)) {
66 q_push(&rx,in);
67 if (in == '\n')
68 spi_io_rx_nl++;
71 /*// Alternate if we don't care about losing old data.
72 if (USIBR != 0) {
73 q_push_o(&rx,USIBR);