hw/prep_pci.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pci.h"
  27
  28 typedef uint32_t pci_addr_t;
  29 #include "pci_host.h"
  30
  31 typedef PCIHostState PREPPCIState;
  32
  33 static void pci_prep_addr_writel(void* opaque, uint32_t addr, uint32_t val)
  34 {
  35     PREPPCIState *s = opaque;
  36     s->config_reg = val;
  37 }
  38
  39 static uint32_t pci_prep_addr_readl(void* opaque, uint32_t addr)
  40 {
  41     PREPPCIState *s = opaque;
  42     return s->config_reg;
  43 }
  44
  45 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
  46 {
  47     int i;
  48
  49     for(i = 0; i < 11; i++) {
  50         if ((addr & (1 << (11 + i))) != 0)
  51             break;
  52     }
  53     return (addr & 0x7ff) |  (i << 11);
  54 }
  55
  56 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
  57 {
  58     PREPPCIState *s = opaque;
  59     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
  60 }
  61
  62 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
  63 {
  64     PREPPCIState *s = opaque;
  65 #ifdef TARGET_WORDS_BIGENDIAN
  66     val = bswap16(val);
  67 #endif
  68     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
  69 }
  70
  71 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
  72 {
  73     PREPPCIState *s = opaque;
  74 #ifdef TARGET_WORDS_BIGENDIAN
  75     val = bswap32(val);
  76 #endif
  77     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
  78 }
  79
  80 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
  81 {
  82     PREPPCIState *s = opaque;
  83     uint32_t val;
  84     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
  85     return val;
  86 }
  87
  88 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
  89 {
  90     PREPPCIState *s = opaque;
  91     uint32_t val;
  92     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
  93 #ifdef TARGET_WORDS_BIGENDIAN
  94     val = bswap16(val);
  95 #endif
  96     return val;
  97 }
  98
  99 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
 100 {
 101     PREPPCIState *s = opaque;
 102     uint32_t val;
 103     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
 104 #ifdef TARGET_WORDS_BIGENDIAN
 105     val = bswap32(val);
 106 #endif
 107     return val;
 108 }
 109
 110 static CPUWriteMemoryFunc * const PPC_PCIIO_write[] = {
 111     &PPC_PCIIO_writeb,
 112     &PPC_PCIIO_writew,
 113     &PPC_PCIIO_writel,
 114 };
 115
 116 static CPUReadMemoryFunc * const PPC_PCIIO_read[] = {
 117     &PPC_PCIIO_readb,
 118     &PPC_PCIIO_readw,
 119     &PPC_PCIIO_readl,
 120 };
 121
 122 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
 123 {
 124     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 125 }
 126
 127 static void prep_set_irq(void *opaque, int irq_num, int level)
 128 {
 129     qemu_irq *pic = opaque;
 130
 131     qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
 132 }
 133
 134 PCIBus *pci_prep_init(qemu_irq *pic)
 135 {
 136     PREPPCIState *s;
 137     PCIDevice *d;
 138     int PPC_io_memory;
 139
 140     s = qemu_mallocz(sizeof(PREPPCIState));
 141     s->bus = pci_register_bus(NULL, "pci",
 142                               prep_set_irq, prep_map_irq, pic, 0, 4);
 143
 144     register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);
 145     register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);
 146
 147     register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
 148     register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
 149     register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
 150     register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
 151     register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
 152     register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
 153
 154     PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
 155                                            PPC_PCIIO_write, s);
 156     cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
 157
 158     /* PCI host bridge */
 159     d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
 160                             sizeof(PCIDevice), 0, NULL, NULL);
 161     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
 162     pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
 163     d->config[0x08] = 0x00; // revision
 164     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 165     d->config[0x0C] = 0x08; // cache_line_size
 166     d->config[0x0D] = 0x10; // latency_timer
 167     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 168     d->config[0x34] = 0x00; // capabilities_pointer
 169
 170     return s->bus;
 171 }