hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32 #include "qemu-log.h"
  33
  34 #define BIOS_FILENAME "ppc405_rom.bin"
  35 #define BIOS_SIZE (2048 * 1024)
  36
  37 #define KERNEL_LOAD_ADDR 0x00000000
  38 #define INITRD_LOAD_ADDR 0x01800000
  39
  40 #define USE_FLASH_BIOS
  41
  42 #define DEBUG_BOARD_INIT
  43
  44 /*****************************************************************************/
  45 /* PPC405EP reference board (IBM) */
  46 /* Standalone board with:
  47  * - PowerPC 405EP CPU
  48  * - SDRAM (0x00000000)
  49  * - Flash (0xFFF80000)
  50  * - SRAM  (0xFFF00000)
  51  * - NVRAM (0xF0000000)
  52  * - FPGA  (0xF0300000)
  53  */
  54 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  55 struct ref405ep_fpga_t {
  56     uint8_t reg0;
  57     uint8_t reg1;
  58 };
  59
  60 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  61 {
  62     ref405ep_fpga_t *fpga;
  63     uint32_t ret;
  64
  65     fpga = opaque;
  66     switch (addr) {
  67     case 0x0:
  68         ret = fpga->reg0;
  69         break;
  70     case 0x1:
  71         ret = fpga->reg1;
  72         break;
  73     default:
  74         ret = 0;
  75         break;
  76     }
  77
  78     return ret;
  79 }
  80
  81 static void ref405ep_fpga_writeb (void *opaque,
  82                                   target_phys_addr_t addr, uint32_t value)
  83 {
  84     ref405ep_fpga_t *fpga;
  85
  86     fpga = opaque;
  87     switch (addr) {
  88     case 0x0:
  89         /* Read only */
  90         break;
  91     case 0x1:
  92         fpga->reg1 = value;
  93         break;
  94     default:
  95         break;
  96     }
  97 }
  98
  99 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 100 {
 101     uint32_t ret;
 102
 103     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 104     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 105
 106     return ret;
 107 }
 108
 109 static void ref405ep_fpga_writew (void *opaque,
 110                                   target_phys_addr_t addr, uint32_t value)
 111 {
 112     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 113     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 114 }
 115
 116 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 117 {
 118     uint32_t ret;
 119
 120     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 121     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 122     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 123     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 124
 125     return ret;
 126 }
 127
 128 static void ref405ep_fpga_writel (void *opaque,
 129                                   target_phys_addr_t addr, uint32_t value)
 130 {
 131     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 132     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 133     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 134     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 135 }
 136
 137 static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
 138     &ref405ep_fpga_readb,
 139     &ref405ep_fpga_readw,
 140     &ref405ep_fpga_readl,
 141 };
 142
 143 static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
 144     &ref405ep_fpga_writeb,
 145     &ref405ep_fpga_writew,
 146     &ref405ep_fpga_writel,
 147 };
 148
 149 static void ref405ep_fpga_reset (void *opaque)
 150 {
 151     ref405ep_fpga_t *fpga;
 152
 153     fpga = opaque;
 154     fpga->reg0 = 0x00;
 155     fpga->reg1 = 0x0F;
 156 }
 157
 158 static void ref405ep_fpga_init (uint32_t base)
 159 {
 160     ref405ep_fpga_t *fpga;
 161     int fpga_memory;
 162
 163     fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
 164     fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
 165                                          ref405ep_fpga_write, fpga);
 166     cpu_register_physical_memory(base, 0x00000100, fpga_memory);
 167     ref405ep_fpga_reset(fpga);
 168     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 169 }
 170
 171 static void ref405ep_init (ram_addr_t ram_size,
 172                            const char *boot_device,
 173                            const char *kernel_filename,
 174                            const char *kernel_cmdline,
 175                            const char *initrd_filename,
 176                            const char *cpu_model)
 177 {
 178     char *filename;
 179     ppc4xx_bd_info_t bd;
 180     CPUPPCState *env;
 181     qemu_irq *pic;
 182     ram_addr_t sram_offset, bios_offset, bdloc;
 183     target_phys_addr_t ram_bases[2], ram_sizes[2];
 184     target_ulong sram_size, bios_size;
 185     //int phy_addr = 0;
 186     //static int phy_addr = 1;
 187     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 188     int linux_boot;
 189     int fl_idx, fl_sectors, len;
 190     int ppc_boot_device = boot_device[0];
 191     DriveInfo *dinfo;
 192
 193     /* XXX: fix this */
 194     ram_bases[0] = qemu_ram_alloc(0x08000000);
 195     ram_sizes[0] = 0x08000000;
 196     ram_bases[1] = 0x00000000;
 197     ram_sizes[1] = 0x00000000;
 198     ram_size = 128 * 1024 * 1024;
 199 #ifdef DEBUG_BOARD_INIT
 200     printf("%s: register cpu\n", __func__);
 201 #endif
 202     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 203                         kernel_filename == NULL ? 0 : 1);
 204     /* allocate SRAM */
 205     sram_size = 512 * 1024;
 206     sram_offset = qemu_ram_alloc(sram_size);
 207 #ifdef DEBUG_BOARD_INIT
 208     printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
 209 #endif
 210     cpu_register_physical_memory(0xFFF00000, sram_size,
 211                                  sram_offset | IO_MEM_RAM);
 212     /* allocate and load BIOS */
 213 #ifdef DEBUG_BOARD_INIT
 214     printf("%s: register BIOS\n", __func__);
 215 #endif
 216     fl_idx = 0;
 217 #ifdef USE_FLASH_BIOS
 218     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 219     if (dinfo) {
 220         bios_size = bdrv_getlength(dinfo->bdrv);
 221         bios_offset = qemu_ram_alloc(bios_size);
 222         fl_sectors = (bios_size + 65535) >> 16;
 223 #ifdef DEBUG_BOARD_INIT
 224         printf("Register parallel flash %d size " TARGET_FMT_lx
 225                " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
 226                fl_idx, bios_size, bios_offset, -bios_size,
 227                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 228 #endif
 229         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 230                               dinfo->bdrv, 65536, fl_sectors, 1,
 231                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 232         fl_idx++;
 233     } else
 234 #endif
 235     {
 236 #ifdef DEBUG_BOARD_INIT
 237         printf("Load BIOS from file\n");
 238 #endif
 239         bios_offset = qemu_ram_alloc(BIOS_SIZE);
 240         if (bios_name == NULL)
 241             bios_name = BIOS_FILENAME;
 242         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 243         if (filename) {
 244             bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
 245             qemu_free(filename);
 246         } else {
 247             bios_size = -1;
 248         }
 249         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 250             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 251                     bios_name);
 252             exit(1);
 253         }
 254         bios_size = (bios_size + 0xfff) & ~0xfff;
 255         cpu_register_physical_memory((uint32_t)(-bios_size),
 256                                      bios_size, bios_offset | IO_MEM_ROM);
 257     }
 258     /* Register FPGA */
 259 #ifdef DEBUG_BOARD_INIT
 260     printf("%s: register FPGA\n", __func__);
 261 #endif
 262     ref405ep_fpga_init(0xF0300000);
 263     /* Register NVRAM */
 264 #ifdef DEBUG_BOARD_INIT
 265     printf("%s: register NVRAM\n", __func__);
 266 #endif
 267     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 268     /* Load kernel */
 269     linux_boot = (kernel_filename != NULL);
 270     if (linux_boot) {
 271 #ifdef DEBUG_BOARD_INIT
 272         printf("%s: load kernel\n", __func__);
 273 #endif
 274         memset(&bd, 0, sizeof(bd));
 275         bd.bi_memstart = 0x00000000;
 276         bd.bi_memsize = ram_size;
 277         bd.bi_flashstart = -bios_size;
 278         bd.bi_flashsize = -bios_size;
 279         bd.bi_flashoffset = 0;
 280         bd.bi_sramstart = 0xFFF00000;
 281         bd.bi_sramsize = sram_size;
 282         bd.bi_bootflags = 0;
 283         bd.bi_intfreq = 133333333;
 284         bd.bi_busfreq = 33333333;
 285         bd.bi_baudrate = 115200;
 286         bd.bi_s_version[0] = 'Q';
 287         bd.bi_s_version[1] = 'M';
 288         bd.bi_s_version[2] = 'U';
 289         bd.bi_s_version[3] = '\0';
 290         bd.bi_r_version[0] = 'Q';
 291         bd.bi_r_version[1] = 'E';
 292         bd.bi_r_version[2] = 'M';
 293         bd.bi_r_version[3] = 'U';
 294         bd.bi_r_version[4] = '\0';
 295         bd.bi_procfreq = 133333333;
 296         bd.bi_plb_busfreq = 33333333;
 297         bd.bi_pci_busfreq = 33333333;
 298         bd.bi_opbfreq = 33333333;
 299         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 300         env->gpr[3] = bdloc;
 301         kernel_base = KERNEL_LOAD_ADDR;
 302         /* now we can load the kernel */
 303         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 304                                           ram_size - kernel_base);
 305         if (kernel_size < 0) {
 306             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 307                     kernel_filename);
 308             exit(1);
 309         }
 310         printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx,
 311                kernel_size, kernel_base);
 312         /* load initrd */
 313         if (initrd_filename) {
 314             initrd_base = INITRD_LOAD_ADDR;
 315             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 316                                               ram_size - initrd_base);
 317             if (initrd_size < 0) {
 318                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 319                         initrd_filename);
 320                 exit(1);
 321             }
 322         } else {
 323             initrd_base = 0;
 324             initrd_size = 0;
 325         }
 326         env->gpr[4] = initrd_base;
 327         env->gpr[5] = initrd_size;
 328         ppc_boot_device = 'm';
 329         if (kernel_cmdline != NULL) {
 330             len = strlen(kernel_cmdline);
 331             bdloc -= ((len + 255) & ~255);
 332             cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
 333             env->gpr[6] = bdloc;
 334             env->gpr[7] = bdloc + len;
 335         } else {
 336             env->gpr[6] = 0;
 337             env->gpr[7] = 0;
 338         }
 339         env->nip = KERNEL_LOAD_ADDR;
 340     } else {
 341         kernel_base = 0;
 342         kernel_size = 0;
 343         initrd_base = 0;
 344         initrd_size = 0;
 345         bdloc = 0;
 346     }
 347 #ifdef DEBUG_BOARD_INIT
 348     printf("%s: Done\n", __func__);
 349 #endif
 350     printf("bdloc %016lx\n", (unsigned long)bdloc);
 351 }
 352
 353 static QEMUMachine ref405ep_machine = {
 354     .name = "ref405ep",
 355     .desc = "ref405ep",
 356     .init = ref405ep_init,
 357 };
 358
 359 /*****************************************************************************/
 360 /* AMCC Taihu evaluation board */
 361 /* - PowerPC 405EP processor
 362  * - SDRAM               128 MB at 0x00000000
 363  * - Boot flash          2 MB   at 0xFFE00000
 364  * - Application flash   32 MB  at 0xFC000000
 365  * - 2 serial ports
 366  * - 2 ethernet PHY
 367  * - 1 USB 1.1 device    0x50000000
 368  * - 1 LCD display       0x50100000
 369  * - 1 CPLD              0x50100000
 370  * - 1 I2C EEPROM
 371  * - 1 I2C thermal sensor
 372  * - a set of LEDs
 373  * - bit-bang SPI port using GPIOs
 374  * - 1 EBC interface connector 0 0x50200000
 375  * - 1 cardbus controller + expansion slot.
 376  * - 1 PCI expansion slot.
 377  */
 378 typedef struct taihu_cpld_t taihu_cpld_t;
 379 struct taihu_cpld_t {
 380     uint8_t reg0;
 381     uint8_t reg1;
 382 };
 383
 384 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 385 {
 386     taihu_cpld_t *cpld;
 387     uint32_t ret;
 388
 389     cpld = opaque;
 390     switch (addr) {
 391     case 0x0:
 392         ret = cpld->reg0;
 393         break;
 394     case 0x1:
 395         ret = cpld->reg1;
 396         break;
 397     default:
 398         ret = 0;
 399         break;
 400     }
 401
 402     return ret;
 403 }
 404
 405 static void taihu_cpld_writeb (void *opaque,
 406                                target_phys_addr_t addr, uint32_t value)
 407 {
 408     taihu_cpld_t *cpld;
 409
 410     cpld = opaque;
 411     switch (addr) {
 412     case 0x0:
 413         /* Read only */
 414         break;
 415     case 0x1:
 416         cpld->reg1 = value;
 417         break;
 418     default:
 419         break;
 420     }
 421 }
 422
 423 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 424 {
 425     uint32_t ret;
 426
 427     ret = taihu_cpld_readb(opaque, addr) << 8;
 428     ret |= taihu_cpld_readb(opaque, addr + 1);
 429
 430     return ret;
 431 }
 432
 433 static void taihu_cpld_writew (void *opaque,
 434                                target_phys_addr_t addr, uint32_t value)
 435 {
 436     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 437     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 438 }
 439
 440 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 441 {
 442     uint32_t ret;
 443
 444     ret = taihu_cpld_readb(opaque, addr) << 24;
 445     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 446     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 447     ret |= taihu_cpld_readb(opaque, addr + 3);
 448
 449     return ret;
 450 }
 451
 452 static void taihu_cpld_writel (void *opaque,
 453                                target_phys_addr_t addr, uint32_t value)
 454 {
 455     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 456     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 457     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 458     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 459 }
 460
 461 static CPUReadMemoryFunc * const taihu_cpld_read[] = {
 462     &taihu_cpld_readb,
 463     &taihu_cpld_readw,
 464     &taihu_cpld_readl,
 465 };
 466
 467 static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
 468     &taihu_cpld_writeb,
 469     &taihu_cpld_writew,
 470     &taihu_cpld_writel,
 471 };
 472
 473 static void taihu_cpld_reset (void *opaque)
 474 {
 475     taihu_cpld_t *cpld;
 476
 477     cpld = opaque;
 478     cpld->reg0 = 0x01;
 479     cpld->reg1 = 0x80;
 480 }
 481
 482 static void taihu_cpld_init (uint32_t base)
 483 {
 484     taihu_cpld_t *cpld;
 485     int cpld_memory;
 486
 487     cpld = qemu_mallocz(sizeof(taihu_cpld_t));
 488     cpld_memory = cpu_register_io_memory(taihu_cpld_read,
 489                                          taihu_cpld_write, cpld);
 490     cpu_register_physical_memory(base, 0x00000100, cpld_memory);
 491     taihu_cpld_reset(cpld);
 492     qemu_register_reset(&taihu_cpld_reset, cpld);
 493 }
 494
 495 static void taihu_405ep_init(ram_addr_t ram_size,
 496                              const char *boot_device,
 497                              const char *kernel_filename,
 498                              const char *kernel_cmdline,
 499                              const char *initrd_filename,
 500                              const char *cpu_model)
 501 {
 502     char *filename;
 503     CPUPPCState *env;
 504     qemu_irq *pic;
 505     ram_addr_t bios_offset;
 506     target_phys_addr_t ram_bases[2], ram_sizes[2];
 507     target_ulong bios_size;
 508     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 509     int linux_boot;
 510     int fl_idx, fl_sectors;
 511     int ppc_boot_device = boot_device[0];
 512     DriveInfo *dinfo;
 513
 514     /* RAM is soldered to the board so the size cannot be changed */
 515     ram_bases[0] = qemu_ram_alloc(0x04000000);
 516     ram_sizes[0] = 0x04000000;
 517     ram_bases[1] = qemu_ram_alloc(0x04000000);
 518     ram_sizes[1] = 0x04000000;
 519     ram_size = 0x08000000;
 520 #ifdef DEBUG_BOARD_INIT
 521     printf("%s: register cpu\n", __func__);
 522 #endif
 523     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 524                         kernel_filename == NULL ? 0 : 1);
 525     /* allocate and load BIOS */
 526 #ifdef DEBUG_BOARD_INIT
 527     printf("%s: register BIOS\n", __func__);
 528 #endif
 529     fl_idx = 0;
 530 #if defined(USE_FLASH_BIOS)
 531     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 532     if (dinfo) {
 533         bios_size = bdrv_getlength(dinfo->bdrv);
 534         /* XXX: should check that size is 2MB */
 535         //        bios_size = 2 * 1024 * 1024;
 536         fl_sectors = (bios_size + 65535) >> 16;
 537         bios_offset = qemu_ram_alloc(bios_size);
 538 #ifdef DEBUG_BOARD_INIT
 539         printf("Register parallel flash %d size " TARGET_FMT_lx
 540                " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
 541                fl_idx, bios_size, bios_offset, -bios_size,
 542                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 543 #endif
 544         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 545                               dinfo->bdrv, 65536, fl_sectors, 1,
 546                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 547         fl_idx++;
 548     } else
 549 #endif
 550     {
 551 #ifdef DEBUG_BOARD_INIT
 552         printf("Load BIOS from file\n");
 553 #endif
 554         if (bios_name == NULL)
 555             bios_name = BIOS_FILENAME;
 556         bios_offset = qemu_ram_alloc(BIOS_SIZE);
 557         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 558         if (filename) {
 559             bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
 560         } else {
 561             bios_size = -1;
 562         }
 563         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 564             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 565                     bios_name);
 566             exit(1);
 567         }
 568         bios_size = (bios_size + 0xfff) & ~0xfff;
 569         cpu_register_physical_memory((uint32_t)(-bios_size),
 570                                      bios_size, bios_offset | IO_MEM_ROM);
 571     }
 572     /* Register Linux flash */
 573     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 574     if (dinfo) {
 575         bios_size = bdrv_getlength(dinfo->bdrv);
 576         /* XXX: should check that size is 32MB */
 577         bios_size = 32 * 1024 * 1024;
 578         fl_sectors = (bios_size + 65535) >> 16;
 579 #ifdef DEBUG_BOARD_INIT
 580         printf("Register parallel flash %d size " TARGET_FMT_lx
 581                " at offset %08lx  addr " TARGET_FMT_lx " '%s'\n",
 582                fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
 583                bdrv_get_device_name(dinfo->bdrv));
 584 #endif
 585         bios_offset = qemu_ram_alloc(bios_size);
 586         pflash_cfi02_register(0xfc000000, bios_offset,
 587                               dinfo->bdrv, 65536, fl_sectors, 1,
 588                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 589         fl_idx++;
 590     }
 591     /* Register CLPD & LCD display */
 592 #ifdef DEBUG_BOARD_INIT
 593     printf("%s: register CPLD\n", __func__);
 594 #endif
 595     taihu_cpld_init(0x50100000);
 596     /* Load kernel */
 597     linux_boot = (kernel_filename != NULL);
 598     if (linux_boot) {
 599 #ifdef DEBUG_BOARD_INIT
 600         printf("%s: load kernel\n", __func__);
 601 #endif
 602         kernel_base = KERNEL_LOAD_ADDR;
 603         /* now we can load the kernel */
 604         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 605                                           ram_size - kernel_base);
 606         if (kernel_size < 0) {
 607             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 608                     kernel_filename);
 609             exit(1);
 610         }
 611         /* load initrd */
 612         if (initrd_filename) {
 613             initrd_base = INITRD_LOAD_ADDR;
 614             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 615                                               ram_size - initrd_base);
 616             if (initrd_size < 0) {
 617                 fprintf(stderr,
 618                         "qemu: could not load initial ram disk '%s'\n",
 619                         initrd_filename);
 620                 exit(1);
 621             }
 622         } else {
 623             initrd_base = 0;
 624             initrd_size = 0;
 625         }
 626         ppc_boot_device = 'm';
 627     } else {
 628         kernel_base = 0;
 629         kernel_size = 0;
 630         initrd_base = 0;
 631         initrd_size = 0;
 632     }
 633 #ifdef DEBUG_BOARD_INIT
 634     printf("%s: Done\n", __func__);
 635 #endif
 636 }
 637
 638 static QEMUMachine taihu_machine = {
 639     .name = "taihu",
 640     .desc = "taihu",
 641     .init = taihu_405ep_init,
 642 };
 643
 644 static void ppc405_machine_init(void)
 645 {
 646     qemu_register_machine(&ref405ep_machine);
 647     qemu_register_machine(&taihu_machine);
 648 }
 649
 650 machine_init(ppc405_machine_init);