hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31 #ifdef DEBUG_PCI
  32 # define PCI_DPRINTF(format, ...)       printf(format, __VA_ARGS__)
  33 #else
  34 # define PCI_DPRINTF(format, ...)       do { } while (0)
  35 #endif
  36
  37 struct PCIBus {
  38     BusState qbus;
  39     int bus_num;
  40     int devfn_min;
  41     pci_set_irq_fn set_irq;
  42     pci_map_irq_fn map_irq;
  43     uint32_t config_reg; /* XXX: suppress */
  44     void *irq_opaque;
  45     PCIDevice *devices[256];
  46     PCIDevice *parent_dev;
  47     PCIBus *next;
  48     /* The bus IRQ state is the logical OR of the connected devices.
  49        Keep a count of the number of devices with raised IRQs.  */
  50     int nirq;
  51     int *irq_count;
  52 };
  53
  54 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  55
  56 static struct BusInfo pci_bus_info = {
  57     .name       = "PCI",
  58     .size       = sizeof(PCIBus),
  59     .print_dev  = pcibus_dev_print,
  60     .props      = (Property[]) {
  61         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  62         DEFINE_PROP_END_OF_LIST()
  63     }
  64 };
  65
  66 static void pci_update_mappings(PCIDevice *d);
  67 static void pci_set_irq(void *opaque, int irq_num, int level);
  68
  69 target_phys_addr_t pci_mem_base;
  70 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  71 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  72 static PCIBus *first_bus;
  73
  74 static const VMStateDescription vmstate_pcibus = {
  75     .name = "PCIBUS",
  76     .version_id = 1,
  77     .minimum_version_id = 1,
  78     .minimum_version_id_old = 1,
  79     .fields      = (VMStateField []) {
  80         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  81         VMSTATE_INT32_VARRAY(irq_count, PCIBus, nirq),
  82         VMSTATE_END_OF_LIST()
  83     }
  84 };
  85
  86 static void pci_bus_reset(void *opaque)
  87 {
  88     PCIBus *bus = opaque;
  89     int i;
  90
  91     for (i = 0; i < bus->nirq; i++) {
  92         bus->irq_count[i] = 0;
  93     }
  94     for (i = 0; i < 256; i++) {
  95         if (bus->devices[i])
  96             memset(bus->devices[i]->irq_state, 0,
  97                    sizeof(bus->devices[i]->irq_state));
  98     }
  99 }
 100
 101 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 102                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 103                          void *irq_opaque, int devfn_min, int nirq)
 104 {
 105     PCIBus *bus;
 106     static int nbus = 0;
 107
 108     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name));
 109     bus->set_irq = set_irq;
 110     bus->map_irq = map_irq;
 111     bus->irq_opaque = irq_opaque;
 112     bus->devfn_min = devfn_min;
 113     bus->nirq = nirq;
 114     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 115     bus->next = first_bus;
 116     first_bus = bus;
 117     vmstate_register(nbus++, &vmstate_pcibus, bus);
 118     qemu_register_reset(pci_bus_reset, bus);
 119     return bus;
 120 }
 121
 122 static PCIBus *pci_register_secondary_bus(PCIDevice *dev,
 123                                           pci_map_irq_fn map_irq,
 124                                           const char *name)
 125 {
 126     PCIBus *bus;
 127
 128     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, &dev->qdev, name));
 129     bus->map_irq = map_irq;
 130     bus->parent_dev = dev;
 131     bus->next = dev->bus->next;
 132     dev->bus->next = bus;
 133     return bus;
 134 }
 135
 136 int pci_bus_num(PCIBus *s)
 137 {
 138     return s->bus_num;
 139 }
 140
 141 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 142 {
 143     PCIDevice *s = container_of(pv, PCIDevice, config);
 144     uint8_t config[size];
 145     int i;
 146
 147     qemu_get_buffer(f, config, size);
 148     for (i = 0; i < size; ++i)
 149         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 150             return -EINVAL;
 151     memcpy(s->config, config, size);
 152
 153     pci_update_mappings(s);
 154
 155     return 0;
 156 }
 157
 158 /* just put buffer */
 159 static void put_pci_config_device(QEMUFile *f, const void *pv, size_t size)
 160 {
 161     const uint8_t *v = pv;
 162     qemu_put_buffer(f, v, size);
 163 }
 164
 165 static VMStateInfo vmstate_info_pci_config = {
 166     .name = "pci config",
 167     .get  = get_pci_config_device,
 168     .put  = put_pci_config_device,
 169 };
 170
 171 const VMStateDescription vmstate_pci_device = {
 172     .name = "PCIDevice",
 173     .version_id = 2,
 174     .minimum_version_id = 1,
 175     .minimum_version_id_old = 1,
 176     .fields      = (VMStateField []) {
 177         VMSTATE_INT32_LE(version_id, PCIDevice),
 178         VMSTATE_SINGLE(config, PCIDevice, 0, vmstate_info_pci_config,
 179                        typeof_field(PCIDevice,config)),
 180         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, 4, 2),
 181         VMSTATE_END_OF_LIST()
 182     }
 183 };
 184
 185 void pci_device_save(PCIDevice *s, QEMUFile *f)
 186 {
 187     vmstate_save_state(f, &vmstate_pci_device, s);
 188 }
 189
 190 int pci_device_load(PCIDevice *s, QEMUFile *f)
 191 {
 192     return vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
 193 }
 194
 195 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 196 {
 197     uint16_t *id;
 198
 199     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 200     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 201     id[1] = cpu_to_le16(pci_default_sub_device_id);
 202     return 0;
 203 }
 204
 205 /*
 206  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 207  */
 208 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 209 {
 210     const char *p;
 211     char *e;
 212     unsigned long val;
 213     unsigned long dom = 0, bus = 0;
 214     unsigned slot = 0;
 215
 216     p = addr;
 217     val = strtoul(p, &e, 16);
 218     if (e == p)
 219         return -1;
 220     if (*e == ':') {
 221         bus = val;
 222         p = e + 1;
 223         val = strtoul(p, &e, 16);
 224         if (e == p)
 225             return -1;
 226         if (*e == ':') {
 227             dom = bus;
 228             bus = val;
 229             p = e + 1;
 230             val = strtoul(p, &e, 16);
 231             if (e == p)
 232                 return -1;
 233         }
 234     }
 235
 236     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 237         return -1;
 238
 239     slot = val;
 240
 241     if (*e)
 242         return -1;
 243
 244     /* Note: QEMU doesn't implement domains other than 0 */
 245     if (dom != 0 || pci_find_bus(bus) == NULL)
 246         return -1;
 247
 248     *domp = dom;
 249     *busp = bus;
 250     *slotp = slot;
 251     return 0;
 252 }
 253
 254 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 255                      unsigned *slotp)
 256 {
 257     /* strip legacy tag */
 258     if (!strncmp(addr, "pci_addr=", 9)) {
 259         addr += 9;
 260     }
 261     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 262         monitor_printf(mon, "Invalid pci address\n");
 263         return -1;
 264     }
 265     return 0;
 266 }
 267
 268 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 269 {
 270     int dom, bus;
 271     unsigned slot;
 272
 273     if (!devaddr) {
 274         *devfnp = -1;
 275         return pci_find_bus(0);
 276     }
 277
 278     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 279         return NULL;
 280     }
 281
 282     *devfnp = slot << 3;
 283     return pci_find_bus(bus);
 284 }
 285
 286 static void pci_init_cmask(PCIDevice *dev)
 287 {
 288     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 289     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 290     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 291     dev->cmask[PCI_REVISION_ID] = 0xff;
 292     dev->cmask[PCI_CLASS_PROG] = 0xff;
 293     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 294     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 295     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 296 }
 297
 298 static void pci_init_wmask(PCIDevice *dev)
 299 {
 300     int i;
 301     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 302     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 303     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 304                               | PCI_COMMAND_MASTER;
 305     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 306         dev->wmask[i] = 0xff;
 307 }
 308
 309 /* -1 for devfn means auto assign */
 310 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 311                                          const char *name, int devfn,
 312                                          PCIConfigReadFunc *config_read,
 313                                          PCIConfigWriteFunc *config_write)
 314 {
 315     if (devfn < 0) {
 316         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 317             if (!bus->devices[devfn])
 318                 goto found;
 319         }
 320         return NULL;
 321     found: ;
 322     } else if (bus->devices[devfn]) {
 323         return NULL;
 324     }
 325     pci_dev->bus = bus;
 326     pci_dev->devfn = devfn;
 327     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 328     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 329     pci_set_default_subsystem_id(pci_dev);
 330     pci_init_cmask(pci_dev);
 331     pci_init_wmask(pci_dev);
 332
 333     if (!config_read)
 334         config_read = pci_default_read_config;
 335     if (!config_write)
 336         config_write = pci_default_write_config;
 337     pci_dev->config_read = config_read;
 338     pci_dev->config_write = config_write;
 339     bus->devices[devfn] = pci_dev;
 340     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 341     pci_dev->version_id = 2; /* Current pci device vmstate version */
 342     return pci_dev;
 343 }
 344
 345 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 346                                int instance_size, int devfn,
 347                                PCIConfigReadFunc *config_read,
 348                                PCIConfigWriteFunc *config_write)
 349 {
 350     PCIDevice *pci_dev;
 351
 352     pci_dev = qemu_mallocz(instance_size);
 353     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 354                                      config_read, config_write);
 355     return pci_dev;
 356 }
 357 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 358 {
 359     return addr + pci_mem_base;
 360 }
 361
 362 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 363 {
 364     PCIIORegion *r;
 365     int i;
 366
 367     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 368         r = &pci_dev->io_regions[i];
 369         if (!r->size || r->addr == -1)
 370             continue;
 371         if (r->type == PCI_ADDRESS_SPACE_IO) {
 372             isa_unassign_ioport(r->addr, r->size);
 373         } else {
 374             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 375                                                      r->size,
 376                                                      IO_MEM_UNASSIGNED);
 377         }
 378     }
 379 }
 380
 381 int pci_unregister_device(PCIDevice *pci_dev)
 382 {
 383     int ret = 0;
 384
 385     if (pci_dev->unregister)
 386         ret = pci_dev->unregister(pci_dev);
 387     if (ret)
 388         return ret;
 389
 390     pci_unregister_io_regions(pci_dev);
 391
 392     qemu_free_irqs(pci_dev->irq);
 393     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 394     qdev_free(&pci_dev->qdev);
 395     return 0;
 396 }
 397
 398 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 399                             uint32_t size, int type,
 400                             PCIMapIORegionFunc *map_func)
 401 {
 402     PCIIORegion *r;
 403     uint32_t addr;
 404     uint32_t wmask;
 405
 406     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 407         return;
 408
 409     if (size & (size-1)) {
 410         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 411                     "type=0x%x, size=0x%x\n", type, size);
 412         exit(1);
 413     }
 414
 415     r = &pci_dev->io_regions[region_num];
 416     r->addr = -1;
 417     r->size = size;
 418     r->type = type;
 419     r->map_func = map_func;
 420
 421     wmask = ~(size - 1);
 422     if (region_num == PCI_ROM_SLOT) {
 423         addr = 0x30;
 424         /* ROM enable bit is writeable */
 425         wmask |= 1;
 426     } else {
 427         addr = 0x10 + region_num * 4;
 428     }
 429     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 430     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 431     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 432 }
 433
 434 static void pci_update_mappings(PCIDevice *d)
 435 {
 436     PCIIORegion *r;
 437     int cmd, i;
 438     uint32_t last_addr, new_addr, config_ofs;
 439
 440     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 441     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 442         r = &d->io_regions[i];
 443         if (i == PCI_ROM_SLOT) {
 444             config_ofs = 0x30;
 445         } else {
 446             config_ofs = 0x10 + i * 4;
 447         }
 448         if (r->size != 0) {
 449             if (r->type & PCI_ADDRESS_SPACE_IO) {
 450                 if (cmd & PCI_COMMAND_IO) {
 451                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 452                                                          config_ofs));
 453                     new_addr = new_addr & ~(r->size - 1);
 454                     last_addr = new_addr + r->size - 1;
 455                     /* NOTE: we have only 64K ioports on PC */
 456                     if (last_addr <= new_addr || new_addr == 0 ||
 457                         last_addr >= 0x10000) {
 458                         new_addr = -1;
 459                     }
 460                 } else {
 461                     new_addr = -1;
 462                 }
 463             } else {
 464                 if (cmd & PCI_COMMAND_MEMORY) {
 465                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 466                                                          config_ofs));
 467                     /* the ROM slot has a specific enable bit */
 468                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 469                         goto no_mem_map;
 470                     new_addr = new_addr & ~(r->size - 1);
 471                     last_addr = new_addr + r->size - 1;
 472                     /* NOTE: we do not support wrapping */
 473                     /* XXX: as we cannot support really dynamic
 474                        mappings, we handle specific values as invalid
 475                        mappings. */
 476                     if (last_addr <= new_addr || new_addr == 0 ||
 477                         last_addr == -1) {
 478                         new_addr = -1;
 479                     }
 480                 } else {
 481                 no_mem_map:
 482                     new_addr = -1;
 483                 }
 484             }
 485             /* now do the real mapping */
 486             if (new_addr != r->addr) {
 487                 if (r->addr != -1) {
 488                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 489                         int class;
 490                         /* NOTE: specific hack for IDE in PC case:
 491                            only one byte must be mapped. */
 492                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 493                         if (class == 0x0101 && r->size == 4) {
 494                             isa_unassign_ioport(r->addr + 2, 1);
 495                         } else {
 496                             isa_unassign_ioport(r->addr, r->size);
 497                         }
 498                     } else {
 499                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 500                                                      r->size,
 501                                                      IO_MEM_UNASSIGNED);
 502                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 503                     }
 504                 }
 505                 r->addr = new_addr;
 506                 if (r->addr != -1) {
 507                     r->map_func(d, i, r->addr, r->size, r->type);
 508                 }
 509             }
 510         }
 511     }
 512 }
 513
 514 uint32_t pci_default_read_config(PCIDevice *d,
 515                                  uint32_t address, int len)
 516 {
 517     uint32_t val;
 518
 519     switch(len) {
 520     default:
 521     case 4:
 522         if (address <= 0xfc) {
 523             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 524             break;
 525         }
 526         /* fall through */
 527     case 2:
 528         if (address <= 0xfe) {
 529             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 530             break;
 531         }
 532         /* fall through */
 533     case 1:
 534         val = d->config[address];
 535         break;
 536     }
 537     return val;
 538 }
 539
 540 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 541 {
 542     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 543     int i;
 544
 545     /* not efficient, but simple */
 546     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 547     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 548         uint8_t wmask = d->wmask[addr];
 549         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 550     }
 551     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 552         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 553             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 554         pci_update_mappings(d);
 555 }
 556
 557 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 558 {
 559     PCIBus *s = opaque;
 560     PCIDevice *pci_dev;
 561     int config_addr, bus_num;
 562
 563 #if 0
 564     PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
 565                 addr, val, len);
 566 #endif
 567     bus_num = (addr >> 16) & 0xff;
 568     while (s && s->bus_num != bus_num)
 569         s = s->next;
 570     if (!s)
 571         return;
 572     pci_dev = s->devices[(addr >> 8) & 0xff];
 573     if (!pci_dev)
 574         return;
 575     config_addr = addr & 0xff;
 576     PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 577                 pci_dev->name, config_addr, val, len);
 578     pci_dev->config_write(pci_dev, config_addr, val, len);
 579 }
 580
 581 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 582 {
 583     PCIBus *s = opaque;
 584     PCIDevice *pci_dev;
 585     int config_addr, bus_num;
 586     uint32_t val;
 587
 588     bus_num = (addr >> 16) & 0xff;
 589     while (s && s->bus_num != bus_num)
 590         s= s->next;
 591     if (!s)
 592         goto fail;
 593     pci_dev = s->devices[(addr >> 8) & 0xff];
 594     if (!pci_dev) {
 595     fail:
 596         switch(len) {
 597         case 1:
 598             val = 0xff;
 599             break;
 600         case 2:
 601             val = 0xffff;
 602             break;
 603         default:
 604         case 4:
 605             val = 0xffffffff;
 606             break;
 607         }
 608         goto the_end;
 609     }
 610     config_addr = addr & 0xff;
 611     val = pci_dev->config_read(pci_dev, config_addr, len);
 612     PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 613                 pci_dev->name, config_addr, val, len);
 614  the_end:
 615 #if 0
 616     PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
 617                 addr, val, len);
 618 #endif
 619     return val;
 620 }
 621
 622 /***********************************************************/
 623 /* generic PCI irq support */
 624
 625 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 626 static void pci_set_irq(void *opaque, int irq_num, int level)
 627 {
 628     PCIDevice *pci_dev = opaque;
 629     PCIBus *bus;
 630     int change;
 631
 632     change = level - pci_dev->irq_state[irq_num];
 633     if (!change)
 634         return;
 635
 636     pci_dev->irq_state[irq_num] = level;
 637     for (;;) {
 638         bus = pci_dev->bus;
 639         irq_num = bus->map_irq(pci_dev, irq_num);
 640         if (bus->set_irq)
 641             break;
 642         pci_dev = bus->parent_dev;
 643     }
 644     bus->irq_count[irq_num] += change;
 645     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 646 }
 647
 648 /***********************************************************/
 649 /* monitor info on PCI */
 650
 651 typedef struct {
 652     uint16_t class;
 653     const char *desc;
 654 } pci_class_desc;
 655
 656 static const pci_class_desc pci_class_descriptions[] =
 657 {
 658     { 0x0100, "SCSI controller"},
 659     { 0x0101, "IDE controller"},
 660     { 0x0102, "Floppy controller"},
 661     { 0x0103, "IPI controller"},
 662     { 0x0104, "RAID controller"},
 663     { 0x0106, "SATA controller"},
 664     { 0x0107, "SAS controller"},
 665     { 0x0180, "Storage controller"},
 666     { 0x0200, "Ethernet controller"},
 667     { 0x0201, "Token Ring controller"},
 668     { 0x0202, "FDDI controller"},
 669     { 0x0203, "ATM controller"},
 670     { 0x0280, "Network controller"},
 671     { 0x0300, "VGA controller"},
 672     { 0x0301, "XGA controller"},
 673     { 0x0302, "3D controller"},
 674     { 0x0380, "Display controller"},
 675     { 0x0400, "Video controller"},
 676     { 0x0401, "Audio controller"},
 677     { 0x0402, "Phone"},
 678     { 0x0480, "Multimedia controller"},
 679     { 0x0500, "RAM controller"},
 680     { 0x0501, "Flash controller"},
 681     { 0x0580, "Memory controller"},
 682     { 0x0600, "Host bridge"},
 683     { 0x0601, "ISA bridge"},
 684     { 0x0602, "EISA bridge"},
 685     { 0x0603, "MC bridge"},
 686     { 0x0604, "PCI bridge"},
 687     { 0x0605, "PCMCIA bridge"},
 688     { 0x0606, "NUBUS bridge"},
 689     { 0x0607, "CARDBUS bridge"},
 690     { 0x0608, "RACEWAY bridge"},
 691     { 0x0680, "Bridge"},
 692     { 0x0c03, "USB controller"},
 693     { 0, NULL}
 694 };
 695
 696 static void pci_info_device(PCIDevice *d)
 697 {
 698     Monitor *mon = cur_mon;
 699     int i, class;
 700     PCIIORegion *r;
 701     const pci_class_desc *desc;
 702
 703     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 704                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 705     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 706     monitor_printf(mon, "    ");
 707     desc = pci_class_descriptions;
 708     while (desc->desc && class != desc->class)
 709         desc++;
 710     if (desc->desc) {
 711         monitor_printf(mon, "%s", desc->desc);
 712     } else {
 713         monitor_printf(mon, "Class %04x", class);
 714     }
 715     monitor_printf(mon, ": PCI device %04x:%04x\n",
 716            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 717            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 718
 719     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 720         monitor_printf(mon, "      IRQ %d.\n",
 721                        d->config[PCI_INTERRUPT_LINE]);
 722     }
 723     if (class == 0x0604) {
 724         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 725     }
 726     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 727         r = &d->io_regions[i];
 728         if (r->size != 0) {
 729             monitor_printf(mon, "      BAR%d: ", i);
 730             if (r->type & PCI_ADDRESS_SPACE_IO) {
 731                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 732                                r->addr, r->addr + r->size - 1);
 733             } else {
 734                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 735                                r->addr, r->addr + r->size - 1);
 736             }
 737         }
 738     }
 739     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
 740     if (class == 0x0604 && d->config[0x19] != 0) {
 741         pci_for_each_device(d->config[0x19], pci_info_device);
 742     }
 743 }
 744
 745 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 746 {
 747     PCIBus *bus = first_bus;
 748     PCIDevice *d;
 749     int devfn;
 750
 751     while (bus && bus->bus_num != bus_num)
 752         bus = bus->next;
 753     if (bus) {
 754         for(devfn = 0; devfn < 256; devfn++) {
 755             d = bus->devices[devfn];
 756             if (d)
 757                 fn(d);
 758         }
 759     }
 760 }
 761
 762 void pci_info(Monitor *mon)
 763 {
 764     pci_for_each_device(0, pci_info_device);
 765 }
 766
 767 PCIDevice *pci_create(const char *name, const char *devaddr)
 768 {
 769     PCIBus *bus;
 770     int devfn;
 771     DeviceState *dev;
 772
 773     bus = pci_get_bus_devfn(&devfn, devaddr);
 774     if (!bus) {
 775         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 776                 devaddr, name);
 777         exit(1);
 778     }
 779
 780     dev = qdev_create(&bus->qbus, name);
 781     qdev_prop_set_uint32(dev, "addr", devfn);
 782     return (PCIDevice *)dev;
 783 }
 784
 785 static const char * const pci_nic_models[] = {
 786     "ne2k_pci",
 787     "i82551",
 788     "i82557b",
 789     "i82559er",
 790     "rtl8139",
 791     "e1000",
 792     "pcnet",
 793     "virtio",
 794     NULL
 795 };
 796
 797 static const char * const pci_nic_names[] = {
 798     "ne2k_pci",
 799     "i82551",
 800     "i82557b",
 801     "i82559er",
 802     "rtl8139",
 803     "e1000",
 804     "pcnet",
 805     "virtio-net-pci",
 806     NULL
 807 };
 808
 809 /* Initialize a PCI NIC.  */
 810 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 811                         const char *default_devaddr)
 812 {
 813     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 814     PCIDevice *pci_dev;
 815     DeviceState *dev;
 816     int i;
 817
 818     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 819
 820     for (i = 0; pci_nic_models[i]; i++) {
 821         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 822             pci_dev = pci_create(pci_nic_names[i], devaddr);
 823             dev = &pci_dev->qdev;
 824             if (nd->id)
 825                 dev->id = qemu_strdup(nd->id);
 826             dev->nd = nd;
 827             qdev_init(dev);
 828             nd->private = dev;
 829             return pci_dev;
 830         }
 831     }
 832
 833     return NULL;
 834 }
 835
 836 typedef struct {
 837     PCIDevice dev;
 838     PCIBus *bus;
 839 } PCIBridge;
 840
 841 static void pci_bridge_write_config(PCIDevice *d,
 842                              uint32_t address, uint32_t val, int len)
 843 {
 844     PCIBridge *s = (PCIBridge *)d;
 845
 846     pci_default_write_config(d, address, val, len);
 847     s->bus->bus_num = d->config[PCI_SECONDARY_BUS];
 848 }
 849
 850 PCIBus *pci_find_bus(int bus_num)
 851 {
 852     PCIBus *bus = first_bus;
 853
 854     while (bus && bus->bus_num != bus_num)
 855         bus = bus->next;
 856
 857     return bus;
 858 }
 859
 860 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 861 {
 862     PCIBus *bus = pci_find_bus(bus_num);
 863
 864     if (!bus)
 865         return NULL;
 866
 867     return bus->devices[PCI_DEVFN(slot, function)];
 868 }
 869
 870 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 871                         pci_map_irq_fn map_irq, const char *name)
 872 {
 873     PCIBridge *s;
 874     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 875                                          devfn, NULL, pci_bridge_write_config);
 876
 877     pci_config_set_vendor_id(s->dev.config, vid);
 878     pci_config_set_device_id(s->dev.config, did);
 879
 880     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 881     s->dev.config[0x05] = 0x00;
 882     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 883     s->dev.config[0x07] = 0x00; // status = fast devsel
 884     s->dev.config[0x08] = 0x00; // revision
 885     s->dev.config[0x09] = 0x00; // programming i/f
 886     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 887     s->dev.config[0x0D] = 0x10; // latency_timer
 888     s->dev.config[PCI_HEADER_TYPE] =
 889         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 890     s->dev.config[0x1E] = 0xa0; // secondary status
 891
 892     s->bus = pci_register_secondary_bus(&s->dev, map_irq, name);
 893     return s->bus;
 894 }
 895
 896 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 897 {
 898     PCIDevice *pci_dev = (PCIDevice *)qdev;
 899     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 900     PCIBus *bus;
 901     int devfn;
 902
 903     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 904     devfn = pci_dev->devfn;
 905     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
 906                                      info->config_read, info->config_write);
 907     assert(pci_dev);
 908     return info->init(pci_dev);
 909 }
 910
 911 void pci_qdev_register(PCIDeviceInfo *info)
 912 {
 913     info->qdev.init = pci_qdev_init;
 914     info->qdev.bus_info = &pci_bus_info;
 915     qdev_register(&info->qdev);
 916 }
 917
 918 void pci_qdev_register_many(PCIDeviceInfo *info)
 919 {
 920     while (info->qdev.name) {
 921         pci_qdev_register(info);
 922         info++;
 923     }
 924 }
 925
 926 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
 927 {
 928     DeviceState *dev;
 929
 930     dev = qdev_create(&bus->qbus, name);
 931     qdev_prop_set_uint32(dev, "addr", devfn);
 932     qdev_init(dev);
 933
 934     return (PCIDevice *)dev;
 935 }
 936
 937 static int pci_find_space(PCIDevice *pdev, uint8_t size)
 938 {
 939     int offset = PCI_CONFIG_HEADER_SIZE;
 940     int i;
 941     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 942         if (pdev->used[i])
 943             offset = i + 1;
 944         else if (i - offset + 1 == size)
 945             return offset;
 946     return 0;
 947 }
 948
 949 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
 950                                         uint8_t *prev_p)
 951 {
 952     uint8_t next, prev;
 953
 954     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
 955         return 0;
 956
 957     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
 958          prev = next + PCI_CAP_LIST_NEXT)
 959         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
 960             break;
 961
 962     if (prev_p)
 963         *prev_p = prev;
 964     return next;
 965 }
 966
 967 /* Reserve space and add capability to the linked list in pci config space */
 968 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 969 {
 970     uint8_t offset = pci_find_space(pdev, size);
 971     uint8_t *config = pdev->config + offset;
 972     if (!offset)
 973         return -ENOSPC;
 974     config[PCI_CAP_LIST_ID] = cap_id;
 975     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
 976     pdev->config[PCI_CAPABILITY_LIST] = offset;
 977     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
 978     memset(pdev->used + offset, 0xFF, size);
 979     /* Make capability read-only by default */
 980     memset(pdev->wmask + offset, 0, size);
 981     /* Check capability by default */
 982     memset(pdev->cmask + offset, 0xFF, size);
 983     return offset;
 984 }
 985
 986 /* Unlink capability from the pci config space. */
 987 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 988 {
 989     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
 990     if (!offset)
 991         return;
 992     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
 993     /* Make capability writeable again */
 994     memset(pdev->wmask + offset, 0xff, size);
 995     /* Clear cmask as device-specific registers can't be checked */
 996     memset(pdev->cmask + offset, 0, size);
 997     memset(pdev->used + offset, 0, size);
 998
 999     if (!pdev->config[PCI_CAPABILITY_LIST])
1000         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1001 }
1002
1003 /* Reserve space for capability at a known offset (to call after load). */
1004 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1005 {
1006     memset(pdev->used + offset, 0xff, size);
1007 }
1008
1009 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1010 {
1011     return pci_find_capability_list(pdev, cap_id, NULL);
1012 }
1013
1014 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1015 {
1016     PCIDevice *d = (PCIDevice *)dev;
1017     const pci_class_desc *desc;
1018     char ctxt[64];
1019     PCIIORegion *r;
1020     int i, class;
1021
1022     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1023     desc = pci_class_descriptions;
1024     while (desc->desc && class != desc->class)
1025         desc++;
1026     if (desc->desc) {
1027         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1028     } else {
1029         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1030     }
1031
1032     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1033                    "pci id %04x:%04x (sub %04x:%04x)\n",
1034                    indent, "", ctxt,
1035                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1036                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1037                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1038                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1039                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1040     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1041         r = &d->io_regions[i];
1042         if (!r->size)
1043             continue;
1044         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1045                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1046                        r->addr, r->addr + r->size - 1);
1047     }
1048 }