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qemu-io: Implement bdrv_load_vmstate/bdrv_save_vmstate
[armpft.git] / hw / sun4m.c
blob220eaae3ebd05c4b62e663d6ea8513643abd51dc
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39
40 //#define DEBUG_IRQ
41
42 /*
43 * Sun4m architecture was used in the following machines:
44 *
45 * SPARCserver 6xxMP/xx
46 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47 * SPARCclassic X (4/10)
48 * SPARCstation LX/ZX (4/30)
49 * SPARCstation Voyager
50 * SPARCstation 10/xx, SPARCserver 10/xx
51 * SPARCstation 5, SPARCserver 5
52 * SPARCstation 20/xx, SPARCserver 20
53 * SPARCstation 4
54 *
55 * Sun4d architecture was used in the following machines:
56 *
57 * SPARCcenter 2000
58 * SPARCserver 1000
59 *
60 * Sun4c architecture was used in the following machines:
61 * SPARCstation 1/1+, SPARCserver 1/1+
62 * SPARCstation SLC
63 * SPARCstation IPC
64 * SPARCstation ELC
65 * SPARCstation IPX
66 *
67 * See for example: http://www.sunhelp.org/faq/sunref1.html
68 */
69
70 #ifdef DEBUG_IRQ
71 #define DPRINTF(fmt, ...) \
72 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
73 #else
74 #define DPRINTF(fmt, ...)
75 #endif
76
77 #define KERNEL_LOAD_ADDR 0x00004000
78 #define CMDLINE_ADDR 0x007ff000
79 #define INITRD_LOAD_ADDR 0x00800000
80 #define PROM_SIZE_MAX (1024 * 1024)
81 #define PROM_VADDR 0xffd00000
82 #define PROM_FILENAME "openbios-sparc32"
83 #define CFG_ADDR 0xd00000510ULL
84 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85
86 #define MAX_CPUS 16
87 #define MAX_PILS 16
88
89 #define ESCC_CLOCK 4915200
90
91 struct sun4m_hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint32_t intbit_to_level[32];
148 uint64_t max_mem;
149 const char * const default_cpu_model;
150 };
151
152 int DMA_get_channel_mode (int nchan)
153 {
154 return 0;
155 }
156 int DMA_read_memory (int nchan, void *buf, int pos, int size)
157 {
158 return 0;
159 }
160 int DMA_write_memory (int nchan, void *buf, int pos, int size)
161 {
162 return 0;
163 }
164 void DMA_hold_DREQ (int nchan) {}
165 void DMA_release_DREQ (int nchan) {}
166 void DMA_schedule(int nchan) {}
167 void DMA_init (int high_page_enable) {}
168 void DMA_register_channel (int nchan,
169 DMA_transfer_handler transfer_handler,
170 void *opaque)
171 {
172 }
173
174 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
175 {
176 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
177 return 0;
178 }
179
180 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
181 const char *boot_devices, ram_addr_t RAM_size,
182 uint32_t kernel_size,
183 int width, int height, int depth,
184 int nvram_machine_id, const char *arch)
185 {
186 unsigned int i;
187 uint32_t start, end;
188 uint8_t image[0x1ff0];
189 struct OpenBIOS_nvpart_v1 *part_header;
190
191 memset(image, '\0', sizeof(image));
192
193 start = 0;
194
195 // OpenBIOS nvram variables
196 // Variable partition
197 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
198 part_header->signature = OPENBIOS_PART_SYSTEM;
199 pstrcpy(part_header->name, sizeof(part_header->name), "system");
200
201 end = start + sizeof(struct OpenBIOS_nvpart_v1);
202 for (i = 0; i < nb_prom_envs; i++)
203 end = OpenBIOS_set_var(image, end, prom_envs[i]);
204
205 // End marker
206 image[end++] = '\0';
207
208 end = start + ((end - start + 15) & ~15);
209 OpenBIOS_finish_partition(part_header, end - start);
210
211 // free partition
212 start = end;
213 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
214 part_header->signature = OPENBIOS_PART_FREE;
215 pstrcpy(part_header->name, sizeof(part_header->name), "free");
216
217 end = 0x1fd0;
218 OpenBIOS_finish_partition(part_header, end - start);
219
220 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
221 nvram_machine_id);
222
223 for (i = 0; i < sizeof(image); i++)
224 m48t59_write(nvram, i, image[i]);
225 }
226
227 static void *slavio_intctl;
228
229 void pic_info(Monitor *mon)
230 {
231 if (slavio_intctl)
232 slavio_pic_info(mon, slavio_intctl);
233 }
234
235 void irq_info(Monitor *mon)
236 {
237 if (slavio_intctl)
238 slavio_irq_info(mon, slavio_intctl);
239 }
240
241 void cpu_check_irqs(CPUState *env)
242 {
243 if (env->pil_in && (env->interrupt_index == 0 ||
244 (env->interrupt_index & ~15) == TT_EXTINT)) {
245 unsigned int i;
246
247 for (i = 15; i > 0; i--) {
248 if (env->pil_in & (1 << i)) {
249 int old_interrupt = env->interrupt_index;
250
251 env->interrupt_index = TT_EXTINT | i;
252 if (old_interrupt != env->interrupt_index) {
253 DPRINTF("Set CPU IRQ %d\n", i);
254 cpu_interrupt(env, CPU_INTERRUPT_HARD);
255 }
256 break;
257 }
258 }
259 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
260 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
261 env->interrupt_index = 0;
262 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
263 }
264 }
265
266 static void cpu_set_irq(void *opaque, int irq, int level)
267 {
268 CPUState *env = opaque;
269
270 if (level) {
271 DPRINTF("Raise CPU IRQ %d\n", irq);
272 env->halted = 0;
273 env->pil_in |= 1 << irq;
274 cpu_check_irqs(env);
275 } else {
276 DPRINTF("Lower CPU IRQ %d\n", irq);
277 env->pil_in &= ~(1 << irq);
278 cpu_check_irqs(env);
279 }
280 }
281
282 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
283 {
284 }
285
286 static void *slavio_misc;
287
288 void qemu_system_powerdown(void)
289 {
290 slavio_set_power_fail(slavio_misc, 1);
291 }
292
293 static void main_cpu_reset(void *opaque)
294 {
295 CPUState *env = opaque;
296
297 cpu_reset(env);
298 env->halted = 0;
299 }
300
301 static void secondary_cpu_reset(void *opaque)
302 {
303 CPUState *env = opaque;
304
305 cpu_reset(env);
306 env->halted = 1;
307 }
308
309 static void cpu_halt_signal(void *opaque, int irq, int level)
310 {
311 if (level && cpu_single_env)
312 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
313 }
314
315 static unsigned long sun4m_load_kernel(const char *kernel_filename,
316 const char *initrd_filename,
317 ram_addr_t RAM_size)
318 {
319 int linux_boot;
320 unsigned int i;
321 long initrd_size, kernel_size;
322
323 linux_boot = (kernel_filename != NULL);
324
325 kernel_size = 0;
326 if (linux_boot) {
327 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
328 NULL);
329 if (kernel_size < 0)
330 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
331 RAM_size - KERNEL_LOAD_ADDR);
332 if (kernel_size < 0)
333 kernel_size = load_image_targphys(kernel_filename,
334 KERNEL_LOAD_ADDR,
335 RAM_size - KERNEL_LOAD_ADDR);
336 if (kernel_size < 0) {
337 fprintf(stderr, "qemu: could not load kernel '%s'\n",
338 kernel_filename);
339 exit(1);
340 }
341
342 /* load initrd */
343 initrd_size = 0;
344 if (initrd_filename) {
345 initrd_size = load_image_targphys(initrd_filename,
346 INITRD_LOAD_ADDR,
347 RAM_size - INITRD_LOAD_ADDR);
348 if (initrd_size < 0) {
349 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
350 initrd_filename);
351 exit(1);
352 }
353 }
354 if (initrd_size > 0) {
355 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
356 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
357 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
358 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
359 break;
360 }
361 }
362 }
363 }
364 return kernel_size;
365 }
366
367 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
368 void *dma_opaque, qemu_irq irq, qemu_irq *reset)
369 {
370 DeviceState *dev;
371 SysBusDevice *s;
372
373 qemu_check_nic_model(&nd_table[0], "lance");
374
375 dev = qdev_create(NULL, "lance");
376 qdev_set_netdev(dev, nd);
377 qdev_set_prop_ptr(dev, "dma", dma_opaque);
378 qdev_init(dev);
379 s = sysbus_from_qdev(dev);
380 sysbus_mmio_map(s, 0, leaddr);
381 sysbus_connect_irq(s, 0, irq);
382 *reset = qdev_get_gpio_in(dev, 0);
383 }
384
385 /* NCR89C100/MACIO Internal ID register */
386 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
387
388 static void idreg_init(target_phys_addr_t addr)
389 {
390 DeviceState *dev;
391 SysBusDevice *s;
392
393 dev = qdev_create(NULL, "macio_idreg");
394 qdev_init(dev);
395 s = sysbus_from_qdev(dev);
396
397 sysbus_mmio_map(s, 0, addr);
398 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
399 }
400
401 static void idreg_init1(SysBusDevice *dev)
402 {
403 ram_addr_t idreg_offset;
404
405 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
406 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
407 }
408
409 static SysBusDeviceInfo idreg_info = {
410 .init = idreg_init1,
411 .qdev.name = "macio_idreg",
412 .qdev.size = sizeof(SysBusDevice),
413 .qdev.props = (DevicePropList[]) {
414 {.name = NULL}
415 }
416 };
417
418 static void idreg_register_devices(void)
419 {
420 sysbus_register_withprop(&idreg_info);
421 }
422
423 device_init(idreg_register_devices);
424
425 /* Boot PROM (OpenBIOS) */
426 static void prom_init(target_phys_addr_t addr, const char *bios_name)
427 {
428 DeviceState *dev;
429 SysBusDevice *s;
430 char *filename;
431 int ret;
432
433 dev = qdev_create(NULL, "openprom");
434 qdev_init(dev);
435 s = sysbus_from_qdev(dev);
436
437 sysbus_mmio_map(s, 0, addr);
438
439 /* load boot prom */
440 if (bios_name == NULL) {
441 bios_name = PROM_FILENAME;
442 }
443 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
444 if (filename) {
445 ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL);
446 if (ret < 0 || ret > PROM_SIZE_MAX) {
447 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
448 }
449 qemu_free(filename);
450 } else {
451 ret = -1;
452 }
453 if (ret < 0 || ret > PROM_SIZE_MAX) {
454 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
455 exit(1);
456 }
457 }
458
459 static void prom_init1(SysBusDevice *dev)
460 {
461 ram_addr_t prom_offset;
462
463 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
464 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
465 }
466
467 static SysBusDeviceInfo prom_info = {
468 .init = prom_init1,
469 .qdev.name = "openprom",
470 .qdev.size = sizeof(SysBusDevice),
471 .qdev.props = (DevicePropList[]) {
472 {.name = NULL}
473 }
474 };
475
476 static void prom_register_devices(void)
477 {
478 sysbus_register_withprop(&prom_info);
479 }
480
481 device_init(prom_register_devices);
482
483 /* System RAM */
484 static void ram_init1(SysBusDevice *dev)
485 {
486 ram_addr_t RAM_size, ram_offset;
487
488 RAM_size = qdev_get_prop_int(&dev->qdev, "size", 0);
489
490 ram_offset = qemu_ram_alloc(RAM_size);
491 sysbus_init_mmio(dev, RAM_size, ram_offset);
492 }
493
494 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
495 uint64_t max_mem)
496 {
497 DeviceState *dev;
498 SysBusDevice *s;
499
500 /* allocate RAM */
501 if ((uint64_t)RAM_size > max_mem) {
502 fprintf(stderr,
503 "qemu: Too much memory for this machine: %d, maximum %d\n",
504 (unsigned int)(RAM_size / (1024 * 1024)),
505 (unsigned int)(max_mem / (1024 * 1024)));
506 exit(1);
507 }
508 dev = qdev_create(NULL, "memory");
509 qdev_set_prop_int(dev, "size", RAM_size);
510 qdev_init(dev);
511 s = sysbus_from_qdev(dev);
512
513 sysbus_mmio_map(s, 0, addr);
514 }
515
516 static SysBusDeviceInfo ram_info = {
517 .init = ram_init1,
518 .qdev.name = "memory",
519 .qdev.size = sizeof(SysBusDevice),
520 .qdev.props = (DevicePropList[]) {
521 {.name = "size", .type = PROP_TYPE_INT},
522 {.name = NULL}
523 }
524 };
525
526 static void ram_register_devices(void)
527 {
528 sysbus_register_withprop(&ram_info);
529 }
530
531 device_init(ram_register_devices);
532
533 static CPUState *cpu_devinit(const char *cpu_model, unsigned int id,
534 uint64_t prom_addr, qemu_irq **cpu_irqs)
535 {
536 CPUState *env;
537
538 env = cpu_init(cpu_model);
539 if (!env) {
540 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
541 exit(1);
542 }
543
544 cpu_sparc_set_id(env, id);
545 if (id == 0) {
546 qemu_register_reset(main_cpu_reset, env);
547 } else {
548 qemu_register_reset(secondary_cpu_reset, env);
549 env->halted = 1;
550 }
551 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
552 env->prom_addr = prom_addr;
553
554 return env;
555 }
556
557 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
558 const char *boot_device,
559 const char *kernel_filename,
560 const char *kernel_cmdline,
561 const char *initrd_filename, const char *cpu_model)
562 {
563 CPUState *envs[MAX_CPUS];
564 unsigned int i;
565 void *iommu, *espdma, *ledma, *nvram;
566 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
567 espdma_irq, ledma_irq;
568 qemu_irq *esp_reset, *le_reset;
569 qemu_irq fdc_tc;
570 qemu_irq *cpu_halt;
571 unsigned long kernel_size;
572 BlockDriverState *fd[MAX_FD];
573 int drive_index;
574 void *fw_cfg;
575 DeviceState *dev;
576
577 /* init CPUs */
578 if (!cpu_model)
579 cpu_model = hwdef->default_cpu_model;
580
581 for(i = 0; i < smp_cpus; i++) {
582 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
583 }
584
585 for (i = smp_cpus; i < MAX_CPUS; i++)
586 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
587
588
589 /* set up devices */
590 ram_init(0, RAM_size, hwdef->max_mem);
591
592 prom_init(hwdef->slavio_base, bios_name);
593
594 dev = slavio_intctl_init(hwdef->intctl_base,
595 hwdef->intctl_base + 0x10000ULL,
596 &hwdef->intbit_to_level[0],
597 cpu_irqs,
598 hwdef->clock_irq);
599
600 for (i = 0; i < 32; i++) {
601 slavio_irq[i] = qdev_get_gpio_in(dev, i);
602 }
603 for (i = 0; i < MAX_CPUS; i++) {
604 slavio_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
605 }
606
607 if (hwdef->idreg_base) {
608 idreg_init(hwdef->idreg_base);
609 }
610
611 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
612 slavio_irq[hwdef->me_irq]);
613
614 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
615 iommu, &espdma_irq, &esp_reset);
616
617 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
618 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
619 &le_reset);
620
621 if (graphic_depth != 8 && graphic_depth != 24) {
622 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
623 exit (1);
624 }
625 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
626 graphic_depth);
627
628 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
629
630 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
631 hwdef->nvram_size, 8);
632
633 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
634 slavio_cpu_irq, smp_cpus);
635
636 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
637 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
638 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
639 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
640 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
641 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
642
643 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
644 slavio_misc = slavio_misc_init(hwdef->slavio_base,
645 hwdef->aux1_base, hwdef->aux2_base,
646 slavio_irq[hwdef->me_irq], fdc_tc);
647 if (hwdef->apc_base) {
648 apc_init(hwdef->apc_base, cpu_halt[0]);
649 }
650
651 if (hwdef->fd_base) {
652 /* there is zero or one floppy drive */
653 memset(fd, 0, sizeof(fd));
654 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
655 if (drive_index != -1)
656 fd[0] = drives_table[drive_index].bdrv;
657
658 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
659 &fdc_tc);
660 }
661
662 if (drive_get_max_bus(IF_SCSI) > 0) {
663 fprintf(stderr, "qemu: too many SCSI bus\n");
664 exit(1);
665 }
666
667 esp_init(hwdef->esp_base, 2,
668 espdma_memory_read, espdma_memory_write,
669 espdma, espdma_irq, esp_reset);
670
671 if (hwdef->cs_base) {
672 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
673 slavio_irq[hwdef->cs_irq]);
674 }
675
676 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
677 RAM_size);
678
679 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
680 boot_device, RAM_size, kernel_size, graphic_width,
681 graphic_height, graphic_depth, hwdef->nvram_machine_id,
682 "Sun4m");
683
684 if (hwdef->ecc_base)
685 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
686 hwdef->ecc_version);
687
688 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
689 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
690 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
691 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
692 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
693 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
694 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
695 if (kernel_cmdline) {
696 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
697 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
698 } else {
699 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
700 }
701 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
702 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
703 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
704 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
705 }
706
707 enum {
708 ss2_id = 0,
709 ss5_id = 32,
710 vger_id,
711 lx_id,
712 ss4_id,
713 scls_id,
714 sbook_id,
715 ss10_id = 64,
716 ss20_id,
717 ss600mp_id,
718 ss1000_id = 96,
719 ss2000_id,
720 };
721
722 static const struct sun4m_hwdef sun4m_hwdefs[] = {
723 /* SS-5 */
724 {
725 .iommu_base = 0x10000000,
726 .tcx_base = 0x50000000,
727 .cs_base = 0x6c000000,
728 .slavio_base = 0x70000000,
729 .ms_kb_base = 0x71000000,
730 .serial_base = 0x71100000,
731 .nvram_base = 0x71200000,
732 .fd_base = 0x71400000,
733 .counter_base = 0x71d00000,
734 .intctl_base = 0x71e00000,
735 .idreg_base = 0x78000000,
736 .dma_base = 0x78400000,
737 .esp_base = 0x78800000,
738 .le_base = 0x78c00000,
739 .apc_base = 0x6a000000,
740 .aux1_base = 0x71900000,
741 .aux2_base = 0x71910000,
742 .vram_size = 0x00100000,
743 .nvram_size = 0x2000,
744 .esp_irq = 18,
745 .le_irq = 16,
746 .clock_irq = 7,
747 .clock1_irq = 19,
748 .ms_kb_irq = 14,
749 .ser_irq = 15,
750 .fd_irq = 22,
751 .me_irq = 30,
752 .cs_irq = 5,
753 .nvram_machine_id = 0x80,
754 .machine_id = ss5_id,
755 .iommu_version = 0x05000000,
756 .intbit_to_level = {
757 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
758 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
759 },
760 .max_mem = 0x10000000,
761 .default_cpu_model = "Fujitsu MB86904",
762 },
763 /* SS-10 */
764 {
765 .iommu_base = 0xfe0000000ULL,
766 .tcx_base = 0xe20000000ULL,
767 .slavio_base = 0xff0000000ULL,
768 .ms_kb_base = 0xff1000000ULL,
769 .serial_base = 0xff1100000ULL,
770 .nvram_base = 0xff1200000ULL,
771 .fd_base = 0xff1700000ULL,
772 .counter_base = 0xff1300000ULL,
773 .intctl_base = 0xff1400000ULL,
774 .idreg_base = 0xef0000000ULL,
775 .dma_base = 0xef0400000ULL,
776 .esp_base = 0xef0800000ULL,
777 .le_base = 0xef0c00000ULL,
778 .apc_base = 0xefa000000ULL, // XXX should not exist
779 .aux1_base = 0xff1800000ULL,
780 .aux2_base = 0xff1a01000ULL,
781 .ecc_base = 0xf00000000ULL,
782 .ecc_version = 0x10000000, // version 0, implementation 1
783 .vram_size = 0x00100000,
784 .nvram_size = 0x2000,
785 .esp_irq = 18,
786 .le_irq = 16,
787 .clock_irq = 7,
788 .clock1_irq = 19,
789 .ms_kb_irq = 14,
790 .ser_irq = 15,
791 .fd_irq = 22,
792 .me_irq = 30,
793 .ecc_irq = 28,
794 .nvram_machine_id = 0x72,
795 .machine_id = ss10_id,
796 .iommu_version = 0x03000000,
797 .intbit_to_level = {
798 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
799 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
800 },
801 .max_mem = 0xf00000000ULL,
802 .default_cpu_model = "TI SuperSparc II",
803 },
804 /* SS-600MP */
805 {
806 .iommu_base = 0xfe0000000ULL,
807 .tcx_base = 0xe20000000ULL,
808 .slavio_base = 0xff0000000ULL,
809 .ms_kb_base = 0xff1000000ULL,
810 .serial_base = 0xff1100000ULL,
811 .nvram_base = 0xff1200000ULL,
812 .counter_base = 0xff1300000ULL,
813 .intctl_base = 0xff1400000ULL,
814 .dma_base = 0xef0081000ULL,
815 .esp_base = 0xef0080000ULL,
816 .le_base = 0xef0060000ULL,
817 .apc_base = 0xefa000000ULL, // XXX should not exist
818 .aux1_base = 0xff1800000ULL,
819 .aux2_base = 0xff1a01000ULL, // XXX should not exist
820 .ecc_base = 0xf00000000ULL,
821 .ecc_version = 0x00000000, // version 0, implementation 0
822 .vram_size = 0x00100000,
823 .nvram_size = 0x2000,
824 .esp_irq = 18,
825 .le_irq = 16,
826 .clock_irq = 7,
827 .clock1_irq = 19,
828 .ms_kb_irq = 14,
829 .ser_irq = 15,
830 .fd_irq = 22,
831 .me_irq = 30,
832 .ecc_irq = 28,
833 .nvram_machine_id = 0x71,
834 .machine_id = ss600mp_id,
835 .iommu_version = 0x01000000,
836 .intbit_to_level = {
837 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
838 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
839 },
840 .max_mem = 0xf00000000ULL,
841 .default_cpu_model = "TI SuperSparc II",
842 },
843 /* SS-20 */
844 {
845 .iommu_base = 0xfe0000000ULL,
846 .tcx_base = 0xe20000000ULL,
847 .slavio_base = 0xff0000000ULL,
848 .ms_kb_base = 0xff1000000ULL,
849 .serial_base = 0xff1100000ULL,
850 .nvram_base = 0xff1200000ULL,
851 .fd_base = 0xff1700000ULL,
852 .counter_base = 0xff1300000ULL,
853 .intctl_base = 0xff1400000ULL,
854 .idreg_base = 0xef0000000ULL,
855 .dma_base = 0xef0400000ULL,
856 .esp_base = 0xef0800000ULL,
857 .le_base = 0xef0c00000ULL,
858 .apc_base = 0xefa000000ULL, // XXX should not exist
859 .aux1_base = 0xff1800000ULL,
860 .aux2_base = 0xff1a01000ULL,
861 .ecc_base = 0xf00000000ULL,
862 .ecc_version = 0x20000000, // version 0, implementation 2
863 .vram_size = 0x00100000,
864 .nvram_size = 0x2000,
865 .esp_irq = 18,
866 .le_irq = 16,
867 .clock_irq = 7,
868 .clock1_irq = 19,
869 .ms_kb_irq = 14,
870 .ser_irq = 15,
871 .fd_irq = 22,
872 .me_irq = 30,
873 .ecc_irq = 28,
874 .nvram_machine_id = 0x72,
875 .machine_id = ss20_id,
876 .iommu_version = 0x13000000,
877 .intbit_to_level = {
878 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
879 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
880 },
881 .max_mem = 0xf00000000ULL,
882 .default_cpu_model = "TI SuperSparc II",
883 },
884 /* Voyager */
885 {
886 .iommu_base = 0x10000000,
887 .tcx_base = 0x50000000,
888 .slavio_base = 0x70000000,
889 .ms_kb_base = 0x71000000,
890 .serial_base = 0x71100000,
891 .nvram_base = 0x71200000,
892 .fd_base = 0x71400000,
893 .counter_base = 0x71d00000,
894 .intctl_base = 0x71e00000,
895 .idreg_base = 0x78000000,
896 .dma_base = 0x78400000,
897 .esp_base = 0x78800000,
898 .le_base = 0x78c00000,
899 .apc_base = 0x71300000, // pmc
900 .aux1_base = 0x71900000,
901 .aux2_base = 0x71910000,
902 .vram_size = 0x00100000,
903 .nvram_size = 0x2000,
904 .esp_irq = 18,
905 .le_irq = 16,
906 .clock_irq = 7,
907 .clock1_irq = 19,
908 .ms_kb_irq = 14,
909 .ser_irq = 15,
910 .fd_irq = 22,
911 .me_irq = 30,
912 .nvram_machine_id = 0x80,
913 .machine_id = vger_id,
914 .iommu_version = 0x05000000,
915 .intbit_to_level = {
916 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
917 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
918 },
919 .max_mem = 0x10000000,
920 .default_cpu_model = "Fujitsu MB86904",
921 },
922 /* LX */
923 {
924 .iommu_base = 0x10000000,
925 .tcx_base = 0x50000000,
926 .slavio_base = 0x70000000,
927 .ms_kb_base = 0x71000000,
928 .serial_base = 0x71100000,
929 .nvram_base = 0x71200000,
930 .fd_base = 0x71400000,
931 .counter_base = 0x71d00000,
932 .intctl_base = 0x71e00000,
933 .idreg_base = 0x78000000,
934 .dma_base = 0x78400000,
935 .esp_base = 0x78800000,
936 .le_base = 0x78c00000,
937 .aux1_base = 0x71900000,
938 .aux2_base = 0x71910000,
939 .vram_size = 0x00100000,
940 .nvram_size = 0x2000,
941 .esp_irq = 18,
942 .le_irq = 16,
943 .clock_irq = 7,
944 .clock1_irq = 19,
945 .ms_kb_irq = 14,
946 .ser_irq = 15,
947 .fd_irq = 22,
948 .me_irq = 30,
949 .nvram_machine_id = 0x80,
950 .machine_id = lx_id,
951 .iommu_version = 0x04000000,
952 .intbit_to_level = {
953 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
954 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
955 },
956 .max_mem = 0x10000000,
957 .default_cpu_model = "TI MicroSparc I",
958 },
959 /* SS-4 */
960 {
961 .iommu_base = 0x10000000,
962 .tcx_base = 0x50000000,
963 .cs_base = 0x6c000000,
964 .slavio_base = 0x70000000,
965 .ms_kb_base = 0x71000000,
966 .serial_base = 0x71100000,
967 .nvram_base = 0x71200000,
968 .fd_base = 0x71400000,
969 .counter_base = 0x71d00000,
970 .intctl_base = 0x71e00000,
971 .idreg_base = 0x78000000,
972 .dma_base = 0x78400000,
973 .esp_base = 0x78800000,
974 .le_base = 0x78c00000,
975 .apc_base = 0x6a000000,
976 .aux1_base = 0x71900000,
977 .aux2_base = 0x71910000,
978 .vram_size = 0x00100000,
979 .nvram_size = 0x2000,
980 .esp_irq = 18,
981 .le_irq = 16,
982 .clock_irq = 7,
983 .clock1_irq = 19,
984 .ms_kb_irq = 14,
985 .ser_irq = 15,
986 .fd_irq = 22,
987 .me_irq = 30,
988 .cs_irq = 5,
989 .nvram_machine_id = 0x80,
990 .machine_id = ss4_id,
991 .iommu_version = 0x05000000,
992 .intbit_to_level = {
993 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
994 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
995 },
996 .max_mem = 0x10000000,
997 .default_cpu_model = "Fujitsu MB86904",
998 },
999 /* SPARCClassic */
1000 {
1001 .iommu_base = 0x10000000,
1002 .tcx_base = 0x50000000,
1003 .slavio_base = 0x70000000,
1004 .ms_kb_base = 0x71000000,
1005 .serial_base = 0x71100000,
1006 .nvram_base = 0x71200000,
1007 .fd_base = 0x71400000,
1008 .counter_base = 0x71d00000,
1009 .intctl_base = 0x71e00000,
1010 .idreg_base = 0x78000000,
1011 .dma_base = 0x78400000,
1012 .esp_base = 0x78800000,
1013 .le_base = 0x78c00000,
1014 .apc_base = 0x6a000000,
1015 .aux1_base = 0x71900000,
1016 .aux2_base = 0x71910000,
1017 .vram_size = 0x00100000,
1018 .nvram_size = 0x2000,
1019 .esp_irq = 18,
1020 .le_irq = 16,
1021 .clock_irq = 7,
1022 .clock1_irq = 19,
1023 .ms_kb_irq = 14,
1024 .ser_irq = 15,
1025 .fd_irq = 22,
1026 .me_irq = 30,
1027 .nvram_machine_id = 0x80,
1028 .machine_id = scls_id,
1029 .iommu_version = 0x05000000,
1030 .intbit_to_level = {
1031 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1032 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1033 },
1034 .max_mem = 0x10000000,
1035 .default_cpu_model = "TI MicroSparc I",
1036 },
1037 /* SPARCbook */
1038 {
1039 .iommu_base = 0x10000000,
1040 .tcx_base = 0x50000000, // XXX
1041 .slavio_base = 0x70000000,
1042 .ms_kb_base = 0x71000000,
1043 .serial_base = 0x71100000,
1044 .nvram_base = 0x71200000,
1045 .fd_base = 0x71400000,
1046 .counter_base = 0x71d00000,
1047 .intctl_base = 0x71e00000,
1048 .idreg_base = 0x78000000,
1049 .dma_base = 0x78400000,
1050 .esp_base = 0x78800000,
1051 .le_base = 0x78c00000,
1052 .apc_base = 0x6a000000,
1053 .aux1_base = 0x71900000,
1054 .aux2_base = 0x71910000,
1055 .vram_size = 0x00100000,
1056 .nvram_size = 0x2000,
1057 .esp_irq = 18,
1058 .le_irq = 16,
1059 .clock_irq = 7,
1060 .clock1_irq = 19,
1061 .ms_kb_irq = 14,
1062 .ser_irq = 15,
1063 .fd_irq = 22,
1064 .me_irq = 30,
1065 .nvram_machine_id = 0x80,
1066 .machine_id = sbook_id,
1067 .iommu_version = 0x05000000,
1068 .intbit_to_level = {
1069 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1070 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1071 },
1072 .max_mem = 0x10000000,
1073 .default_cpu_model = "TI MicroSparc I",
1074 },
1075 };
1076
1077 /* SPARCstation 5 hardware initialisation */
1078 static void ss5_init(ram_addr_t RAM_size,
1079 const char *boot_device,
1080 const char *kernel_filename, const char *kernel_cmdline,
1081 const char *initrd_filename, const char *cpu_model)
1082 {
1083 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1084 kernel_cmdline, initrd_filename, cpu_model);
1085 }
1086
1087 /* SPARCstation 10 hardware initialisation */
1088 static void ss10_init(ram_addr_t RAM_size,
1089 const char *boot_device,
1090 const char *kernel_filename, const char *kernel_cmdline,
1091 const char *initrd_filename, const char *cpu_model)
1092 {
1093 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1094 kernel_cmdline, initrd_filename, cpu_model);
1095 }
1096
1097 /* SPARCserver 600MP hardware initialisation */
1098 static void ss600mp_init(ram_addr_t RAM_size,
1099 const char *boot_device,
1100 const char *kernel_filename,
1101 const char *kernel_cmdline,
1102 const char *initrd_filename, const char *cpu_model)
1103 {
1104 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1105 kernel_cmdline, initrd_filename, cpu_model);
1106 }
1107
1108 /* SPARCstation 20 hardware initialisation */
1109 static void ss20_init(ram_addr_t RAM_size,
1110 const char *boot_device,
1111 const char *kernel_filename, const char *kernel_cmdline,
1112 const char *initrd_filename, const char *cpu_model)
1113 {
1114 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1115 kernel_cmdline, initrd_filename, cpu_model);
1116 }
1117
1118 /* SPARCstation Voyager hardware initialisation */
1119 static void vger_init(ram_addr_t RAM_size,
1120 const char *boot_device,
1121 const char *kernel_filename, const char *kernel_cmdline,
1122 const char *initrd_filename, const char *cpu_model)
1123 {
1124 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1125 kernel_cmdline, initrd_filename, cpu_model);
1126 }
1127
1128 /* SPARCstation LX hardware initialisation */
1129 static void ss_lx_init(ram_addr_t RAM_size,
1130 const char *boot_device,
1131 const char *kernel_filename, const char *kernel_cmdline,
1132 const char *initrd_filename, const char *cpu_model)
1133 {
1134 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1135 kernel_cmdline, initrd_filename, cpu_model);
1136 }
1137
1138 /* SPARCstation 4 hardware initialisation */
1139 static void ss4_init(ram_addr_t RAM_size,
1140 const char *boot_device,
1141 const char *kernel_filename, const char *kernel_cmdline,
1142 const char *initrd_filename, const char *cpu_model)
1143 {
1144 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1145 kernel_cmdline, initrd_filename, cpu_model);
1146 }
1147
1148 /* SPARCClassic hardware initialisation */
1149 static void scls_init(ram_addr_t RAM_size,
1150 const char *boot_device,
1151 const char *kernel_filename, const char *kernel_cmdline,
1152 const char *initrd_filename, const char *cpu_model)
1153 {
1154 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1155 kernel_cmdline, initrd_filename, cpu_model);
1156 }
1157
1158 /* SPARCbook hardware initialisation */
1159 static void sbook_init(ram_addr_t RAM_size,
1160 const char *boot_device,
1161 const char *kernel_filename, const char *kernel_cmdline,
1162 const char *initrd_filename, const char *cpu_model)
1163 {
1164 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1165 kernel_cmdline, initrd_filename, cpu_model);
1166 }
1167
1168 static QEMUMachine ss5_machine = {
1169 .name = "SS-5",
1170 .desc = "Sun4m platform, SPARCstation 5",
1171 .init = ss5_init,
1172 .use_scsi = 1,
1173 .is_default = 1,
1174 };
1175
1176 static QEMUMachine ss10_machine = {
1177 .name = "SS-10",
1178 .desc = "Sun4m platform, SPARCstation 10",
1179 .init = ss10_init,
1180 .use_scsi = 1,
1181 .max_cpus = 4,
1182 };
1183
1184 static QEMUMachine ss600mp_machine = {
1185 .name = "SS-600MP",
1186 .desc = "Sun4m platform, SPARCserver 600MP",
1187 .init = ss600mp_init,
1188 .use_scsi = 1,
1189 .max_cpus = 4,
1190 };
1191
1192 static QEMUMachine ss20_machine = {
1193 .name = "SS-20",
1194 .desc = "Sun4m platform, SPARCstation 20",
1195 .init = ss20_init,
1196 .use_scsi = 1,
1197 .max_cpus = 4,
1198 };
1199
1200 static QEMUMachine voyager_machine = {
1201 .name = "Voyager",
1202 .desc = "Sun4m platform, SPARCstation Voyager",
1203 .init = vger_init,
1204 .use_scsi = 1,
1205 };
1206
1207 static QEMUMachine ss_lx_machine = {
1208 .name = "LX",
1209 .desc = "Sun4m platform, SPARCstation LX",
1210 .init = ss_lx_init,
1211 .use_scsi = 1,
1212 };
1213
1214 static QEMUMachine ss4_machine = {
1215 .name = "SS-4",
1216 .desc = "Sun4m platform, SPARCstation 4",
1217 .init = ss4_init,
1218 .use_scsi = 1,
1219 };
1220
1221 static QEMUMachine scls_machine = {
1222 .name = "SPARCClassic",
1223 .desc = "Sun4m platform, SPARCClassic",
1224 .init = scls_init,
1225 .use_scsi = 1,
1226 };
1227
1228 static QEMUMachine sbook_machine = {
1229 .name = "SPARCbook",
1230 .desc = "Sun4m platform, SPARCbook",
1231 .init = sbook_init,
1232 .use_scsi = 1,
1233 };
1234
1235 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1236 /* SS-1000 */
1237 {
1238 .iounit_bases = {
1239 0xfe0200000ULL,
1240 0xfe1200000ULL,
1241 0xfe2200000ULL,
1242 0xfe3200000ULL,
1243 -1,
1244 },
1245 .tcx_base = 0x820000000ULL,
1246 .slavio_base = 0xf00000000ULL,
1247 .ms_kb_base = 0xf00240000ULL,
1248 .serial_base = 0xf00200000ULL,
1249 .nvram_base = 0xf00280000ULL,
1250 .counter_base = 0xf00300000ULL,
1251 .espdma_base = 0x800081000ULL,
1252 .esp_base = 0x800080000ULL,
1253 .ledma_base = 0x800040000ULL,
1254 .le_base = 0x800060000ULL,
1255 .sbi_base = 0xf02800000ULL,
1256 .vram_size = 0x00100000,
1257 .nvram_size = 0x2000,
1258 .esp_irq = 3,
1259 .le_irq = 4,
1260 .clock_irq = 14,
1261 .clock1_irq = 10,
1262 .ms_kb_irq = 12,
1263 .ser_irq = 12,
1264 .nvram_machine_id = 0x80,
1265 .machine_id = ss1000_id,
1266 .iounit_version = 0x03000000,
1267 .max_mem = 0xf00000000ULL,
1268 .default_cpu_model = "TI SuperSparc II",
1269 },
1270 /* SS-2000 */
1271 {
1272 .iounit_bases = {
1273 0xfe0200000ULL,
1274 0xfe1200000ULL,
1275 0xfe2200000ULL,
1276 0xfe3200000ULL,
1277 0xfe4200000ULL,
1278 },
1279 .tcx_base = 0x820000000ULL,
1280 .slavio_base = 0xf00000000ULL,
1281 .ms_kb_base = 0xf00240000ULL,
1282 .serial_base = 0xf00200000ULL,
1283 .nvram_base = 0xf00280000ULL,
1284 .counter_base = 0xf00300000ULL,
1285 .espdma_base = 0x800081000ULL,
1286 .esp_base = 0x800080000ULL,
1287 .ledma_base = 0x800040000ULL,
1288 .le_base = 0x800060000ULL,
1289 .sbi_base = 0xf02800000ULL,
1290 .vram_size = 0x00100000,
1291 .nvram_size = 0x2000,
1292 .esp_irq = 3,
1293 .le_irq = 4,
1294 .clock_irq = 14,
1295 .clock1_irq = 10,
1296 .ms_kb_irq = 12,
1297 .ser_irq = 12,
1298 .nvram_machine_id = 0x80,
1299 .machine_id = ss2000_id,
1300 .iounit_version = 0x03000000,
1301 .max_mem = 0xf00000000ULL,
1302 .default_cpu_model = "TI SuperSparc II",
1303 },
1304 };
1305
1306 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1307 const char *boot_device,
1308 const char *kernel_filename,
1309 const char *kernel_cmdline,
1310 const char *initrd_filename, const char *cpu_model)
1311 {
1312 CPUState *envs[MAX_CPUS];
1313 unsigned int i;
1314 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
1315 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1316 espdma_irq, ledma_irq;
1317 qemu_irq *esp_reset, *le_reset;
1318 unsigned long kernel_size;
1319 void *fw_cfg;
1320
1321 /* init CPUs */
1322 if (!cpu_model)
1323 cpu_model = hwdef->default_cpu_model;
1324
1325 for(i = 0; i < smp_cpus; i++) {
1326 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1327 }
1328
1329 for (i = smp_cpus; i < MAX_CPUS; i++)
1330 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1331
1332 /* set up devices */
1333 ram_init(0, RAM_size, hwdef->max_mem);
1334
1335 prom_init(hwdef->slavio_base, bios_name);
1336
1337 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1338
1339 for (i = 0; i < MAX_IOUNITS; i++)
1340 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1341 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1342 hwdef->iounit_version,
1343 sbi_irq[hwdef->me_irq]);
1344
1345 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1346 iounits[0], &espdma_irq, &esp_reset);
1347
1348 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1349 iounits[0], &ledma_irq, &le_reset);
1350
1351 if (graphic_depth != 8 && graphic_depth != 24) {
1352 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1353 exit (1);
1354 }
1355 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1356 graphic_depth);
1357
1358 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1359
1360 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1361 hwdef->nvram_size, 8);
1362
1363 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1364 sbi_cpu_irq, smp_cpus);
1365
1366 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1367 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1368 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1369 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1370 escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1371 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1372
1373 if (drive_get_max_bus(IF_SCSI) > 0) {
1374 fprintf(stderr, "qemu: too many SCSI bus\n");
1375 exit(1);
1376 }
1377
1378 esp_init(hwdef->esp_base, 2,
1379 espdma_memory_read, espdma_memory_write,
1380 espdma, espdma_irq, esp_reset);
1381
1382 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1383 RAM_size);
1384
1385 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1386 boot_device, RAM_size, kernel_size, graphic_width,
1387 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1388 "Sun4d");
1389
1390 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1391 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1392 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1393 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1394 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1395 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1396 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1397 if (kernel_cmdline) {
1398 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1399 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1400 } else {
1401 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1402 }
1403 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1404 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1405 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1406 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1407 }
1408
1409 /* SPARCserver 1000 hardware initialisation */
1410 static void ss1000_init(ram_addr_t RAM_size,
1411 const char *boot_device,
1412 const char *kernel_filename, const char *kernel_cmdline,
1413 const char *initrd_filename, const char *cpu_model)
1414 {
1415 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1416 kernel_cmdline, initrd_filename, cpu_model);
1417 }
1418
1419 /* SPARCcenter 2000 hardware initialisation */
1420 static void ss2000_init(ram_addr_t RAM_size,
1421 const char *boot_device,
1422 const char *kernel_filename, const char *kernel_cmdline,
1423 const char *initrd_filename, const char *cpu_model)
1424 {
1425 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1426 kernel_cmdline, initrd_filename, cpu_model);
1427 }
1428
1429 static QEMUMachine ss1000_machine = {
1430 .name = "SS-1000",
1431 .desc = "Sun4d platform, SPARCserver 1000",
1432 .init = ss1000_init,
1433 .use_scsi = 1,
1434 .max_cpus = 8,
1435 };
1436
1437 static QEMUMachine ss2000_machine = {
1438 .name = "SS-2000",
1439 .desc = "Sun4d platform, SPARCcenter 2000",
1440 .init = ss2000_init,
1441 .use_scsi = 1,
1442 .max_cpus = 20,
1443 };
1444
1445 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1446 /* SS-2 */
1447 {
1448 .iommu_base = 0xf8000000,
1449 .tcx_base = 0xfe000000,
1450 .slavio_base = 0xf6000000,
1451 .intctl_base = 0xf5000000,
1452 .counter_base = 0xf3000000,
1453 .ms_kb_base = 0xf0000000,
1454 .serial_base = 0xf1000000,
1455 .nvram_base = 0xf2000000,
1456 .fd_base = 0xf7200000,
1457 .dma_base = 0xf8400000,
1458 .esp_base = 0xf8800000,
1459 .le_base = 0xf8c00000,
1460 .aux1_base = 0xf7400003,
1461 .vram_size = 0x00100000,
1462 .nvram_size = 0x800,
1463 .esp_irq = 2,
1464 .le_irq = 3,
1465 .clock_irq = 5,
1466 .clock1_irq = 7,
1467 .ms_kb_irq = 1,
1468 .ser_irq = 1,
1469 .fd_irq = 1,
1470 .me_irq = 1,
1471 .nvram_machine_id = 0x55,
1472 .machine_id = ss2_id,
1473 .max_mem = 0x10000000,
1474 .default_cpu_model = "Cypress CY7C601",
1475 },
1476 };
1477
1478 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1479 const char *boot_device,
1480 const char *kernel_filename,
1481 const char *kernel_cmdline,
1482 const char *initrd_filename, const char *cpu_model)
1483 {
1484 CPUState *env;
1485 void *iommu, *espdma, *ledma, *nvram;
1486 qemu_irq *cpu_irqs, *slavio_irq, espdma_irq, ledma_irq;
1487 qemu_irq *esp_reset, *le_reset;
1488 qemu_irq fdc_tc;
1489 unsigned long kernel_size;
1490 BlockDriverState *fd[MAX_FD];
1491 int drive_index;
1492 void *fw_cfg;
1493
1494 /* init CPU */
1495 if (!cpu_model)
1496 cpu_model = hwdef->default_cpu_model;
1497
1498 env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1499
1500 /* set up devices */
1501 ram_init(0, RAM_size, hwdef->max_mem);
1502
1503 prom_init(hwdef->slavio_base, bios_name);
1504
1505 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1506 &slavio_irq, cpu_irqs);
1507
1508 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1509 slavio_irq[hwdef->me_irq]);
1510
1511 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1512 iommu, &espdma_irq, &esp_reset);
1513
1514 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1515 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1516 &le_reset);
1517
1518 if (graphic_depth != 8 && graphic_depth != 24) {
1519 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1520 exit (1);
1521 }
1522 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1523 graphic_depth);
1524
1525 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1526
1527 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1528 hwdef->nvram_size, 2);
1529
1530 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1531 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1532 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1533 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1534 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1535 slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1536 ESCC_CLOCK, 1);
1537
1538 slavio_misc = slavio_misc_init(0, hwdef->aux1_base, 0,
1539 slavio_irq[hwdef->me_irq], fdc_tc);
1540
1541 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1542 /* there is zero or one floppy drive */
1543 memset(fd, 0, sizeof(fd));
1544 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1545 if (drive_index != -1)
1546 fd[0] = drives_table[drive_index].bdrv;
1547
1548 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1549 &fdc_tc);
1550 }
1551
1552 if (drive_get_max_bus(IF_SCSI) > 0) {
1553 fprintf(stderr, "qemu: too many SCSI bus\n");
1554 exit(1);
1555 }
1556
1557 esp_init(hwdef->esp_base, 2,
1558 espdma_memory_read, espdma_memory_write,
1559 espdma, espdma_irq, esp_reset);
1560
1561 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1562 RAM_size);
1563
1564 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1565 boot_device, RAM_size, kernel_size, graphic_width,
1566 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1567 "Sun4c");
1568
1569 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1570 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1571 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1572 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1573 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1574 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1575 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1576 if (kernel_cmdline) {
1577 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1578 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1579 } else {
1580 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1581 }
1582 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1583 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1584 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1585 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1586 }
1587
1588 /* SPARCstation 2 hardware initialisation */
1589 static void ss2_init(ram_addr_t RAM_size,
1590 const char *boot_device,
1591 const char *kernel_filename, const char *kernel_cmdline,
1592 const char *initrd_filename, const char *cpu_model)
1593 {
1594 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1595 kernel_cmdline, initrd_filename, cpu_model);
1596 }
1597
1598 static QEMUMachine ss2_machine = {
1599 .name = "SS-2",
1600 .desc = "Sun4c platform, SPARCstation 2",
1601 .init = ss2_init,
1602 .use_scsi = 1,
1603 };
1604
1605 static void ss2_machine_init(void)
1606 {
1607 qemu_register_machine(&ss5_machine);
1608 qemu_register_machine(&ss10_machine);
1609 qemu_register_machine(&ss600mp_machine);
1610 qemu_register_machine(&ss20_machine);
1611 qemu_register_machine(&voyager_machine);
1612 qemu_register_machine(&ss_lx_machine);
1613 qemu_register_machine(&ss4_machine);
1614 qemu_register_machine(&scls_machine);
1615 qemu_register_machine(&sbook_machine);
1616 qemu_register_machine(&ss1000_machine);
1617 qemu_register_machine(&ss2000_machine);
1618 qemu_register_machine(&ss2_machine);
1619 }
1620
1621 machine_init(ss2_machine_init);
Adding pft support to QEMU's arm cpus