hw/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sun4m.h"
  26 #include "monitor.h"
  27 #include "sysbus.h"
  28
  29 //#define DEBUG_IRQ_COUNT
  30 //#define DEBUG_IRQ
  31
  32 #ifdef DEBUG_IRQ
  33 #define DPRINTF(fmt, ...)                                       \
  34     do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define DPRINTF(fmt, ...)
  37 #endif
  38
  39 /*
  40  * Registers of interrupt controller in sun4m.
  41  *
  42  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  43  * produced as NCR89C105. See
  44  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  45  *
  46  * There is a system master controller and one for each cpu.
  47  *
  48  */
  49
  50 #define MAX_CPUS 16
  51 #define MAX_PILS 16
  52
  53 struct SLAVIO_INTCTLState;
  54
  55 typedef struct SLAVIO_CPUINTCTLState {
  56     uint32_t intreg_pending;
  57     struct SLAVIO_INTCTLState *master;
  58     uint32_t cpu;
  59 } SLAVIO_CPUINTCTLState;
  60
  61 typedef struct SLAVIO_INTCTLState {
  62     SysBusDevice busdev;
  63     uint32_t intregm_pending;
  64     uint32_t intregm_disabled;
  65     uint32_t target_cpu;
  66 #ifdef DEBUG_IRQ_COUNT
  67     uint64_t irq_count[32];
  68 #endif
  69     qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
  70     const uint32_t *intbit_to_level;
  71     uint32_t cputimer_lbit, cputimer_mbit;
  72     uint32_t pil_out[MAX_CPUS];
  73     SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
  74 } SLAVIO_INTCTLState;
  75
  76 #define INTCTL_MAXADDR 0xf
  77 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  78 #define INTCTLM_SIZE 0x14
  79 #define MASTER_IRQ_MASK ~0x0fa2007f
  80 #define MASTER_DISABLE 0x80000000
  81 #define CPU_SOFTIRQ_MASK 0xfffe0000
  82 #define CPU_IRQ_INT15_IN 0x0004000
  83 #define CPU_IRQ_INT15_MASK 0x80000000
  84
  85 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
  86
  87 // per-cpu interrupt controller
  88 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
  89 {
  90     SLAVIO_CPUINTCTLState *s = opaque;
  91     uint32_t saddr, ret;
  92
  93     saddr = addr >> 2;
  94     switch (saddr) {
  95     case 0:
  96         ret = s->intreg_pending;
  97         break;
  98     default:
  99         ret = 0;
 100         break;
 101     }
 102     DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
 103
 104     return ret;
 105 }
 106
 107 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
 108                                      uint32_t val)
 109 {
 110     SLAVIO_CPUINTCTLState *s = opaque;
 111     uint32_t saddr;
 112
 113     saddr = addr >> 2;
 114     DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
 115     switch (saddr) {
 116     case 1: // clear pending softints
 117         if (val & CPU_IRQ_INT15_IN)
 118             val |= CPU_IRQ_INT15_MASK;
 119         val &= CPU_SOFTIRQ_MASK;
 120         s->intreg_pending &= ~val;
 121         slavio_check_interrupts(s->master, 1);
 122         DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
 123                 s->intreg_pending);
 124         break;
 125     case 2: // set softint
 126         val &= CPU_SOFTIRQ_MASK;
 127         s->intreg_pending |= val;
 128         slavio_check_interrupts(s->master, 1);
 129         DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
 130                 s->intreg_pending);
 131         break;
 132     default:
 133         break;
 134     }
 135 }
 136
 137 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
 138     NULL,
 139     NULL,
 140     slavio_intctl_mem_readl,
 141 };
 142
 143 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
 144     NULL,
 145     NULL,
 146     slavio_intctl_mem_writel,
 147 };
 148
 149 // master system interrupt controller
 150 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
 151 {
 152     SLAVIO_INTCTLState *s = opaque;
 153     uint32_t saddr, ret;
 154
 155     saddr = addr >> 2;
 156     switch (saddr) {
 157     case 0:
 158         ret = s->intregm_pending & ~MASTER_DISABLE;
 159         break;
 160     case 1:
 161         ret = s->intregm_disabled & MASTER_IRQ_MASK;
 162         break;
 163     case 4:
 164         ret = s->target_cpu;
 165         break;
 166     default:
 167         ret = 0;
 168         break;
 169     }
 170     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
 171
 172     return ret;
 173 }
 174
 175 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
 176                                       uint32_t val)
 177 {
 178     SLAVIO_INTCTLState *s = opaque;
 179     uint32_t saddr;
 180
 181     saddr = addr >> 2;
 182     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
 183     switch (saddr) {
 184     case 2: // clear (enable)
 185         // Force clear unused bits
 186         val &= MASTER_IRQ_MASK;
 187         s->intregm_disabled &= ~val;
 188         DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
 189                 s->intregm_disabled);
 190         slavio_check_interrupts(s, 1);
 191         break;
 192     case 3: // set (disable, clear pending)
 193         // Force clear unused bits
 194         val &= MASTER_IRQ_MASK;
 195         s->intregm_disabled |= val;
 196         s->intregm_pending &= ~val;
 197         slavio_check_interrupts(s, 1);
 198         DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
 199                 s->intregm_disabled);
 200         break;
 201     case 4:
 202         s->target_cpu = val & (MAX_CPUS - 1);
 203         slavio_check_interrupts(s, 1);
 204         DPRINTF("Set master irq cpu %d\n", s->target_cpu);
 205         break;
 206     default:
 207         break;
 208     }
 209 }
 210
 211 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
 212     NULL,
 213     NULL,
 214     slavio_intctlm_mem_readl,
 215 };
 216
 217 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
 218     NULL,
 219     NULL,
 220     slavio_intctlm_mem_writel,
 221 };
 222
 223 void slavio_pic_info(Monitor *mon, void *opaque)
 224 {
 225     SLAVIO_INTCTLState *s = opaque;
 226     int i;
 227
 228     for (i = 0; i < MAX_CPUS; i++) {
 229         monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
 230                        s->slaves[i].intreg_pending);
 231     }
 232     monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
 233                    s->intregm_pending, s->intregm_disabled);
 234 }
 235
 236 void slavio_irq_info(Monitor *mon, void *opaque)
 237 {
 238 #ifndef DEBUG_IRQ_COUNT
 239     monitor_printf(mon, "irq statistic code not compiled.\n");
 240 #else
 241     SLAVIO_INTCTLState *s = opaque;
 242     int i;
 243     int64_t count;
 244
 245     monitor_printf(mon, "IRQ statistics:\n");
 246     for (i = 0; i < 32; i++) {
 247         count = s->irq_count[i];
 248         if (count > 0)
 249             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 250     }
 251 #endif
 252 }
 253
 254 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
 255 {
 256     uint32_t pending = s->intregm_pending, pil_pending;
 257     unsigned int i, j;
 258
 259     pending &= ~s->intregm_disabled;
 260
 261     DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
 262     for (i = 0; i < MAX_CPUS; i++) {
 263         pil_pending = 0;
 264         if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
 265             (i == s->target_cpu)) {
 266             for (j = 0; j < 32; j++) {
 267                 if (pending & (1 << j))
 268                     pil_pending |= 1 << s->intbit_to_level[j];
 269             }
 270         }
 271         pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
 272
 273         if (set_irqs) {
 274             for (j = 0; j < MAX_PILS; j++) {
 275                 if (pil_pending & (1 << j)) {
 276                     if (!(s->pil_out[i] & (1 << j))) {
 277                         qemu_irq_raise(s->cpu_irqs[i][j]);
 278                     }
 279                 } else {
 280                     if (s->pil_out[i] & (1 << j)) {
 281                         qemu_irq_lower(s->cpu_irqs[i][j]);
 282                     }
 283                 }
 284             }
 285         }
 286         s->pil_out[i] = pil_pending;
 287     }
 288 }
 289
 290 /*
 291  * "irq" here is the bit number in the system interrupt register to
 292  * separate serial and keyboard interrupts sharing a level.
 293  */
 294 static void slavio_set_irq(void *opaque, int irq, int level)
 295 {
 296     SLAVIO_INTCTLState *s = opaque;
 297     uint32_t mask = 1 << irq;
 298     uint32_t pil = s->intbit_to_level[irq];
 299
 300     DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
 301             level);
 302     if (pil > 0) {
 303         if (level) {
 304 #ifdef DEBUG_IRQ_COUNT
 305             s->irq_count[pil]++;
 306 #endif
 307             s->intregm_pending |= mask;
 308             s->slaves[s->target_cpu].intreg_pending |= 1 << pil;
 309         } else {
 310             s->intregm_pending &= ~mask;
 311             s->slaves[s->target_cpu].intreg_pending &= ~(1 << pil);
 312         }
 313         slavio_check_interrupts(s, 1);
 314     }
 315 }
 316
 317 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
 318 {
 319     SLAVIO_INTCTLState *s = opaque;
 320
 321     DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
 322
 323     if (level) {
 324         s->intregm_pending |= s->cputimer_mbit;
 325         s->slaves[cpu].intreg_pending |= s->cputimer_lbit;
 326     } else {
 327         s->intregm_pending &= ~s->cputimer_mbit;
 328         s->slaves[cpu].intreg_pending &= ~s->cputimer_lbit;
 329     }
 330
 331     slavio_check_interrupts(s, 1);
 332 }
 333
 334 static void slavio_set_irq_all(void *opaque, int irq, int level)
 335 {
 336     if (irq < 32) {
 337         slavio_set_irq(opaque, irq, level);
 338     } else {
 339         slavio_set_timer_irq_cpu(opaque, irq - 32, level);
 340     }
 341 }
 342
 343 static void slavio_intctl_save(QEMUFile *f, void *opaque)
 344 {
 345     SLAVIO_INTCTLState *s = opaque;
 346     int i;
 347
 348     for (i = 0; i < MAX_CPUS; i++) {
 349         qemu_put_be32s(f, &s->slaves[i].intreg_pending);
 350     }
 351     qemu_put_be32s(f, &s->intregm_pending);
 352     qemu_put_be32s(f, &s->intregm_disabled);
 353     qemu_put_be32s(f, &s->target_cpu);
 354 }
 355
 356 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
 357 {
 358     SLAVIO_INTCTLState *s = opaque;
 359     int i;
 360
 361     if (version_id != 1)
 362         return -EINVAL;
 363
 364     for (i = 0; i < MAX_CPUS; i++) {
 365         qemu_get_be32s(f, &s->slaves[i].intreg_pending);
 366     }
 367     qemu_get_be32s(f, &s->intregm_pending);
 368     qemu_get_be32s(f, &s->intregm_disabled);
 369     qemu_get_be32s(f, &s->target_cpu);
 370     slavio_check_interrupts(s, 0);
 371     return 0;
 372 }
 373
 374 static void slavio_intctl_reset(void *opaque)
 375 {
 376     SLAVIO_INTCTLState *s = opaque;
 377     int i;
 378
 379     for (i = 0; i < MAX_CPUS; i++) {
 380         s->slaves[i].intreg_pending = 0;
 381     }
 382     s->intregm_disabled = ~MASTER_IRQ_MASK;
 383     s->intregm_pending = 0;
 384     s->target_cpu = 0;
 385     slavio_check_interrupts(s, 0);
 386 }
 387
 388 static void slavio_intctl_init1(SysBusDevice *dev)
 389 {
 390     SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
 391     int io_memory, cputimer;
 392     unsigned int i, j;
 393
 394     qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
 395     io_memory = cpu_register_io_memory(slavio_intctlm_mem_read,
 396                                        slavio_intctlm_mem_write, s);
 397     sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory);
 398     s->intbit_to_level = qdev_get_prop_ptr(&dev->qdev, "intbit_to_level");
 399     cputimer = qdev_get_prop_int(&dev->qdev, "cputimer_bit", -1);
 400     s->cputimer_mbit = 1 << cputimer;
 401     s->cputimer_lbit = 1 << s->intbit_to_level[cputimer];
 402
 403     for (i = 0; i < MAX_CPUS; i++) {
 404         for (j = 0; j < MAX_PILS; j++) {
 405             sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
 406         }
 407         io_memory = cpu_register_io_memory(slavio_intctl_mem_read,
 408                                            slavio_intctl_mem_write,
 409                                            &s->slaves[i]);
 410         sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
 411         s->slaves[i].cpu = i;
 412         s->slaves[i].master = s;
 413     }
 414     register_savevm("slavio_intctl", -1, 1, slavio_intctl_save,
 415                     slavio_intctl_load, s);
 416     qemu_register_reset(slavio_intctl_reset, s);
 417     slavio_intctl_reset(s);
 418 }
 419
 420 DeviceState *slavio_intctl_init(target_phys_addr_t addr,
 421                                 target_phys_addr_t addrg,
 422                                 const uint32_t *intbit_to_level,
 423                                 qemu_irq **parent_irq, unsigned int cputimer)
 424 {
 425     DeviceState *dev;
 426     SysBusDevice *s;
 427     unsigned int i, j;
 428
 429     dev = qdev_create(NULL, "slavio_intctl");
 430     qdev_set_prop_ptr(dev, "intbit_to_level", (void *)intbit_to_level);
 431     qdev_set_prop_int(dev, "cputimer_bit", cputimer);
 432     qdev_init(dev);
 433
 434     s = sysbus_from_qdev(dev);
 435
 436     for (i = 0; i < MAX_CPUS; i++) {
 437         for (j = 0; j < MAX_PILS; j++) {
 438             sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
 439         }
 440     }
 441     sysbus_mmio_map(s, 0, addrg);
 442     for (i = 0; i < MAX_CPUS; i++) {
 443         sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
 444     }
 445
 446     return dev;
 447 }
 448
 449 static SysBusDeviceInfo slavio_intctl_info = {
 450     .init = slavio_intctl_init1,
 451     .qdev.name  = "slavio_intctl",
 452     .qdev.size  = sizeof(SLAVIO_INTCTLState),
 453     .qdev.props = (DevicePropList[]) {
 454         {.name = "intbit_to_level", .type = PROP_TYPE_PTR},
 455         {.name = "cputimer_bit", .type = PROP_TYPE_INT},
 456         {.name = NULL}
 457     }
 458 };
 459
 460 static void slavio_intctl_register_devices(void)
 461 {
 462     sysbus_register_withprop(&slavio_intctl_info);
 463 }
 464
 465 device_init(slavio_intctl_register_devices)