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qemu-io: Implement bdrv_load_vmstate/bdrv_save_vmstate
[armpft.git] / hw / fdc.c
blob3959b112ef98dd09b95637919c7546532e861750
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "block.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36
37 /********************************************************/
38 /* debug Floppy devices */
39 //#define DEBUG_FLOPPY
40
41 #ifdef DEBUG_FLOPPY
42 #define FLOPPY_DPRINTF(fmt, ...) \
43 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
44 #else
45 #define FLOPPY_DPRINTF(fmt, ...)
46 #endif
47
48 #define FLOPPY_ERROR(fmt, ...) \
49 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
50
51 /********************************************************/
52 /* Floppy drive emulation */
53
54 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
55 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
56
57 /* Will always be a fixed parameter for us */
58 #define FD_SECTOR_LEN 512
59 #define FD_SECTOR_SC 2 /* Sector size code */
60 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
61
62 /* Floppy disk drive emulation */
63 typedef enum fdisk_type_t {
64 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
65 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
66 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
67 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
68 FDRIVE_DISK_NONE = 0x05, /* No disk */
69 } fdisk_type_t;
70
71 typedef enum fdrive_type_t {
72 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
73 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
74 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
75 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
76 } fdrive_type_t;
77
78 typedef enum fdisk_flags_t {
79 FDISK_DBL_SIDES = 0x01,
80 } fdisk_flags_t;
81
82 typedef struct fdrive_t {
83 BlockDriverState *bs;
84 /* Drive status */
85 fdrive_type_t drive;
86 uint8_t perpendicular; /* 2.88 MB access mode */
87 /* Position */
88 uint8_t head;
89 uint8_t track;
90 uint8_t sect;
91 /* Media */
92 fdisk_flags_t flags;
93 uint8_t last_sect; /* Nb sector per track */
94 uint8_t max_track; /* Nb of tracks */
95 uint16_t bps; /* Bytes per sector */
96 uint8_t ro; /* Is read-only */
97 } fdrive_t;
98
99 static void fd_init (fdrive_t *drv, BlockDriverState *bs)
100 {
101 /* Drive */
102 drv->bs = bs;
103 drv->drive = FDRIVE_DRV_NONE;
104 drv->perpendicular = 0;
105 /* Disk */
106 drv->last_sect = 0;
107 drv->max_track = 0;
108 }
109
110 static int _fd_sector (uint8_t head, uint8_t track,
111 uint8_t sect, uint8_t last_sect)
112 {
113 return (((track * 2) + head) * last_sect) + sect - 1;
114 }
115
116 /* Returns current position, in sectors, for given drive */
117 static int fd_sector (fdrive_t *drv)
118 {
119 return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
120 }
121
122 /* Seek to a new position:
123 * returns 0 if already on right track
124 * returns 1 if track changed
125 * returns 2 if track is invalid
126 * returns 3 if sector is invalid
127 * returns 4 if seek is disabled
128 */
129 static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
130 int enable_seek)
131 {
132 uint32_t sector;
133 int ret;
134
135 if (track > drv->max_track ||
136 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
137 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
138 head, track, sect, 1,
139 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
140 drv->max_track, drv->last_sect);
141 return 2;
142 }
143 if (sect > drv->last_sect) {
144 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
145 head, track, sect, 1,
146 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
147 drv->max_track, drv->last_sect);
148 return 3;
149 }
150 sector = _fd_sector(head, track, sect, drv->last_sect);
151 ret = 0;
152 if (sector != fd_sector(drv)) {
153 #if 0
154 if (!enable_seek) {
155 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
156 head, track, sect, 1, drv->max_track, drv->last_sect);
157 return 4;
158 }
159 #endif
160 drv->head = head;
161 if (drv->track != track)
162 ret = 1;
163 drv->track = track;
164 drv->sect = sect;
165 }
166
167 return ret;
168 }
169
170 /* Set drive back to track 0 */
171 static void fd_recalibrate (fdrive_t *drv)
172 {
173 FLOPPY_DPRINTF("recalibrate\n");
174 drv->head = 0;
175 drv->track = 0;
176 drv->sect = 1;
177 }
178
179 /* Recognize floppy formats */
180 typedef struct fd_format_t {
181 fdrive_type_t drive;
182 fdisk_type_t disk;
183 uint8_t last_sect;
184 uint8_t max_track;
185 uint8_t max_head;
186 const char *str;
187 } fd_format_t;
188
189 static const fd_format_t fd_formats[] = {
190 /* First entry is default format */
191 /* 1.44 MB 3"1/2 floppy disks */
192 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
193 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
197 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
198 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
199 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
200 /* 2.88 MB 3"1/2 floppy disks */
201 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
202 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
203 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
204 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
205 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
206 /* 720 kB 3"1/2 floppy disks */
207 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
208 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
210 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
211 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
212 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
213 /* 1.2 MB 5"1/4 floppy disks */
214 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
215 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
216 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
219 /* 720 kB 5"1/4 floppy disks */
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
221 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
222 /* 360 kB 5"1/4 floppy disks */
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
224 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
227 /* 320 kB 5"1/4 floppy disks */
228 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
229 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
230 /* 360 kB must match 5"1/4 better than 3"1/2... */
231 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
232 /* end */
233 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
234 };
235
236 /* Revalidate a disk drive after a disk change */
237 static void fd_revalidate (fdrive_t *drv)
238 {
239 const fd_format_t *parse;
240 uint64_t nb_sectors, size;
241 int i, first_match, match;
242 int nb_heads, max_track, last_sect, ro;
243
244 FLOPPY_DPRINTF("revalidate\n");
245 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
246 ro = bdrv_is_read_only(drv->bs);
247 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
248 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
249 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
250 nb_heads - 1, max_track, last_sect);
251 } else {
252 bdrv_get_geometry(drv->bs, &nb_sectors);
253 match = -1;
254 first_match = -1;
255 for (i = 0;; i++) {
256 parse = &fd_formats[i];
257 if (parse->drive == FDRIVE_DRV_NONE)
258 break;
259 if (drv->drive == parse->drive ||
260 drv->drive == FDRIVE_DRV_NONE) {
261 size = (parse->max_head + 1) * parse->max_track *
262 parse->last_sect;
263 if (nb_sectors == size) {
264 match = i;
265 break;
266 }
267 if (first_match == -1)
268 first_match = i;
269 }
270 }
271 if (match == -1) {
272 if (first_match == -1)
273 match = 1;
274 else
275 match = first_match;
276 parse = &fd_formats[match];
277 }
278 nb_heads = parse->max_head + 1;
279 max_track = parse->max_track;
280 last_sect = parse->last_sect;
281 drv->drive = parse->drive;
282 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
283 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
284 }
285 if (nb_heads == 1) {
286 drv->flags &= ~FDISK_DBL_SIDES;
287 } else {
288 drv->flags |= FDISK_DBL_SIDES;
289 }
290 drv->max_track = max_track;
291 drv->last_sect = last_sect;
292 drv->ro = ro;
293 } else {
294 FLOPPY_DPRINTF("No disk in drive\n");
295 drv->last_sect = 0;
296 drv->max_track = 0;
297 drv->flags &= ~FDISK_DBL_SIDES;
298 }
299 }
300
301 /********************************************************/
302 /* Intel 82078 floppy disk controller emulation */
303
304 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
305 static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
306 static int fdctrl_transfer_handler (void *opaque, int nchan,
307 int dma_pos, int dma_len);
308 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
309
310 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
311 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
312 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
313 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
314 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
315 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
316 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
317 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
318 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
319 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
320 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
321
322 enum {
323 FD_DIR_WRITE = 0,
324 FD_DIR_READ = 1,
325 FD_DIR_SCANE = 2,
326 FD_DIR_SCANL = 3,
327 FD_DIR_SCANH = 4,
328 };
329
330 enum {
331 FD_STATE_MULTI = 0x01, /* multi track flag */
332 FD_STATE_FORMAT = 0x02, /* format flag */
333 FD_STATE_SEEK = 0x04, /* seek flag */
334 };
335
336 enum {
337 FD_REG_SRA = 0x00,
338 FD_REG_SRB = 0x01,
339 FD_REG_DOR = 0x02,
340 FD_REG_TDR = 0x03,
341 FD_REG_MSR = 0x04,
342 FD_REG_DSR = 0x04,
343 FD_REG_FIFO = 0x05,
344 FD_REG_DIR = 0x07,
345 };
346
347 enum {
348 FD_CMD_READ_TRACK = 0x02,
349 FD_CMD_SPECIFY = 0x03,
350 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
351 FD_CMD_WRITE = 0x05,
352 FD_CMD_READ = 0x06,
353 FD_CMD_RECALIBRATE = 0x07,
354 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
355 FD_CMD_WRITE_DELETED = 0x09,
356 FD_CMD_READ_ID = 0x0a,
357 FD_CMD_READ_DELETED = 0x0c,
358 FD_CMD_FORMAT_TRACK = 0x0d,
359 FD_CMD_DUMPREG = 0x0e,
360 FD_CMD_SEEK = 0x0f,
361 FD_CMD_VERSION = 0x10,
362 FD_CMD_SCAN_EQUAL = 0x11,
363 FD_CMD_PERPENDICULAR_MODE = 0x12,
364 FD_CMD_CONFIGURE = 0x13,
365 FD_CMD_LOCK = 0x14,
366 FD_CMD_VERIFY = 0x16,
367 FD_CMD_POWERDOWN_MODE = 0x17,
368 FD_CMD_PART_ID = 0x18,
369 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
370 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
371 FD_CMD_SAVE = 0x2c,
372 FD_CMD_OPTION = 0x33,
373 FD_CMD_RESTORE = 0x4c,
374 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
375 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
376 FD_CMD_FORMAT_AND_WRITE = 0xcd,
377 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
378 };
379
380 enum {
381 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
382 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
383 FD_CONFIG_POLL = 0x10, /* Poll enabled */
384 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
385 FD_CONFIG_EIS = 0x40, /* No implied seeks */
386 };
387
388 enum {
389 FD_SR0_EQPMT = 0x10,
390 FD_SR0_SEEK = 0x20,
391 FD_SR0_ABNTERM = 0x40,
392 FD_SR0_INVCMD = 0x80,
393 FD_SR0_RDYCHG = 0xc0,
394 };
395
396 enum {
397 FD_SR1_EC = 0x80, /* End of cylinder */
398 };
399
400 enum {
401 FD_SR2_SNS = 0x04, /* Scan not satisfied */
402 FD_SR2_SEH = 0x08, /* Scan equal hit */
403 };
404
405 enum {
406 FD_SRA_DIR = 0x01,
407 FD_SRA_nWP = 0x02,
408 FD_SRA_nINDX = 0x04,
409 FD_SRA_HDSEL = 0x08,
410 FD_SRA_nTRK0 = 0x10,
411 FD_SRA_STEP = 0x20,
412 FD_SRA_nDRV2 = 0x40,
413 FD_SRA_INTPEND = 0x80,
414 };
415
416 enum {
417 FD_SRB_MTR0 = 0x01,
418 FD_SRB_MTR1 = 0x02,
419 FD_SRB_WGATE = 0x04,
420 FD_SRB_RDATA = 0x08,
421 FD_SRB_WDATA = 0x10,
422 FD_SRB_DR0 = 0x20,
423 };
424
425 enum {
426 #if MAX_FD == 4
427 FD_DOR_SELMASK = 0x03,
428 #else
429 FD_DOR_SELMASK = 0x01,
430 #endif
431 FD_DOR_nRESET = 0x04,
432 FD_DOR_DMAEN = 0x08,
433 FD_DOR_MOTEN0 = 0x10,
434 FD_DOR_MOTEN1 = 0x20,
435 FD_DOR_MOTEN2 = 0x40,
436 FD_DOR_MOTEN3 = 0x80,
437 };
438
439 enum {
440 #if MAX_FD == 4
441 FD_TDR_BOOTSEL = 0x0c,
442 #else
443 FD_TDR_BOOTSEL = 0x04,
444 #endif
445 };
446
447 enum {
448 FD_DSR_DRATEMASK= 0x03,
449 FD_DSR_PWRDOWN = 0x40,
450 FD_DSR_SWRESET = 0x80,
451 };
452
453 enum {
454 FD_MSR_DRV0BUSY = 0x01,
455 FD_MSR_DRV1BUSY = 0x02,
456 FD_MSR_DRV2BUSY = 0x04,
457 FD_MSR_DRV3BUSY = 0x08,
458 FD_MSR_CMDBUSY = 0x10,
459 FD_MSR_NONDMA = 0x20,
460 FD_MSR_DIO = 0x40,
461 FD_MSR_RQM = 0x80,
462 };
463
464 enum {
465 FD_DIR_DSKCHG = 0x80,
466 };
467
468 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
469 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
470 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
471
472 struct fdctrl_t {
473 SysBusDevice busdev;
474 /* Controller's identification */
475 uint8_t version;
476 /* HW */
477 qemu_irq irq;
478 int dma_chann;
479 target_phys_addr_t io_base;
480 /* Controller state */
481 QEMUTimer *result_timer;
482 uint8_t sra;
483 uint8_t srb;
484 uint8_t dor;
485 uint8_t tdr;
486 uint8_t dsr;
487 uint8_t msr;
488 uint8_t cur_drv;
489 uint8_t status0;
490 uint8_t status1;
491 uint8_t status2;
492 /* Command FIFO */
493 uint8_t *fifo;
494 uint32_t data_pos;
495 uint32_t data_len;
496 uint8_t data_state;
497 uint8_t data_dir;
498 uint8_t eot; /* last wanted sector */
499 /* States kept only to be returned back */
500 /* Timers state */
501 uint8_t timer0;
502 uint8_t timer1;
503 /* precompensation */
504 uint8_t precomp_trk;
505 uint8_t config;
506 uint8_t lock;
507 /* Power down config (also with status regB access mode */
508 uint8_t pwrd;
509 /* Sun4m quirks? */
510 int sun4m;
511 /* Floppy drives */
512 fdrive_t drives[MAX_FD];
513 int reset_sensei;
514 };
515
516 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
517 {
518 fdctrl_t *fdctrl = opaque;
519 uint32_t retval;
520
521 switch (reg) {
522 case FD_REG_SRA:
523 retval = fdctrl_read_statusA(fdctrl);
524 break;
525 case FD_REG_SRB:
526 retval = fdctrl_read_statusB(fdctrl);
527 break;
528 case FD_REG_DOR:
529 retval = fdctrl_read_dor(fdctrl);
530 break;
531 case FD_REG_TDR:
532 retval = fdctrl_read_tape(fdctrl);
533 break;
534 case FD_REG_MSR:
535 retval = fdctrl_read_main_status(fdctrl);
536 break;
537 case FD_REG_FIFO:
538 retval = fdctrl_read_data(fdctrl);
539 break;
540 case FD_REG_DIR:
541 retval = fdctrl_read_dir(fdctrl);
542 break;
543 default:
544 retval = (uint32_t)(-1);
545 break;
546 }
547 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
548
549 return retval;
550 }
551
552 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
553 {
554 fdctrl_t *fdctrl = opaque;
555
556 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
557
558 switch (reg) {
559 case FD_REG_DOR:
560 fdctrl_write_dor(fdctrl, value);
561 break;
562 case FD_REG_TDR:
563 fdctrl_write_tape(fdctrl, value);
564 break;
565 case FD_REG_DSR:
566 fdctrl_write_rate(fdctrl, value);
567 break;
568 case FD_REG_FIFO:
569 fdctrl_write_data(fdctrl, value);
570 break;
571 default:
572 break;
573 }
574 }
575
576 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
577 {
578 return fdctrl_read(opaque, reg & 7);
579 }
580
581 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
582 {
583 fdctrl_write(opaque, reg & 7, value);
584 }
585
586 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
587 {
588 return fdctrl_read(opaque, (uint32_t)reg);
589 }
590
591 static void fdctrl_write_mem (void *opaque,
592 target_phys_addr_t reg, uint32_t value)
593 {
594 fdctrl_write(opaque, (uint32_t)reg, value);
595 }
596
597 static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
598 fdctrl_read_mem,
599 fdctrl_read_mem,
600 fdctrl_read_mem,
601 };
602
603 static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
604 fdctrl_write_mem,
605 fdctrl_write_mem,
606 fdctrl_write_mem,
607 };
608
609 static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
610 fdctrl_read_mem,
611 NULL,
612 NULL,
613 };
614
615 static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
616 fdctrl_write_mem,
617 NULL,
618 NULL,
619 };
620
621 static void fd_save (QEMUFile *f, fdrive_t *fd)
622 {
623 qemu_put_8s(f, &fd->head);
624 qemu_put_8s(f, &fd->track);
625 qemu_put_8s(f, &fd->sect);
626 }
627
628 static void fdc_save (QEMUFile *f, void *opaque)
629 {
630 fdctrl_t *s = opaque;
631 uint8_t tmp;
632 int i;
633 uint8_t dor = s->dor | GET_CUR_DRV(s);
634
635 /* Controller state */
636 qemu_put_8s(f, &s->sra);
637 qemu_put_8s(f, &s->srb);
638 qemu_put_8s(f, &dor);
639 qemu_put_8s(f, &s->tdr);
640 qemu_put_8s(f, &s->dsr);
641 qemu_put_8s(f, &s->msr);
642 qemu_put_8s(f, &s->status0);
643 qemu_put_8s(f, &s->status1);
644 qemu_put_8s(f, &s->status2);
645 /* Command FIFO */
646 qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
647 qemu_put_be32s(f, &s->data_pos);
648 qemu_put_be32s(f, &s->data_len);
649 qemu_put_8s(f, &s->data_state);
650 qemu_put_8s(f, &s->data_dir);
651 qemu_put_8s(f, &s->eot);
652 /* States kept only to be returned back */
653 qemu_put_8s(f, &s->timer0);
654 qemu_put_8s(f, &s->timer1);
655 qemu_put_8s(f, &s->precomp_trk);
656 qemu_put_8s(f, &s->config);
657 qemu_put_8s(f, &s->lock);
658 qemu_put_8s(f, &s->pwrd);
659
660 tmp = MAX_FD;
661 qemu_put_8s(f, &tmp);
662 for (i = 0; i < MAX_FD; i++)
663 fd_save(f, &s->drives[i]);
664 }
665
666 static int fd_load (QEMUFile *f, fdrive_t *fd)
667 {
668 qemu_get_8s(f, &fd->head);
669 qemu_get_8s(f, &fd->track);
670 qemu_get_8s(f, &fd->sect);
671
672 return 0;
673 }
674
675 static int fdc_load (QEMUFile *f, void *opaque, int version_id)
676 {
677 fdctrl_t *s = opaque;
678 int i, ret = 0;
679 uint8_t n;
680
681 if (version_id != 2)
682 return -EINVAL;
683
684 /* Controller state */
685 qemu_get_8s(f, &s->sra);
686 qemu_get_8s(f, &s->srb);
687 qemu_get_8s(f, &s->dor);
688 SET_CUR_DRV(s, s->dor & FD_DOR_SELMASK);
689 s->dor &= ~FD_DOR_SELMASK;
690 qemu_get_8s(f, &s->tdr);
691 qemu_get_8s(f, &s->dsr);
692 qemu_get_8s(f, &s->msr);
693 qemu_get_8s(f, &s->status0);
694 qemu_get_8s(f, &s->status1);
695 qemu_get_8s(f, &s->status2);
696 /* Command FIFO */
697 qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
698 qemu_get_be32s(f, &s->data_pos);
699 qemu_get_be32s(f, &s->data_len);
700 qemu_get_8s(f, &s->data_state);
701 qemu_get_8s(f, &s->data_dir);
702 qemu_get_8s(f, &s->eot);
703 /* States kept only to be returned back */
704 qemu_get_8s(f, &s->timer0);
705 qemu_get_8s(f, &s->timer1);
706 qemu_get_8s(f, &s->precomp_trk);
707 qemu_get_8s(f, &s->config);
708 qemu_get_8s(f, &s->lock);
709 qemu_get_8s(f, &s->pwrd);
710 qemu_get_8s(f, &n);
711
712 if (n > MAX_FD)
713 return -EINVAL;
714
715 for (i = 0; i < n; i++) {
716 ret = fd_load(f, &s->drives[i]);
717 if (ret != 0)
718 break;
719 }
720
721 return ret;
722 }
723
724 static void fdctrl_external_reset(void *opaque)
725 {
726 fdctrl_t *s = opaque;
727
728 fdctrl_reset(s, 0);
729 }
730
731 static void fdctrl_handle_tc(void *opaque, int irq, int level)
732 {
733 //fdctrl_t *s = opaque;
734
735 if (level) {
736 // XXX
737 FLOPPY_DPRINTF("TC pulsed\n");
738 }
739 }
740
741 /* XXX: may change if moved to bdrv */
742 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
743 {
744 return fdctrl->drives[drive_num].drive;
745 }
746
747 /* Change IRQ state */
748 static void fdctrl_reset_irq (fdctrl_t *fdctrl)
749 {
750 if (!(fdctrl->sra & FD_SRA_INTPEND))
751 return;
752 FLOPPY_DPRINTF("Reset interrupt\n");
753 qemu_set_irq(fdctrl->irq, 0);
754 fdctrl->sra &= ~FD_SRA_INTPEND;
755 }
756
757 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
758 {
759 /* Sparc mutation */
760 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
761 /* XXX: not sure */
762 fdctrl->msr &= ~FD_MSR_CMDBUSY;
763 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
764 fdctrl->status0 = status0;
765 return;
766 }
767 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
768 qemu_set_irq(fdctrl->irq, 1);
769 fdctrl->sra |= FD_SRA_INTPEND;
770 }
771 fdctrl->reset_sensei = 0;
772 fdctrl->status0 = status0;
773 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
774 }
775
776 /* Reset controller */
777 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
778 {
779 int i;
780
781 FLOPPY_DPRINTF("reset controller\n");
782 fdctrl_reset_irq(fdctrl);
783 /* Initialise controller */
784 fdctrl->sra = 0;
785 fdctrl->srb = 0xc0;
786 if (!fdctrl->drives[1].bs)
787 fdctrl->sra |= FD_SRA_nDRV2;
788 fdctrl->cur_drv = 0;
789 fdctrl->dor = FD_DOR_nRESET;
790 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
791 fdctrl->msr = FD_MSR_RQM;
792 /* FIFO state */
793 fdctrl->data_pos = 0;
794 fdctrl->data_len = 0;
795 fdctrl->data_state = 0;
796 fdctrl->data_dir = FD_DIR_WRITE;
797 for (i = 0; i < MAX_FD; i++)
798 fd_recalibrate(&fdctrl->drives[i]);
799 fdctrl_reset_fifo(fdctrl);
800 if (do_irq) {
801 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
802 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
803 }
804 }
805
806 static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
807 {
808 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
809 }
810
811 static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
812 {
813 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
814 return &fdctrl->drives[1];
815 else
816 return &fdctrl->drives[0];
817 }
818
819 #if MAX_FD == 4
820 static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
821 {
822 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
823 return &fdctrl->drives[2];
824 else
825 return &fdctrl->drives[1];
826 }
827
828 static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
829 {
830 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
831 return &fdctrl->drives[3];
832 else
833 return &fdctrl->drives[2];
834 }
835 #endif
836
837 static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
838 {
839 switch (fdctrl->cur_drv) {
840 case 0: return drv0(fdctrl);
841 case 1: return drv1(fdctrl);
842 #if MAX_FD == 4
843 case 2: return drv2(fdctrl);
844 case 3: return drv3(fdctrl);
845 #endif
846 default: return NULL;
847 }
848 }
849
850 /* Status A register : 0x00 (read-only) */
851 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
852 {
853 uint32_t retval = fdctrl->sra;
854
855 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
856
857 return retval;
858 }
859
860 /* Status B register : 0x01 (read-only) */
861 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
862 {
863 uint32_t retval = fdctrl->srb;
864
865 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
866
867 return retval;
868 }
869
870 /* Digital output register : 0x02 */
871 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
872 {
873 uint32_t retval = fdctrl->dor;
874
875 /* Selected drive */
876 retval |= fdctrl->cur_drv;
877 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
878
879 return retval;
880 }
881
882 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
883 {
884 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
885
886 /* Motors */
887 if (value & FD_DOR_MOTEN0)
888 fdctrl->srb |= FD_SRB_MTR0;
889 else
890 fdctrl->srb &= ~FD_SRB_MTR0;
891 if (value & FD_DOR_MOTEN1)
892 fdctrl->srb |= FD_SRB_MTR1;
893 else
894 fdctrl->srb &= ~FD_SRB_MTR1;
895
896 /* Drive */
897 if (value & 1)
898 fdctrl->srb |= FD_SRB_DR0;
899 else
900 fdctrl->srb &= ~FD_SRB_DR0;
901
902 /* Reset */
903 if (!(value & FD_DOR_nRESET)) {
904 if (fdctrl->dor & FD_DOR_nRESET) {
905 FLOPPY_DPRINTF("controller enter RESET state\n");
906 }
907 } else {
908 if (!(fdctrl->dor & FD_DOR_nRESET)) {
909 FLOPPY_DPRINTF("controller out of RESET state\n");
910 fdctrl_reset(fdctrl, 1);
911 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
912 }
913 }
914 /* Selected drive */
915 fdctrl->cur_drv = value & FD_DOR_SELMASK;
916
917 fdctrl->dor = value;
918 }
919
920 /* Tape drive register : 0x03 */
921 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
922 {
923 uint32_t retval = fdctrl->tdr;
924
925 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
926
927 return retval;
928 }
929
930 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
931 {
932 /* Reset mode */
933 if (!(fdctrl->dor & FD_DOR_nRESET)) {
934 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
935 return;
936 }
937 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
938 /* Disk boot selection indicator */
939 fdctrl->tdr = value & FD_TDR_BOOTSEL;
940 /* Tape indicators: never allow */
941 }
942
943 /* Main status register : 0x04 (read) */
944 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
945 {
946 uint32_t retval = fdctrl->msr;
947
948 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
949 fdctrl->dor |= FD_DOR_nRESET;
950
951 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
952
953 return retval;
954 }
955
956 /* Data select rate register : 0x04 (write) */
957 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
958 {
959 /* Reset mode */
960 if (!(fdctrl->dor & FD_DOR_nRESET)) {
961 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
962 return;
963 }
964 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
965 /* Reset: autoclear */
966 if (value & FD_DSR_SWRESET) {
967 fdctrl->dor &= ~FD_DOR_nRESET;
968 fdctrl_reset(fdctrl, 1);
969 fdctrl->dor |= FD_DOR_nRESET;
970 }
971 if (value & FD_DSR_PWRDOWN) {
972 fdctrl_reset(fdctrl, 1);
973 }
974 fdctrl->dsr = value;
975 }
976
977 static int fdctrl_media_changed(fdrive_t *drv)
978 {
979 int ret;
980
981 if (!drv->bs)
982 return 0;
983 ret = bdrv_media_changed(drv->bs);
984 if (ret) {
985 fd_revalidate(drv);
986 }
987 return ret;
988 }
989
990 /* Digital input register : 0x07 (read-only) */
991 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
992 {
993 uint32_t retval = 0;
994
995 if (fdctrl_media_changed(drv0(fdctrl))
996 || fdctrl_media_changed(drv1(fdctrl))
997 #if MAX_FD == 4
998 || fdctrl_media_changed(drv2(fdctrl))
999 || fdctrl_media_changed(drv3(fdctrl))
1000 #endif
1001 )
1002 retval |= FD_DIR_DSKCHG;
1003 if (retval != 0)
1004 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1005
1006 return retval;
1007 }
1008
1009 /* FIFO state control */
1010 static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
1011 {
1012 fdctrl->data_dir = FD_DIR_WRITE;
1013 fdctrl->data_pos = 0;
1014 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1015 }
1016
1017 /* Set FIFO status for the host to read */
1018 static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1019 {
1020 fdctrl->data_dir = FD_DIR_READ;
1021 fdctrl->data_len = fifo_len;
1022 fdctrl->data_pos = 0;
1023 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1024 if (do_irq)
1025 fdctrl_raise_irq(fdctrl, 0x00);
1026 }
1027
1028 /* Set an error: unimplemented/unknown command */
1029 static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1030 {
1031 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1032 fdctrl->fifo[0] = FD_SR0_INVCMD;
1033 fdctrl_set_fifo(fdctrl, 1, 0);
1034 }
1035
1036 /* Seek to next sector */
1037 static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1038 {
1039 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1040 cur_drv->head, cur_drv->track, cur_drv->sect,
1041 fd_sector(cur_drv));
1042 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1043 error in fact */
1044 if (cur_drv->sect >= cur_drv->last_sect ||
1045 cur_drv->sect == fdctrl->eot) {
1046 cur_drv->sect = 1;
1047 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1048 if (cur_drv->head == 0 &&
1049 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1050 cur_drv->head = 1;
1051 } else {
1052 cur_drv->head = 0;
1053 cur_drv->track++;
1054 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1055 return 0;
1056 }
1057 } else {
1058 cur_drv->track++;
1059 return 0;
1060 }
1061 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1062 cur_drv->head, cur_drv->track,
1063 cur_drv->sect, fd_sector(cur_drv));
1064 } else {
1065 cur_drv->sect++;
1066 }
1067 return 1;
1068 }
1069
1070 /* Callback for transfer end (stop or abort) */
1071 static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1072 uint8_t status1, uint8_t status2)
1073 {
1074 fdrive_t *cur_drv;
1075
1076 cur_drv = get_cur_drv(fdctrl);
1077 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1078 status0, status1, status2,
1079 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1080 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1081 fdctrl->fifo[1] = status1;
1082 fdctrl->fifo[2] = status2;
1083 fdctrl->fifo[3] = cur_drv->track;
1084 fdctrl->fifo[4] = cur_drv->head;
1085 fdctrl->fifo[5] = cur_drv->sect;
1086 fdctrl->fifo[6] = FD_SECTOR_SC;
1087 fdctrl->data_dir = FD_DIR_READ;
1088 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1089 DMA_release_DREQ(fdctrl->dma_chann);
1090 }
1091 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1092 fdctrl->msr &= ~FD_MSR_NONDMA;
1093 fdctrl_set_fifo(fdctrl, 7, 1);
1094 }
1095
1096 /* Prepare a data transfer (either DMA or FIFO) */
1097 static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1098 {
1099 fdrive_t *cur_drv;
1100 uint8_t kh, kt, ks;
1101 int did_seek = 0;
1102
1103 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1104 cur_drv = get_cur_drv(fdctrl);
1105 kt = fdctrl->fifo[2];
1106 kh = fdctrl->fifo[3];
1107 ks = fdctrl->fifo[4];
1108 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1109 GET_CUR_DRV(fdctrl), kh, kt, ks,
1110 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1111 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1112 case 2:
1113 /* sect too big */
1114 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1115 fdctrl->fifo[3] = kt;
1116 fdctrl->fifo[4] = kh;
1117 fdctrl->fifo[5] = ks;
1118 return;
1119 case 3:
1120 /* track too big */
1121 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1122 fdctrl->fifo[3] = kt;
1123 fdctrl->fifo[4] = kh;
1124 fdctrl->fifo[5] = ks;
1125 return;
1126 case 4:
1127 /* No seek enabled */
1128 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1129 fdctrl->fifo[3] = kt;
1130 fdctrl->fifo[4] = kh;
1131 fdctrl->fifo[5] = ks;
1132 return;
1133 case 1:
1134 did_seek = 1;
1135 break;
1136 default:
1137 break;
1138 }
1139
1140 /* Set the FIFO state */
1141 fdctrl->data_dir = direction;
1142 fdctrl->data_pos = 0;
1143 fdctrl->msr |= FD_MSR_CMDBUSY;
1144 if (fdctrl->fifo[0] & 0x80)
1145 fdctrl->data_state |= FD_STATE_MULTI;
1146 else
1147 fdctrl->data_state &= ~FD_STATE_MULTI;
1148 if (did_seek)
1149 fdctrl->data_state |= FD_STATE_SEEK;
1150 else
1151 fdctrl->data_state &= ~FD_STATE_SEEK;
1152 if (fdctrl->fifo[5] == 00) {
1153 fdctrl->data_len = fdctrl->fifo[8];
1154 } else {
1155 int tmp;
1156 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1157 tmp = (fdctrl->fifo[6] - ks + 1);
1158 if (fdctrl->fifo[0] & 0x80)
1159 tmp += fdctrl->fifo[6];
1160 fdctrl->data_len *= tmp;
1161 }
1162 fdctrl->eot = fdctrl->fifo[6];
1163 if (fdctrl->dor & FD_DOR_DMAEN) {
1164 int dma_mode;
1165 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1166 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1167 dma_mode = (dma_mode >> 2) & 3;
1168 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1169 dma_mode, direction,
1170 (128 << fdctrl->fifo[5]) *
1171 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1172 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1173 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1174 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1175 (direction == FD_DIR_READ && dma_mode == 1)) {
1176 /* No access is allowed until DMA transfer has completed */
1177 fdctrl->msr &= ~FD_MSR_RQM;
1178 /* Now, we just have to wait for the DMA controller to
1179 * recall us...
1180 */
1181 DMA_hold_DREQ(fdctrl->dma_chann);
1182 DMA_schedule(fdctrl->dma_chann);
1183 return;
1184 } else {
1185 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1186 }
1187 }
1188 FLOPPY_DPRINTF("start non-DMA transfer\n");
1189 fdctrl->msr |= FD_MSR_NONDMA;
1190 if (direction != FD_DIR_WRITE)
1191 fdctrl->msr |= FD_MSR_DIO;
1192 /* IO based transfer: calculate len */
1193 fdctrl_raise_irq(fdctrl, 0x00);
1194
1195 return;
1196 }
1197
1198 /* Prepare a transfer of deleted data */
1199 static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1200 {
1201 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1202
1203 /* We don't handle deleted data,
1204 * so we don't return *ANYTHING*
1205 */
1206 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1207 }
1208
1209 /* handlers for DMA transfers */
1210 static int fdctrl_transfer_handler (void *opaque, int nchan,
1211 int dma_pos, int dma_len)
1212 {
1213 fdctrl_t *fdctrl;
1214 fdrive_t *cur_drv;
1215 int len, start_pos, rel_pos;
1216 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1217
1218 fdctrl = opaque;
1219 if (fdctrl->msr & FD_MSR_RQM) {
1220 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1221 return 0;
1222 }
1223 cur_drv = get_cur_drv(fdctrl);
1224 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1225 fdctrl->data_dir == FD_DIR_SCANH)
1226 status2 = FD_SR2_SNS;
1227 if (dma_len > fdctrl->data_len)
1228 dma_len = fdctrl->data_len;
1229 if (cur_drv->bs == NULL) {
1230 if (fdctrl->data_dir == FD_DIR_WRITE)
1231 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1232 else
1233 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1234 len = 0;
1235 goto transfer_error;
1236 }
1237 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1238 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1239 len = dma_len - fdctrl->data_pos;
1240 if (len + rel_pos > FD_SECTOR_LEN)
1241 len = FD_SECTOR_LEN - rel_pos;
1242 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1243 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1244 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1245 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1246 fd_sector(cur_drv) * FD_SECTOR_LEN);
1247 if (fdctrl->data_dir != FD_DIR_WRITE ||
1248 len < FD_SECTOR_LEN || rel_pos != 0) {
1249 /* READ & SCAN commands and realign to a sector for WRITE */
1250 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1251 fdctrl->fifo, 1) < 0) {
1252 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1253 fd_sector(cur_drv));
1254 /* Sure, image size is too small... */
1255 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1256 }
1257 }
1258 switch (fdctrl->data_dir) {
1259 case FD_DIR_READ:
1260 /* READ commands */
1261 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1262 fdctrl->data_pos, len);
1263 break;
1264 case FD_DIR_WRITE:
1265 /* WRITE commands */
1266 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1267 fdctrl->data_pos, len);
1268 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1269 fdctrl->fifo, 1) < 0) {
1270 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1271 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1272 goto transfer_error;
1273 }
1274 break;
1275 default:
1276 /* SCAN commands */
1277 {
1278 uint8_t tmpbuf[FD_SECTOR_LEN];
1279 int ret;
1280 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1281 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1282 if (ret == 0) {
1283 status2 = FD_SR2_SEH;
1284 goto end_transfer;
1285 }
1286 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1287 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1288 status2 = 0x00;
1289 goto end_transfer;
1290 }
1291 }
1292 break;
1293 }
1294 fdctrl->data_pos += len;
1295 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1296 if (rel_pos == 0) {
1297 /* Seek to next sector */
1298 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1299 break;
1300 }
1301 }
1302 end_transfer:
1303 len = fdctrl->data_pos - start_pos;
1304 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1305 fdctrl->data_pos, len, fdctrl->data_len);
1306 if (fdctrl->data_dir == FD_DIR_SCANE ||
1307 fdctrl->data_dir == FD_DIR_SCANL ||
1308 fdctrl->data_dir == FD_DIR_SCANH)
1309 status2 = FD_SR2_SEH;
1310 if (FD_DID_SEEK(fdctrl->data_state))
1311 status0 |= FD_SR0_SEEK;
1312 fdctrl->data_len -= len;
1313 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1314 transfer_error:
1315
1316 return len;
1317 }
1318
1319 /* Data register : 0x05 */
1320 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1321 {
1322 fdrive_t *cur_drv;
1323 uint32_t retval = 0;
1324 int pos;
1325
1326 cur_drv = get_cur_drv(fdctrl);
1327 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1328 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1329 FLOPPY_ERROR("controller not ready for reading\n");
1330 return 0;
1331 }
1332 pos = fdctrl->data_pos;
1333 if (fdctrl->msr & FD_MSR_NONDMA) {
1334 pos %= FD_SECTOR_LEN;
1335 if (pos == 0) {
1336 if (fdctrl->data_pos != 0)
1337 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1338 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1339 fd_sector(cur_drv));
1340 return 0;
1341 }
1342 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1343 FLOPPY_DPRINTF("error getting sector %d\n",
1344 fd_sector(cur_drv));
1345 /* Sure, image size is too small... */
1346 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1347 }
1348 }
1349 }
1350 retval = fdctrl->fifo[pos];
1351 if (++fdctrl->data_pos == fdctrl->data_len) {
1352 fdctrl->data_pos = 0;
1353 /* Switch from transfer mode to status mode
1354 * then from status mode to command mode
1355 */
1356 if (fdctrl->msr & FD_MSR_NONDMA) {
1357 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1358 } else {
1359 fdctrl_reset_fifo(fdctrl);
1360 fdctrl_reset_irq(fdctrl);
1361 }
1362 }
1363 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1364
1365 return retval;
1366 }
1367
1368 static void fdctrl_format_sector (fdctrl_t *fdctrl)
1369 {
1370 fdrive_t *cur_drv;
1371 uint8_t kh, kt, ks;
1372
1373 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1374 cur_drv = get_cur_drv(fdctrl);
1375 kt = fdctrl->fifo[6];
1376 kh = fdctrl->fifo[7];
1377 ks = fdctrl->fifo[8];
1378 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1379 GET_CUR_DRV(fdctrl), kh, kt, ks,
1380 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1381 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1382 case 2:
1383 /* sect too big */
1384 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1385 fdctrl->fifo[3] = kt;
1386 fdctrl->fifo[4] = kh;
1387 fdctrl->fifo[5] = ks;
1388 return;
1389 case 3:
1390 /* track too big */
1391 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1392 fdctrl->fifo[3] = kt;
1393 fdctrl->fifo[4] = kh;
1394 fdctrl->fifo[5] = ks;
1395 return;
1396 case 4:
1397 /* No seek enabled */
1398 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1399 fdctrl->fifo[3] = kt;
1400 fdctrl->fifo[4] = kh;
1401 fdctrl->fifo[5] = ks;
1402 return;
1403 case 1:
1404 fdctrl->data_state |= FD_STATE_SEEK;
1405 break;
1406 default:
1407 break;
1408 }
1409 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1410 if (cur_drv->bs == NULL ||
1411 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1412 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1413 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1414 } else {
1415 if (cur_drv->sect == cur_drv->last_sect) {
1416 fdctrl->data_state &= ~FD_STATE_FORMAT;
1417 /* Last sector done */
1418 if (FD_DID_SEEK(fdctrl->data_state))
1419 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1420 else
1421 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1422 } else {
1423 /* More to do */
1424 fdctrl->data_pos = 0;
1425 fdctrl->data_len = 4;
1426 }
1427 }
1428 }
1429
1430 static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1431 {
1432 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1433 fdctrl->fifo[0] = fdctrl->lock << 4;
1434 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1435 }
1436
1437 static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1438 {
1439 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1440
1441 /* Drives position */
1442 fdctrl->fifo[0] = drv0(fdctrl)->track;
1443 fdctrl->fifo[1] = drv1(fdctrl)->track;
1444 #if MAX_FD == 4
1445 fdctrl->fifo[2] = drv2(fdctrl)->track;
1446 fdctrl->fifo[3] = drv3(fdctrl)->track;
1447 #else
1448 fdctrl->fifo[2] = 0;
1449 fdctrl->fifo[3] = 0;
1450 #endif
1451 /* timers */
1452 fdctrl->fifo[4] = fdctrl->timer0;
1453 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1454 fdctrl->fifo[6] = cur_drv->last_sect;
1455 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1456 (cur_drv->perpendicular << 2);
1457 fdctrl->fifo[8] = fdctrl->config;
1458 fdctrl->fifo[9] = fdctrl->precomp_trk;
1459 fdctrl_set_fifo(fdctrl, 10, 0);
1460 }
1461
1462 static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1463 {
1464 /* Controller's version */
1465 fdctrl->fifo[0] = fdctrl->version;
1466 fdctrl_set_fifo(fdctrl, 1, 1);
1467 }
1468
1469 static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1470 {
1471 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1472 fdctrl_set_fifo(fdctrl, 1, 0);
1473 }
1474
1475 static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1476 {
1477 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1478
1479 /* Drives position */
1480 drv0(fdctrl)->track = fdctrl->fifo[3];
1481 drv1(fdctrl)->track = fdctrl->fifo[4];
1482 #if MAX_FD == 4
1483 drv2(fdctrl)->track = fdctrl->fifo[5];
1484 drv3(fdctrl)->track = fdctrl->fifo[6];
1485 #endif
1486 /* timers */
1487 fdctrl->timer0 = fdctrl->fifo[7];
1488 fdctrl->timer1 = fdctrl->fifo[8];
1489 cur_drv->last_sect = fdctrl->fifo[9];
1490 fdctrl->lock = fdctrl->fifo[10] >> 7;
1491 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1492 fdctrl->config = fdctrl->fifo[11];
1493 fdctrl->precomp_trk = fdctrl->fifo[12];
1494 fdctrl->pwrd = fdctrl->fifo[13];
1495 fdctrl_reset_fifo(fdctrl);
1496 }
1497
1498 static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1499 {
1500 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1501
1502 fdctrl->fifo[0] = 0;
1503 fdctrl->fifo[1] = 0;
1504 /* Drives position */
1505 fdctrl->fifo[2] = drv0(fdctrl)->track;
1506 fdctrl->fifo[3] = drv1(fdctrl)->track;
1507 #if MAX_FD == 4
1508 fdctrl->fifo[4] = drv2(fdctrl)->track;
1509 fdctrl->fifo[5] = drv3(fdctrl)->track;
1510 #else
1511 fdctrl->fifo[4] = 0;
1512 fdctrl->fifo[5] = 0;
1513 #endif
1514 /* timers */
1515 fdctrl->fifo[6] = fdctrl->timer0;
1516 fdctrl->fifo[7] = fdctrl->timer1;
1517 fdctrl->fifo[8] = cur_drv->last_sect;
1518 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1519 (cur_drv->perpendicular << 2);
1520 fdctrl->fifo[10] = fdctrl->config;
1521 fdctrl->fifo[11] = fdctrl->precomp_trk;
1522 fdctrl->fifo[12] = fdctrl->pwrd;
1523 fdctrl->fifo[13] = 0;
1524 fdctrl->fifo[14] = 0;
1525 fdctrl_set_fifo(fdctrl, 15, 1);
1526 }
1527
1528 static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1529 {
1530 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1531
1532 /* XXX: should set main status register to busy */
1533 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1534 qemu_mod_timer(fdctrl->result_timer,
1535 qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
1536 }
1537
1538 static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1539 {
1540 fdrive_t *cur_drv;
1541
1542 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1543 cur_drv = get_cur_drv(fdctrl);
1544 fdctrl->data_state |= FD_STATE_FORMAT;
1545 if (fdctrl->fifo[0] & 0x80)
1546 fdctrl->data_state |= FD_STATE_MULTI;
1547 else
1548 fdctrl->data_state &= ~FD_STATE_MULTI;
1549 fdctrl->data_state &= ~FD_STATE_SEEK;
1550 cur_drv->bps =
1551 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1552 #if 0
1553 cur_drv->last_sect =
1554 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1555 fdctrl->fifo[3] / 2;
1556 #else
1557 cur_drv->last_sect = fdctrl->fifo[3];
1558 #endif
1559 /* TODO: implement format using DMA expected by the Bochs BIOS
1560 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1561 * the sector with the specified fill byte
1562 */
1563 fdctrl->data_state &= ~FD_STATE_FORMAT;
1564 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1565 }
1566
1567 static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1568 {
1569 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1570 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1571 if (fdctrl->fifo[2] & 1)
1572 fdctrl->dor &= ~FD_DOR_DMAEN;
1573 else
1574 fdctrl->dor |= FD_DOR_DMAEN;
1575 /* No result back */
1576 fdctrl_reset_fifo(fdctrl);
1577 }
1578
1579 static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1580 {
1581 fdrive_t *cur_drv;
1582
1583 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1584 cur_drv = get_cur_drv(fdctrl);
1585 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1586 /* 1 Byte status back */
1587 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1588 (cur_drv->track == 0 ? 0x10 : 0x00) |
1589 (cur_drv->head << 2) |
1590 GET_CUR_DRV(fdctrl) |
1591 0x28;
1592 fdctrl_set_fifo(fdctrl, 1, 0);
1593 }
1594
1595 static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1596 {
1597 fdrive_t *cur_drv;
1598
1599 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1600 cur_drv = get_cur_drv(fdctrl);
1601 fd_recalibrate(cur_drv);
1602 fdctrl_reset_fifo(fdctrl);
1603 /* Raise Interrupt */
1604 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1605 }
1606
1607 static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1608 {
1609 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1610
1611 if(fdctrl->reset_sensei > 0) {
1612 fdctrl->fifo[0] =
1613 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1614 fdctrl->reset_sensei--;
1615 } else {
1616 /* XXX: status0 handling is broken for read/write
1617 commands, so we do this hack. It should be suppressed
1618 ASAP */
1619 fdctrl->fifo[0] =
1620 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1621 }
1622
1623 fdctrl->fifo[1] = cur_drv->track;
1624 fdctrl_set_fifo(fdctrl, 2, 0);
1625 fdctrl_reset_irq(fdctrl);
1626 fdctrl->status0 = FD_SR0_RDYCHG;
1627 }
1628
1629 static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1630 {
1631 fdrive_t *cur_drv;
1632
1633 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1634 cur_drv = get_cur_drv(fdctrl);
1635 fdctrl_reset_fifo(fdctrl);
1636 if (fdctrl->fifo[2] > cur_drv->max_track) {
1637 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1638 } else {
1639 cur_drv->track = fdctrl->fifo[2];
1640 /* Raise Interrupt */
1641 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1642 }
1643 }
1644
1645 static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1646 {
1647 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1648
1649 if (fdctrl->fifo[1] & 0x80)
1650 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1651 /* No result back */
1652 fdctrl_reset_fifo(fdctrl);
1653 }
1654
1655 static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1656 {
1657 fdctrl->config = fdctrl->fifo[2];
1658 fdctrl->precomp_trk = fdctrl->fifo[3];
1659 /* No result back */
1660 fdctrl_reset_fifo(fdctrl);
1661 }
1662
1663 static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1664 {
1665 fdctrl->pwrd = fdctrl->fifo[1];
1666 fdctrl->fifo[0] = fdctrl->fifo[1];
1667 fdctrl_set_fifo(fdctrl, 1, 1);
1668 }
1669
1670 static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1671 {
1672 /* No result back */
1673 fdctrl_reset_fifo(fdctrl);
1674 }
1675
1676 static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1677 {
1678 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1679
1680 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1681 /* Command parameters done */
1682 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1683 fdctrl->fifo[0] = fdctrl->fifo[1];
1684 fdctrl->fifo[2] = 0;
1685 fdctrl->fifo[3] = 0;
1686 fdctrl_set_fifo(fdctrl, 4, 1);
1687 } else {
1688 fdctrl_reset_fifo(fdctrl);
1689 }
1690 } else if (fdctrl->data_len > 7) {
1691 /* ERROR */
1692 fdctrl->fifo[0] = 0x80 |
1693 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1694 fdctrl_set_fifo(fdctrl, 1, 1);
1695 }
1696 }
1697
1698 static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1699 {
1700 fdrive_t *cur_drv;
1701
1702 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1703 cur_drv = get_cur_drv(fdctrl);
1704 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1705 cur_drv->track = cur_drv->max_track - 1;
1706 } else {
1707 cur_drv->track += fdctrl->fifo[2];
1708 }
1709 fdctrl_reset_fifo(fdctrl);
1710 /* Raise Interrupt */
1711 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1712 }
1713
1714 static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1715 {
1716 fdrive_t *cur_drv;
1717
1718 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1719 cur_drv = get_cur_drv(fdctrl);
1720 if (fdctrl->fifo[2] > cur_drv->track) {
1721 cur_drv->track = 0;
1722 } else {
1723 cur_drv->track -= fdctrl->fifo[2];
1724 }
1725 fdctrl_reset_fifo(fdctrl);
1726 /* Raise Interrupt */
1727 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1728 }
1729
1730 static const struct {
1731 uint8_t value;
1732 uint8_t mask;
1733 const char* name;
1734 int parameters;
1735 void (*handler)(fdctrl_t *fdctrl, int direction);
1736 int direction;
1737 } handlers[] = {
1738 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1739 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1740 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1741 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1742 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1743 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1744 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1745 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1746 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1747 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1748 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1749 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1750 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1751 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1752 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1753 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1754 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1755 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1756 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1757 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1758 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1759 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1760 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1761 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1762 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1763 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1764 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1765 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1766 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1767 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1768 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1769 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1770 };
1771 /* Associate command to an index in the 'handlers' array */
1772 static uint8_t command_to_handler[256];
1773
1774 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1775 {
1776 fdrive_t *cur_drv;
1777 int pos;
1778
1779 /* Reset mode */
1780 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1781 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1782 return;
1783 }
1784 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1785 FLOPPY_ERROR("controller not ready for writing\n");
1786 return;
1787 }
1788 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1789 /* Is it write command time ? */
1790 if (fdctrl->msr & FD_MSR_NONDMA) {
1791 /* FIFO data write */
1792 pos = fdctrl->data_pos++;
1793 pos %= FD_SECTOR_LEN;
1794 fdctrl->fifo[pos] = value;
1795 if (pos == FD_SECTOR_LEN - 1 ||
1796 fdctrl->data_pos == fdctrl->data_len) {
1797 cur_drv = get_cur_drv(fdctrl);
1798 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1799 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1800 return;
1801 }
1802 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1803 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1804 fd_sector(cur_drv));
1805 return;
1806 }
1807 }
1808 /* Switch from transfer mode to status mode
1809 * then from status mode to command mode
1810 */
1811 if (fdctrl->data_pos == fdctrl->data_len)
1812 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1813 return;
1814 }
1815 if (fdctrl->data_pos == 0) {
1816 /* Command */
1817 pos = command_to_handler[value & 0xff];
1818 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1819 fdctrl->data_len = handlers[pos].parameters + 1;
1820 }
1821
1822 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1823 fdctrl->fifo[fdctrl->data_pos++] = value;
1824 if (fdctrl->data_pos == fdctrl->data_len) {
1825 /* We now have all parameters
1826 * and will be able to treat the command
1827 */
1828 if (fdctrl->data_state & FD_STATE_FORMAT) {
1829 fdctrl_format_sector(fdctrl);
1830 return;
1831 }
1832
1833 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1834 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1835 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1836 }
1837 }
1838
1839 static void fdctrl_result_timer(void *opaque)
1840 {
1841 fdctrl_t *fdctrl = opaque;
1842 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1843
1844 /* Pretend we are spinning.
1845 * This is needed for Coherent, which uses READ ID to check for
1846 * sector interleaving.
1847 */
1848 if (cur_drv->last_sect != 0) {
1849 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1850 }
1851 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1852 }
1853
1854 /* Init functions */
1855 static void fdctrl_init_common (fdctrl_t *fdctrl, int dma_chann,
1856 target_phys_addr_t io_base,
1857 BlockDriverState **fds)
1858 {
1859 int i, j;
1860
1861 /* Fill 'command_to_handler' lookup table */
1862 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1863 for (j = 0; j < sizeof(command_to_handler); j++) {
1864 if ((j & handlers[i].mask) == handlers[i].value)
1865 command_to_handler[j] = i;
1866 }
1867 }
1868
1869 FLOPPY_DPRINTF("init controller\n");
1870 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1871 fdctrl->result_timer = qemu_new_timer(vm_clock,
1872 fdctrl_result_timer, fdctrl);
1873
1874 fdctrl->version = 0x90; /* Intel 82078 controller */
1875 fdctrl->dma_chann = dma_chann;
1876 fdctrl->io_base = io_base;
1877 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1878 if (fdctrl->dma_chann != -1) {
1879 DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1880 }
1881 for (i = 0; i < MAX_FD; i++) {
1882 fd_init(&fdctrl->drives[i], fds[i]);
1883 }
1884 fdctrl_external_reset(fdctrl);
1885 register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
1886 qemu_register_reset(fdctrl_external_reset, fdctrl);
1887 for (i = 0; i < MAX_FD; i++) {
1888 fd_revalidate(&fdctrl->drives[i]);
1889 }
1890 }
1891
1892 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1893 target_phys_addr_t io_base,
1894 BlockDriverState **fds)
1895 {
1896 DeviceState *dev;
1897 SysBusDevice *s;
1898 fdctrl_t *fdctrl;
1899
1900 dev = qdev_create(NULL, "fdc");
1901 qdev_set_prop_int(dev, "strict_io", 0);
1902 qdev_set_prop_int(dev, "mem_mapped", mem_mapped);
1903 qdev_set_prop_int(dev, "sun4m", 0);
1904 qdev_init(dev);
1905 s = sysbus_from_qdev(dev);
1906 sysbus_connect_irq(s, 0, irq);
1907 fdctrl = FROM_SYSBUS(fdctrl_t, s);
1908 if (mem_mapped) {
1909 sysbus_mmio_map(s, 0, io_base);
1910 } else {
1911 register_ioport_read((uint32_t)io_base + 0x01, 5, 1,
1912 &fdctrl_read_port, fdctrl);
1913 register_ioport_read((uint32_t)io_base + 0x07, 1, 1,
1914 &fdctrl_read_port, fdctrl);
1915 register_ioport_write((uint32_t)io_base + 0x01, 5, 1,
1916 &fdctrl_write_port, fdctrl);
1917 register_ioport_write((uint32_t)io_base + 0x07, 1, 1,
1918 &fdctrl_write_port, fdctrl);
1919 }
1920
1921 fdctrl_init_common(fdctrl, dma_chann, io_base, fds);
1922
1923 return fdctrl;
1924 }
1925
1926 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1927 BlockDriverState **fds, qemu_irq *fdc_tc)
1928 {
1929 DeviceState *dev;
1930 SysBusDevice *s;
1931 fdctrl_t *fdctrl;
1932
1933 dev = qdev_create(NULL, "fdc");
1934 qdev_set_prop_int(dev, "strict_io", 1);
1935 qdev_set_prop_int(dev, "mem_mapped", 1);
1936 qdev_set_prop_int(dev, "sun4m", 1);
1937 qdev_init(dev);
1938 s = sysbus_from_qdev(dev);
1939 sysbus_connect_irq(s, 0, irq);
1940 sysbus_mmio_map(s, 0, io_base);
1941 *fdc_tc = qdev_get_gpio_in(dev, 0);
1942
1943 fdctrl = FROM_SYSBUS(fdctrl_t, s);
1944 fdctrl_init_common(fdctrl, -1, io_base, fds);
1945
1946 return fdctrl;
1947 }
1948
1949 static void fdc_init1(SysBusDevice *dev)
1950 {
1951 fdctrl_t *s = FROM_SYSBUS(fdctrl_t, dev);
1952 int io;
1953
1954 sysbus_init_irq(dev, &s->irq);
1955 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1956 if (qdev_get_prop_int(&dev->qdev, "strict_io", 0)) {
1957 io = cpu_register_io_memory(fdctrl_mem_read_strict,
1958 fdctrl_mem_write_strict, s);
1959 } else {
1960 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, s);
1961 }
1962 sysbus_init_mmio(dev, 0x08, io);
1963 }
1964
1965
1966 static SysBusDeviceInfo fdc_info = {
1967 .init = fdc_init1,
1968 .qdev.name = "fdc",
1969 .qdev.size = sizeof(fdctrl_t),
1970 .qdev.props = (DevicePropList[]) {
1971 {.name = "io_base", .type = PROP_TYPE_INT},
1972 {.name = "strict_io", .type = PROP_TYPE_INT},
1973 {.name = "mem_mapped", .type = PROP_TYPE_INT},
1974 {.name = "sun4m", .type = PROP_TYPE_INT},
1975 {.name = NULL}
1976 }
1977 };
1978
1979 static void fdc_register_devices(void)
1980 {
1981 sysbus_register_withprop(&fdc_info);
1982 }
1983
1984 device_init(fdc_register_devices)
Adding pft support to QEMU's arm cpus