hw/mips_jazz.c

   1 /*
   2  * QEMU MIPS Jazz support
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "pc.h"
  28 #include "isa.h"
  29 #include "fdc.h"
  30 #include "sysemu.h"
  31 #include "audio/audio.h"
  32 #include "boards.h"
  33 #include "net.h"
  34 #include "scsi.h"
  35 #include "mips-bios.h"
  36 #include "loader.h"
  37
  38 enum jazz_model_e
  39 {
  40     JAZZ_MAGNUM,
  41     JAZZ_PICA61,
  42 };
  43
  44 static void main_cpu_reset(void *opaque)
  45 {
  46     CPUState *env = opaque;
  47     cpu_reset(env);
  48 }
  49
  50 static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
  51 {
  52     return cpu_inw(0x71);
  53 }
  54
  55 static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  56 {
  57     cpu_outw(0x71, val & 0xff);
  58 }
  59
  60 static CPUReadMemoryFunc * const rtc_read[3] = {
  61     rtc_readb,
  62     rtc_readb,
  63     rtc_readb,
  64 };
  65
  66 static CPUWriteMemoryFunc * const rtc_write[3] = {
  67     rtc_writeb,
  68     rtc_writeb,
  69     rtc_writeb,
  70 };
  71
  72 static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  73 {
  74     /* Nothing to do. That is only to ensure that
  75      * the current DMA acknowledge cycle is completed. */
  76 }
  77
  78 static CPUReadMemoryFunc * const dma_dummy_read[3] = {
  79     NULL,
  80     NULL,
  81     NULL,
  82 };
  83
  84 static CPUWriteMemoryFunc * const dma_dummy_write[3] = {
  85     dma_dummy_writeb,
  86     dma_dummy_writeb,
  87     dma_dummy_writeb,
  88 };
  89
  90 #ifdef HAS_AUDIO
  91 static void audio_init(qemu_irq *pic)
  92 {
  93     struct soundhw *c;
  94     int audio_enabled = 0;
  95
  96     for (c = soundhw; !audio_enabled && c->name; ++c) {
  97         audio_enabled = c->enabled;
  98     }
  99
 100     if (audio_enabled) {
 101         for (c = soundhw; c->name; ++c) {
 102             if (c->enabled) {
 103                 if (c->isa) {
 104                     c->init.init_isa(pic);
 105                 }
 106             }
 107         }
 108     }
 109 }
 110 #endif
 111
 112 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
 113 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
 114
 115 static
 116 void mips_jazz_init (ram_addr_t ram_size,
 117                      const char *cpu_model,
 118                      enum jazz_model_e jazz_model)
 119 {
 120     char *filename;
 121     int bios_size, n;
 122     CPUState *env;
 123     qemu_irq *rc4030, *i8259;
 124     rc4030_dma *dmas;
 125     void* rc4030_opaque;
 126     int s_rtc, s_dma_dummy;
 127     NICInfo *nd;
 128     PITState *pit;
 129     DriveInfo *fds[MAX_FD];
 130     qemu_irq esp_reset;
 131     ram_addr_t ram_offset;
 132     ram_addr_t bios_offset;
 133
 134     /* init CPUs */
 135     if (cpu_model == NULL) {
 136 #ifdef TARGET_MIPS64
 137         cpu_model = "R4000";
 138 #else
 139         /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
 140         cpu_model = "24Kf";
 141 #endif
 142     }
 143     env = cpu_init(cpu_model);
 144     if (!env) {
 145         fprintf(stderr, "Unable to find CPU definition\n");
 146         exit(1);
 147     }
 148     qemu_register_reset(main_cpu_reset, env);
 149
 150     /* allocate RAM */
 151     ram_offset = qemu_ram_alloc(ram_size);
 152     cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
 153
 154     bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE);
 155     cpu_register_physical_memory(0x1fc00000LL,
 156                                  MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
 157     cpu_register_physical_memory(0xfff00000LL,
 158                                  MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
 159
 160     /* load the BIOS image. */
 161     if (bios_name == NULL)
 162         bios_name = BIOS_FILENAME;
 163     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 164     if (filename) {
 165         bios_size = load_image_targphys(filename, 0xfff00000LL,
 166                                         MAGNUM_BIOS_SIZE);
 167         qemu_free(filename);
 168     } else {
 169         bios_size = -1;
 170     }
 171     if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
 172         fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
 173                 bios_name);
 174         exit(1);
 175     }
 176
 177     /* Init CPU internal devices */
 178     cpu_mips_irq_init_cpu(env);
 179     cpu_mips_clock_init(env);
 180
 181     /* Chipset */
 182     rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
 183     s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
 184     cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
 185
 186     /* ISA devices */
 187     i8259 = i8259_init(env->irq[4]);
 188     isa_bus_new(NULL);
 189     isa_bus_irqs(i8259);
 190     DMA_init(0);
 191     pit = pit_init(0x40, i8259[0]);
 192     pcspk_init(pit);
 193
 194     /* ISA IO space at 0x90000000 */
 195     isa_mmio_init(0x90000000, 0x01000000);
 196     isa_mem_base = 0x11000000;
 197
 198     /* Video card */
 199     switch (jazz_model) {
 200     case JAZZ_MAGNUM:
 201         g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
 202         break;
 203     case JAZZ_PICA61:
 204         isa_vga_mm_init(0x40000000, 0x60000000, 0);
 205         break;
 206     default:
 207         break;
 208     }
 209
 210     /* Network controller */
 211     for (n = 0; n < nb_nics; n++) {
 212         nd = &nd_table[n];
 213         if (!nd->model)
 214             nd->model = qemu_strdup("dp83932");
 215         if (strcmp(nd->model, "dp83932") == 0) {
 216             dp83932_init(nd, 0x80001000, 2, rc4030[4],
 217                          rc4030_opaque, rc4030_dma_memory_rw);
 218             break;
 219         } else if (strcmp(nd->model, "?") == 0) {
 220             fprintf(stderr, "qemu: Supported NICs: dp83932\n");
 221             exit(1);
 222         } else {
 223             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 224             exit(1);
 225         }
 226     }
 227
 228     /* SCSI adapter */
 229     esp_init(0x80002000, 0,
 230              rc4030_dma_read, rc4030_dma_write, dmas[0],
 231              rc4030[5], &esp_reset);
 232
 233     /* Floppy */
 234     if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
 235         fprintf(stderr, "qemu: too many floppy drives\n");
 236         exit(1);
 237     }
 238     for (n = 0; n < MAX_FD; n++) {
 239         fds[n] = drive_get(IF_FLOPPY, 0, n);
 240     }
 241     fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
 242
 243     /* Real time clock */
 244     rtc_init(1980);
 245     s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL);
 246     cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
 247
 248     /* Keyboard (i8042) */
 249     i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
 250
 251     /* Serial ports */
 252     if (serial_hds[0])
 253         serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
 254     if (serial_hds[1])
 255         serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
 256
 257     /* Parallel port */
 258     if (parallel_hds[0])
 259         parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
 260
 261     /* Sound card */
 262     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
 263 #ifdef HAS_AUDIO
 264     audio_init(i8259);
 265 #endif
 266
 267     /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
 268     ds1225y_init(0x80009000, "nvram");
 269
 270     /* LED indicator */
 271     jazz_led_init(0x8000f000);
 272 }
 273
 274 static
 275 void mips_magnum_init (ram_addr_t ram_size,
 276                        const char *boot_device,
 277                        const char *kernel_filename, const char *kernel_cmdline,
 278                        const char *initrd_filename, const char *cpu_model)
 279 {
 280     mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM);
 281 }
 282
 283 static
 284 void mips_pica61_init (ram_addr_t ram_size,
 285                        const char *boot_device,
 286                        const char *kernel_filename, const char *kernel_cmdline,
 287                        const char *initrd_filename, const char *cpu_model)
 288 {
 289     mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61);
 290 }
 291
 292 static QEMUMachine mips_magnum_machine = {
 293     .name = "magnum",
 294     .desc = "MIPS Magnum",
 295     .init = mips_magnum_init,
 296     .use_scsi = 1,
 297 };
 298
 299 static QEMUMachine mips_pica61_machine = {
 300     .name = "pica61",
 301     .desc = "Acer Pica 61",
 302     .init = mips_pica61_init,
 303     .use_scsi = 1,
 304 };
 305
 306 static void mips_jazz_machine_init(void)
 307 {
 308     qemu_register_machine(&mips_magnum_machine);
 309     qemu_register_machine(&mips_pica61_machine);
 310 }
 311
 312 machine_init(mips_jazz_machine_init);