hw/grackle_pci.c

   1 /*
   2  * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
   3  *
   4  * Copyright (c) 2006-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "sysbus.h"
  27 #include "ppc_mac.h"
  28 #include "pci.h"
  29
  30 /* debug Grackle */
  31 //#define DEBUG_GRACKLE
  32
  33 #ifdef DEBUG_GRACKLE
  34 #define GRACKLE_DPRINTF(fmt, ...)                               \
  35     do { printf("GRACKLE: " fmt , ## __VA_ARGS__); } while (0)
  36 #else
  37 #define GRACKLE_DPRINTF(fmt, ...)
  38 #endif
  39
  40 typedef target_phys_addr_t pci_addr_t;
  41 #include "pci_host.h"
  42
  43 typedef struct GrackleState {
  44     SysBusDevice busdev;
  45     PCIHostState host_state;
  46 } GrackleState;
  47
  48 static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
  49                                        uint32_t val)
  50 {
  51     GrackleState *s = opaque;
  52
  53     GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
  54                     val);
  55 #ifdef TARGET_WORDS_BIGENDIAN
  56     val = bswap32(val);
  57 #endif
  58     s->host_state.config_reg = val;
  59 }
  60
  61 static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
  62 {
  63     GrackleState *s = opaque;
  64     uint32_t val;
  65
  66     val = s->host_state.config_reg;
  67 #ifdef TARGET_WORDS_BIGENDIAN
  68     val = bswap32(val);
  69 #endif
  70     GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
  71                     val);
  72     return val;
  73 }
  74
  75 static CPUWriteMemoryFunc * const pci_grackle_config_write[] = {
  76     &pci_grackle_config_writel,
  77     &pci_grackle_config_writel,
  78     &pci_grackle_config_writel,
  79 };
  80
  81 static CPUReadMemoryFunc * const pci_grackle_config_read[] = {
  82     &pci_grackle_config_readl,
  83     &pci_grackle_config_readl,
  84     &pci_grackle_config_readl,
  85 };
  86
  87 static CPUWriteMemoryFunc * const pci_grackle_write[] = {
  88     &pci_host_data_writeb,
  89     &pci_host_data_writew,
  90     &pci_host_data_writel,
  91 };
  92
  93 static CPUReadMemoryFunc * const pci_grackle_read[] = {
  94     &pci_host_data_readb,
  95     &pci_host_data_readw,
  96     &pci_host_data_readl,
  97 };
  98
  99 /* Don't know if this matches real hardware, but it agrees with OHW.  */
 100 static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
 101 {
 102     return (irq_num + (pci_dev->devfn >> 3)) & 3;
 103 }
 104
 105 static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
 106 {
 107     qemu_irq *pic = opaque;
 108
 109     GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
 110     qemu_set_irq(pic[irq_num + 0x15], level);
 111 }
 112
 113 static void pci_grackle_save(QEMUFile* f, void *opaque)
 114 {
 115     PCIDevice *d = opaque;
 116
 117     pci_device_save(d, f);
 118 }
 119
 120 static int pci_grackle_load(QEMUFile* f, void *opaque, int version_id)
 121 {
 122     PCIDevice *d = opaque;
 123
 124     if (version_id != 1)
 125         return -EINVAL;
 126
 127     return pci_device_load(d, f);
 128 }
 129
 130 static void pci_grackle_reset(void *opaque)
 131 {
 132 }
 133
 134 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
 135 {
 136     DeviceState *dev;
 137     SysBusDevice *s;
 138     GrackleState *d;
 139
 140     dev = qdev_create(NULL, "grackle");
 141     qdev_init_nofail(dev);
 142     s = sysbus_from_qdev(dev);
 143     d = FROM_SYSBUS(GrackleState, s);
 144     d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
 145                                          pci_grackle_set_irq,
 146                                          pci_grackle_map_irq,
 147                                          pic, 0, 4);
 148
 149     pci_create_simple(d->host_state.bus, 0, "grackle");
 150
 151     sysbus_mmio_map(s, 0, base);
 152     sysbus_mmio_map(s, 1, base + 0x00200000);
 153
 154     return d->host_state.bus;
 155 }
 156
 157 static int pci_grackle_init_device(SysBusDevice *dev)
 158 {
 159     GrackleState *s;
 160     int pci_mem_config, pci_mem_data;
 161
 162     s = FROM_SYSBUS(GrackleState, dev);
 163
 164     pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
 165                                             pci_grackle_config_write, s);
 166     pci_mem_data = cpu_register_io_memory(pci_grackle_read,
 167                                           pci_grackle_write,
 168                                           &s->host_state);
 169     sysbus_init_mmio(dev, 0x1000, pci_mem_config);
 170     sysbus_init_mmio(dev, 0x1000, pci_mem_data);
 171
 172     register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load,
 173                     &s->host_state);
 174     qemu_register_reset(pci_grackle_reset, &s->host_state);
 175     pci_grackle_reset(&s->host_state);
 176     return 0;
 177 }
 178
 179 static int pci_dec_21154_init_device(SysBusDevice *dev)
 180 {
 181     GrackleState *s;
 182     int pci_mem_config, pci_mem_data;
 183
 184     s = FROM_SYSBUS(GrackleState, dev);
 185
 186     pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
 187                                             pci_grackle_config_write, s);
 188     pci_mem_data = cpu_register_io_memory(pci_grackle_read,
 189                                           pci_grackle_write,
 190                                           &s->host_state);
 191     sysbus_init_mmio(dev, 0x1000, pci_mem_config);
 192     sysbus_init_mmio(dev, 0x1000, pci_mem_data);
 193     return 0;
 194 }
 195
 196 static int grackle_pci_host_init(PCIDevice *d)
 197 {
 198     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
 199     pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
 200     d->config[0x08] = 0x00; // revision
 201     d->config[0x09] = 0x01;
 202     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 203     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 204     return 0;
 205 }
 206
 207 static int dec_21154_pci_host_init(PCIDevice *d)
 208 {
 209     /* PCI2PCI bridge same values as PearPC - check this */
 210     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
 211     pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
 212     d->config[0x08] = 0x02; // revision
 213     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
 214     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
 215
 216     d->config[0x18] = 0x0;  // primary_bus
 217     d->config[0x19] = 0x1;  // secondary_bus
 218     d->config[0x1a] = 0x1;  // subordinate_bus
 219     d->config[0x1c] = 0x10; // io_base
 220     d->config[0x1d] = 0x20; // io_limit
 221
 222     d->config[0x20] = 0x80; // memory_base
 223     d->config[0x21] = 0x80;
 224     d->config[0x22] = 0x90; // memory_limit
 225     d->config[0x23] = 0x80;
 226
 227     d->config[0x24] = 0x00; // prefetchable_memory_base
 228     d->config[0x25] = 0x84;
 229     d->config[0x26] = 0x00; // prefetchable_memory_limit
 230     d->config[0x27] = 0x85;
 231     return 0;
 232 }
 233
 234 static PCIDeviceInfo grackle_pci_host_info = {
 235     .qdev.name = "grackle",
 236     .qdev.size = sizeof(PCIDevice),
 237     .init      = grackle_pci_host_init,
 238 };
 239
 240 static PCIDeviceInfo dec_21154_pci_host_info = {
 241     .qdev.name = "DEC 21154",
 242     .qdev.size = sizeof(PCIDevice),
 243     .init      = dec_21154_pci_host_init,
 244 };
 245
 246 static void grackle_register_devices(void)
 247 {
 248     sysbus_register_dev("grackle", sizeof(GrackleState),
 249                         pci_grackle_init_device);
 250     pci_qdev_register(&grackle_pci_host_info);
 251     sysbus_register_dev("DEC 21154", sizeof(GrackleState),
 252                         pci_dec_21154_init_device);
 253     pci_qdev_register(&dec_21154_pci_host_info);
 254 }
 255
 256 device_init(grackle_register_devices)