hw/eccmemctl.c

   1 /*
   2  * QEMU Sparc Sun4m ECC memory controller emulation
   3  *
   4  * Copyright (c) 2007 Robert Reif
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26
  27 //#define DEBUG_ECC
  28
  29 #ifdef DEBUG_ECC
  30 #define DPRINTF(fmt, ...)                                       \
  31     do { printf("ECC: " fmt , ## __VA_ARGS__); } while (0)
  32 #else
  33 #define DPRINTF(fmt, ...)
  34 #endif
  35
  36 /* There are 3 versions of this chip used in SMP sun4m systems:
  37  * MCC (version 0, implementation 0) SS-600MP
  38  * EMC (version 0, implementation 1) SS-10
  39  * SMC (version 0, implementation 2) SS-10SX and SS-20
  40  *
  41  * Chipset docs:
  42  * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
  43  * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
  44  */
  45
  46 #define ECC_MCC        0x00000000
  47 #define ECC_EMC        0x10000000
  48 #define ECC_SMC        0x20000000
  49
  50 /* Register indexes */
  51 #define ECC_MER        0               /* Memory Enable Register */
  52 #define ECC_MDR        1               /* Memory Delay Register */
  53 #define ECC_MFSR       2               /* Memory Fault Status Register */
  54 #define ECC_VCR        3               /* Video Configuration Register */
  55 #define ECC_MFAR0      4               /* Memory Fault Address Register 0 */
  56 #define ECC_MFAR1      5               /* Memory Fault Address Register 1 */
  57 #define ECC_DR         6               /* Diagnostic Register */
  58 #define ECC_ECR0       7               /* Event Count Register 0 */
  59 #define ECC_ECR1       8               /* Event Count Register 1 */
  60
  61 /* ECC fault control register */
  62 #define ECC_MER_EE     0x00000001      /* Enable ECC checking */
  63 #define ECC_MER_EI     0x00000002      /* Enable Interrupts on
  64                                           correctable errors */
  65 #define ECC_MER_MRR0   0x00000004      /* SIMM 0 */
  66 #define ECC_MER_MRR1   0x00000008      /* SIMM 1 */
  67 #define ECC_MER_MRR2   0x00000010      /* SIMM 2 */
  68 #define ECC_MER_MRR3   0x00000020      /* SIMM 3 */
  69 #define ECC_MER_MRR4   0x00000040      /* SIMM 4 */
  70 #define ECC_MER_MRR5   0x00000080      /* SIMM 5 */
  71 #define ECC_MER_MRR6   0x00000100      /* SIMM 6 */
  72 #define ECC_MER_MRR7   0x00000200      /* SIMM 7 */
  73 #define ECC_MER_REU    0x00000100      /* Memory Refresh Enable (600MP) */
  74 #define ECC_MER_MRR    0x000003fc      /* MRR mask */
  75 #define ECC_MER_A      0x00000400      /* Memory controller addr map select */
  76 #define ECC_MER_DCI    0x00000800      /* Disables Coherent Invalidate ACK */
  77 #define ECC_MER_VER    0x0f000000      /* Version */
  78 #define ECC_MER_IMPL   0xf0000000      /* Implementation */
  79 #define ECC_MER_MASK_0 0x00000103      /* Version 0 (MCC) mask */
  80 #define ECC_MER_MASK_1 0x00000bff      /* Version 1 (EMC) mask */
  81 #define ECC_MER_MASK_2 0x00000bff      /* Version 2 (SMC) mask */
  82
  83 /* ECC memory delay register */
  84 #define ECC_MDR_RRI    0x000003ff      /* Refresh Request Interval */
  85 #define ECC_MDR_MI     0x00001c00      /* MIH Delay */
  86 #define ECC_MDR_CI     0x0000e000      /* Coherent Invalidate Delay */
  87 #define ECC_MDR_MDL    0x001f0000      /* MBus Master arbitration delay */
  88 #define ECC_MDR_MDH    0x03e00000      /* MBus Master arbitration delay */
  89 #define ECC_MDR_GAD    0x7c000000      /* Graphics Arbitration Delay */
  90 #define ECC_MDR_RSC    0x80000000      /* Refresh load control */
  91 #define ECC_MDR_MASK   0x7fffffff
  92
  93 /* ECC fault status register */
  94 #define ECC_MFSR_CE    0x00000001      /* Correctable error */
  95 #define ECC_MFSR_BS    0x00000002      /* C2 graphics bad slot access */
  96 #define ECC_MFSR_TO    0x00000004      /* Timeout on write */
  97 #define ECC_MFSR_UE    0x00000008      /* Uncorrectable error */
  98 #define ECC_MFSR_DW    0x000000f0      /* Index of double word in block */
  99 #define ECC_MFSR_SYND  0x0000ff00      /* Syndrome for correctable error */
 100 #define ECC_MFSR_ME    0x00010000      /* Multiple errors */
 101 #define ECC_MFSR_C2ERR 0x00020000      /* C2 graphics error */
 102
 103 /* ECC fault address register 0 */
 104 #define ECC_MFAR0_PADDR 0x0000000f     /* PA[32-35] */
 105 #define ECC_MFAR0_TYPE  0x000000f0     /* Transaction type */
 106 #define ECC_MFAR0_SIZE  0x00000700     /* Transaction size */
 107 #define ECC_MFAR0_CACHE 0x00000800     /* Mapped cacheable */
 108 #define ECC_MFAR0_LOCK  0x00001000     /* Error occurred in atomic cycle */
 109 #define ECC_MFAR0_BMODE 0x00002000     /* Boot mode */
 110 #define ECC_MFAR0_VADDR 0x003fc000     /* VA[12-19] (superset bits) */
 111 #define ECC_MFAR0_S     0x08000000     /* Supervisor mode */
 112 #define ECC_MFARO_MID   0xf0000000     /* Module ID */
 113
 114 /* ECC diagnostic register */
 115 #define ECC_DR_CBX     0x00000001
 116 #define ECC_DR_CB0     0x00000002
 117 #define ECC_DR_CB1     0x00000004
 118 #define ECC_DR_CB2     0x00000008
 119 #define ECC_DR_CB4     0x00000010
 120 #define ECC_DR_CB8     0x00000020
 121 #define ECC_DR_CB16    0x00000040
 122 #define ECC_DR_CB32    0x00000080
 123 #define ECC_DR_DMODE   0x00000c00
 124
 125 #define ECC_NREGS      9
 126 #define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))
 127
 128 #define ECC_DIAG_SIZE  4
 129 #define ECC_DIAG_MASK  (ECC_DIAG_SIZE - 1)
 130
 131 typedef struct ECCState {
 132     SysBusDevice busdev;
 133     qemu_irq irq;
 134     uint32_t regs[ECC_NREGS];
 135     uint8_t diag[ECC_DIAG_SIZE];
 136     uint32_t version;
 137 } ECCState;
 138
 139 static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 140 {
 141     ECCState *s = opaque;
 142
 143     switch (addr >> 2) {
 144     case ECC_MER:
 145         if (s->version == ECC_MCC)
 146             s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
 147         else if (s->version == ECC_EMC)
 148             s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1);
 149         else if (s->version == ECC_SMC)
 150             s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2);
 151         DPRINTF("Write memory enable %08x\n", val);
 152         break;
 153     case ECC_MDR:
 154         s->regs[ECC_MDR] =  val & ECC_MDR_MASK;
 155         DPRINTF("Write memory delay %08x\n", val);
 156         break;
 157     case ECC_MFSR:
 158         s->regs[ECC_MFSR] =  val;
 159         qemu_irq_lower(s->irq);
 160         DPRINTF("Write memory fault status %08x\n", val);
 161         break;
 162     case ECC_VCR:
 163         s->regs[ECC_VCR] =  val;
 164         DPRINTF("Write slot configuration %08x\n", val);
 165         break;
 166     case ECC_DR:
 167         s->regs[ECC_DR] =  val;
 168         DPRINTF("Write diagnostic %08x\n", val);
 169         break;
 170     case ECC_ECR0:
 171         s->regs[ECC_ECR0] =  val;
 172         DPRINTF("Write event count 1 %08x\n", val);
 173         break;
 174     case ECC_ECR1:
 175         s->regs[ECC_ECR0] =  val;
 176         DPRINTF("Write event count 2 %08x\n", val);
 177         break;
 178     }
 179 }
 180
 181 static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
 182 {
 183     ECCState *s = opaque;
 184     uint32_t ret = 0;
 185
 186     switch (addr >> 2) {
 187     case ECC_MER:
 188         ret = s->regs[ECC_MER];
 189         DPRINTF("Read memory enable %08x\n", ret);
 190         break;
 191     case ECC_MDR:
 192         ret = s->regs[ECC_MDR];
 193         DPRINTF("Read memory delay %08x\n", ret);
 194         break;
 195     case ECC_MFSR:
 196         ret = s->regs[ECC_MFSR];
 197         DPRINTF("Read memory fault status %08x\n", ret);
 198         break;
 199     case ECC_VCR:
 200         ret = s->regs[ECC_VCR];
 201         DPRINTF("Read slot configuration %08x\n", ret);
 202         break;
 203     case ECC_MFAR0:
 204         ret = s->regs[ECC_MFAR0];
 205         DPRINTF("Read memory fault address 0 %08x\n", ret);
 206         break;
 207     case ECC_MFAR1:
 208         ret = s->regs[ECC_MFAR1];
 209         DPRINTF("Read memory fault address 1 %08x\n", ret);
 210         break;
 211     case ECC_DR:
 212         ret = s->regs[ECC_DR];
 213         DPRINTF("Read diagnostic %08x\n", ret);
 214         break;
 215     case ECC_ECR0:
 216         ret = s->regs[ECC_ECR0];
 217         DPRINTF("Read event count 1 %08x\n", ret);
 218         break;
 219     case ECC_ECR1:
 220         ret = s->regs[ECC_ECR0];
 221         DPRINTF("Read event count 2 %08x\n", ret);
 222         break;
 223     }
 224     return ret;
 225 }
 226
 227 static CPUReadMemoryFunc * const ecc_mem_read[3] = {
 228     NULL,
 229     NULL,
 230     ecc_mem_readl,
 231 };
 232
 233 static CPUWriteMemoryFunc * const ecc_mem_write[3] = {
 234     NULL,
 235     NULL,
 236     ecc_mem_writel,
 237 };
 238
 239 static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
 240                                 uint32_t val)
 241 {
 242     ECCState *s = opaque;
 243
 244     DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val);
 245     s->diag[addr & ECC_DIAG_MASK] = val;
 246 }
 247
 248 static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
 249 {
 250     ECCState *s = opaque;
 251     uint32_t ret = s->diag[(int)addr];
 252
 253     DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret);
 254     return ret;
 255 }
 256
 257 static CPUReadMemoryFunc * const ecc_diag_mem_read[3] = {
 258     ecc_diag_mem_readb,
 259     NULL,
 260     NULL,
 261 };
 262
 263 static CPUWriteMemoryFunc * const ecc_diag_mem_write[3] = {
 264     ecc_diag_mem_writeb,
 265     NULL,
 266     NULL,
 267 };
 268
 269 static const VMStateDescription vmstate_ecc = {
 270     .name ="ECC",
 271     .version_id = 3,
 272     .minimum_version_id = 3,
 273     .minimum_version_id_old = 3,
 274     .fields      = (VMStateField []) {
 275         VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS),
 276         VMSTATE_BUFFER(diag, ECCState),
 277         VMSTATE_UINT32(version, ECCState),
 278         VMSTATE_END_OF_LIST()
 279     }
 280 };
 281
 282 static void ecc_reset(DeviceState *d)
 283 {
 284     ECCState *s = container_of(d, ECCState, busdev.qdev);
 285
 286     if (s->version == ECC_MCC)
 287         s->regs[ECC_MER] &= ECC_MER_REU;
 288     else
 289         s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |
 290                              ECC_MER_DCI);
 291     s->regs[ECC_MDR] = 0x20;
 292     s->regs[ECC_MFSR] = 0;
 293     s->regs[ECC_VCR] = 0;
 294     s->regs[ECC_MFAR0] = 0x07c00000;
 295     s->regs[ECC_MFAR1] = 0;
 296     s->regs[ECC_DR] = 0;
 297     s->regs[ECC_ECR0] = 0;
 298     s->regs[ECC_ECR1] = 0;
 299 }
 300
 301 static int ecc_init1(SysBusDevice *dev)
 302 {
 303     int ecc_io_memory;
 304     ECCState *s = FROM_SYSBUS(ECCState, dev);
 305
 306     sysbus_init_irq(dev, &s->irq);
 307     s->regs[0] = s->version;
 308     ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s);
 309     sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory);
 310
 311     if (s->version == ECC_MCC) { // SS-600MP only
 312         ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read,
 313                                                ecc_diag_mem_write, s);
 314         sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory);
 315     }
 316     ecc_reset(&s->busdev.qdev);
 317
 318     return 0;
 319 }
 320
 321 static SysBusDeviceInfo ecc_info = {
 322     .init = ecc_init1,
 323     .qdev.name  = "eccmemctl",
 324     .qdev.size  = sizeof(ECCState),
 325     .qdev.vmsd  = &vmstate_ecc,
 326     .qdev.reset = ecc_reset,
 327     .qdev.props = (Property[]) {
 328         DEFINE_PROP_HEX32("version", ECCState, version, -1),
 329         DEFINE_PROP_END_OF_LIST(),
 330     }
 331 };
 332
 333
 334 static void ecc_register_devices(void)
 335 {
 336     sysbus_register_withprop(&ecc_info);
 337 }
 338
 339 device_init(ecc_register_devices)