hw/cs4231.c

   1 /*
   2  * QEMU Crystal CS4231 audio chip emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26
  27 /* debug CS4231 */
  28 //#define DEBUG_CS
  29
  30 /*
  31  * In addition to Crystal CS4231 there is a DMA controller on Sparc.
  32  */
  33 #define CS_SIZE 0x40
  34 #define CS_REGS 16
  35 #define CS_DREGS 32
  36 #define CS_MAXDREG (CS_DREGS - 1)
  37
  38 typedef struct CSState {
  39     SysBusDevice busdev;
  40     qemu_irq irq;
  41     uint32_t regs[CS_REGS];
  42     uint8_t dregs[CS_DREGS];
  43 } CSState;
  44
  45 #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
  46 #define CS_VER 0xa0
  47 #define CS_CDC_VER 0x8a
  48
  49 #ifdef DEBUG_CS
  50 #define DPRINTF(fmt, ...)                                       \
  51     do { printf("CS: " fmt , ## __VA_ARGS__); } while (0)
  52 #else
  53 #define DPRINTF(fmt, ...)
  54 #endif
  55
  56 static void cs_reset(DeviceState *d)
  57 {
  58     CSState *s = container_of(d, CSState, busdev.qdev);
  59
  60     memset(s->regs, 0, CS_REGS * 4);
  61     memset(s->dregs, 0, CS_DREGS);
  62     s->dregs[12] = CS_CDC_VER;
  63     s->dregs[25] = CS_VER;
  64 }
  65
  66 static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
  67 {
  68     CSState *s = opaque;
  69     uint32_t saddr, ret;
  70
  71     saddr = addr >> 2;
  72     switch (saddr) {
  73     case 1:
  74         switch (CS_RAP(s)) {
  75         case 3: // Write only
  76             ret = 0;
  77             break;
  78         default:
  79             ret = s->dregs[CS_RAP(s)];
  80             break;
  81         }
  82         DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
  83         break;
  84     default:
  85         ret = s->regs[saddr];
  86         DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
  87         break;
  88     }
  89     return ret;
  90 }
  91
  92 static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  93 {
  94     CSState *s = opaque;
  95     uint32_t saddr;
  96
  97     saddr = addr >> 2;
  98     DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
  99     switch (saddr) {
 100     case 1:
 101         DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s),
 102                 s->dregs[CS_RAP(s)], val);
 103         switch(CS_RAP(s)) {
 104         case 11:
 105         case 25: // Read only
 106             break;
 107         case 12:
 108             val &= 0x40;
 109             val |= CS_CDC_VER; // Codec version
 110             s->dregs[CS_RAP(s)] = val;
 111             break;
 112         default:
 113             s->dregs[CS_RAP(s)] = val;
 114             break;
 115         }
 116         break;
 117     case 2: // Read only
 118         break;
 119     case 4:
 120         if (val & 1) {
 121             cs_reset(&s->busdev.qdev);
 122         }
 123         val &= 0x7f;
 124         s->regs[saddr] = val;
 125         break;
 126     default:
 127         s->regs[saddr] = val;
 128         break;
 129     }
 130 }
 131
 132 static CPUReadMemoryFunc * const cs_mem_read[3] = {
 133     cs_mem_readl,
 134     cs_mem_readl,
 135     cs_mem_readl,
 136 };
 137
 138 static CPUWriteMemoryFunc * const cs_mem_write[3] = {
 139     cs_mem_writel,
 140     cs_mem_writel,
 141     cs_mem_writel,
 142 };
 143
 144 static const VMStateDescription vmstate_cs4231 = {
 145     .name ="cs4231",
 146     .version_id = 1,
 147     .minimum_version_id = 1,
 148     .minimum_version_id_old = 1,
 149     .fields      = (VMStateField []) {
 150         VMSTATE_UINT32_ARRAY(regs, CSState, CS_REGS),
 151         VMSTATE_UINT8_ARRAY(dregs, CSState, CS_DREGS),
 152         VMSTATE_END_OF_LIST()
 153     }
 154 };
 155
 156 static int cs4231_init1(SysBusDevice *dev)
 157 {
 158     int io;
 159     CSState *s = FROM_SYSBUS(CSState, dev);
 160
 161     io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s);
 162     sysbus_init_mmio(dev, CS_SIZE, io);
 163     sysbus_init_irq(dev, &s->irq);
 164
 165     cs_reset(&s->busdev.qdev);
 166     return 0;
 167 }
 168
 169 static SysBusDeviceInfo cs4231_info = {
 170     .init = cs4231_init1,
 171     .qdev.name  = "SUNW,CS4231",
 172     .qdev.size  = sizeof(CSState),
 173     .qdev.vmsd  = &vmstate_cs4231,
 174     .qdev.reset = cs_reset,
 175     .qdev.props = (Property[]) {
 176         {.name = NULL}
 177     }
 178 };
 179
 180 static void cs4231_register_devices(void)
 181 {
 182     sysbus_register_withprop(&cs4231_info);
 183 }
 184
 185 device_init(cs4231_register_devices)