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qdev: integrate reset
[armpft.git] / target-cris / translate.c
blobbd3ae3d7633a4c05b66367443788d4270d4b6e34
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include <stdarg.h>
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <string.h>
30 #include <inttypes.h>
31
32 #include "cpu.h"
33 #include "exec-all.h"
34 #include "disas.h"
35 #include "tcg-op.h"
36 #include "helper.h"
37 #include "mmu.h"
38 #include "crisv32-decode.h"
39 #include "qemu-common.h"
40
41 #define GEN_HELPER 1
42 #include "helper.h"
43
44 #define DISAS_CRIS 0
45 #if DISAS_CRIS
46 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DIS(...) do { } while (0)
49 #endif
50
51 #define D(x)
52 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
53 #define BUG_ON(x) ({if (x) BUG();})
54
55 #define DISAS_SWI 5
56
57 /* Used by the decoder. */
58 #define EXTRACT_FIELD(src, start, end) \
59 (((src) >> start) & ((1 << (end - start + 1)) - 1))
60
61 #define CC_MASK_NZ 0xc
62 #define CC_MASK_NZV 0xe
63 #define CC_MASK_NZVC 0xf
64 #define CC_MASK_RNZV 0x10e
65
66 static TCGv_ptr cpu_env;
67 static TCGv cpu_R[16];
68 static TCGv cpu_PR[16];
69 static TCGv cc_x;
70 static TCGv cc_src;
71 static TCGv cc_dest;
72 static TCGv cc_result;
73 static TCGv cc_op;
74 static TCGv cc_size;
75 static TCGv cc_mask;
76
77 static TCGv env_btaken;
78 static TCGv env_btarget;
79 static TCGv env_pc;
80
81 #include "gen-icount.h"
82
83 /* This is the state at translation time. */
84 typedef struct DisasContext {
85 CPUState *env;
86 target_ulong pc, ppc;
87
88 /* Decoder. */
89 uint32_t ir;
90 uint32_t opcode;
91 unsigned int op1;
92 unsigned int op2;
93 unsigned int zsize, zzsize;
94 unsigned int mode;
95 unsigned int postinc;
96
97 int update_cc;
98 int cc_op;
99 int cc_size;
100 uint32_t cc_mask;
101
102 int cc_size_uptodate; /* -1 invalid or last written value. */
103
104 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
105 int flags_uptodate; /* Wether or not $ccs is uptodate. */
106 int flagx_known; /* Wether or not flags_x has the x flag known at
107 translation time. */
108 int flags_x;
109
110 int clear_x; /* Clear x after this insn? */
111 int cpustate_changed;
112 unsigned int tb_flags; /* tb dependent flags. */
113 int is_jmp;
114
115 #define JMP_NOJMP 0
116 #define JMP_DIRECT 1
117 #define JMP_INDIRECT 2
118 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
119 uint32_t jmp_pc;
120
121 int delayed_branch;
122
123 struct TranslationBlock *tb;
124 int singlestep_enabled;
125 } DisasContext;
126
127 static void gen_BUG(DisasContext *dc, const char *file, int line)
128 {
129 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
130 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
131 cpu_abort(dc->env, "%s:%d\n", file, line);
132 }
133
134 static const char *regnames[] =
135 {
136 "$r0", "$r1", "$r2", "$r3",
137 "$r4", "$r5", "$r6", "$r7",
138 "$r8", "$r9", "$r10", "$r11",
139 "$r12", "$r13", "$sp", "$acr",
140 };
141 static const char *pregnames[] =
142 {
143 "$bz", "$vr", "$pid", "$srs",
144 "$wz", "$exs", "$eda", "$mof",
145 "$dz", "$ebp", "$erp", "$srp",
146 "$nrp", "$ccs", "$usp", "$spc",
147 };
148
149 /* We need this table to handle preg-moves with implicit width. */
150 static int preg_sizes[] = {
151 1, /* bz. */
152 1, /* vr. */
153 4, /* pid. */
154 1, /* srs. */
155 2, /* wz. */
156 4, 4, 4,
157 4, 4, 4, 4,
158 4, 4, 4, 4,
159 };
160
161 #define t_gen_mov_TN_env(tn, member) \
162 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
163 #define t_gen_mov_env_TN(member, tn) \
164 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
165
166 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
167 {
168 if (r < 0 || r > 15)
169 fprintf(stderr, "wrong register read $r%d\n", r);
170 tcg_gen_mov_tl(tn, cpu_R[r]);
171 }
172 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
173 {
174 if (r < 0 || r > 15)
175 fprintf(stderr, "wrong register write $r%d\n", r);
176 tcg_gen_mov_tl(cpu_R[r], tn);
177 }
178
179 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
180 {
181 if (offset > sizeof (CPUState))
182 fprintf(stderr, "wrong load from env from off=%d\n", offset);
183 tcg_gen_ld_tl(tn, cpu_env, offset);
184 }
185 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
186 {
187 if (offset > sizeof (CPUState))
188 fprintf(stderr, "wrong store to env at off=%d\n", offset);
189 tcg_gen_st_tl(tn, cpu_env, offset);
190 }
191
192 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
193 {
194 if (r < 0 || r > 15)
195 fprintf(stderr, "wrong register read $p%d\n", r);
196 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
197 tcg_gen_mov_tl(tn, tcg_const_tl(0));
198 else if (r == PR_VR)
199 tcg_gen_mov_tl(tn, tcg_const_tl(32));
200 else if (r == PR_EDA) {
201 printf("read from EDA!\n");
202 tcg_gen_mov_tl(tn, cpu_PR[r]);
203 }
204 else
205 tcg_gen_mov_tl(tn, cpu_PR[r]);
206 }
207 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
208 {
209 if (r < 0 || r > 15)
210 fprintf(stderr, "wrong register write $p%d\n", r);
211 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
212 return;
213 else if (r == PR_SRS)
214 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
215 else {
216 if (r == PR_PID)
217 gen_helper_tlb_flush_pid(tn);
218 if (dc->tb_flags & S_FLAG && r == PR_SPC)
219 gen_helper_spc_write(tn);
220 else if (r == PR_CCS)
221 dc->cpustate_changed = 1;
222 tcg_gen_mov_tl(cpu_PR[r], tn);
223 }
224 }
225
226 static inline void t_gen_raise_exception(uint32_t index)
227 {
228 TCGv_i32 tmp = tcg_const_i32(index);
229 gen_helper_raise_exception(tmp);
230 tcg_temp_free_i32(tmp);
231 }
232
233 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
234 {
235 TCGv t0, t_31;
236
237 t0 = tcg_temp_new();
238 t_31 = tcg_const_tl(31);
239 tcg_gen_shl_tl(d, a, b);
240
241 tcg_gen_sub_tl(t0, t_31, b);
242 tcg_gen_sar_tl(t0, t0, t_31);
243 tcg_gen_and_tl(t0, t0, d);
244 tcg_gen_xor_tl(d, d, t0);
245 tcg_temp_free(t0);
246 tcg_temp_free(t_31);
247 }
248
249 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
250 {
251 TCGv t0, t_31;
252
253 t0 = tcg_temp_new();
254 t_31 = tcg_temp_new();
255 tcg_gen_shr_tl(d, a, b);
256
257 tcg_gen_movi_tl(t_31, 31);
258 tcg_gen_sub_tl(t0, t_31, b);
259 tcg_gen_sar_tl(t0, t0, t_31);
260 tcg_gen_and_tl(t0, t0, d);
261 tcg_gen_xor_tl(d, d, t0);
262 tcg_temp_free(t0);
263 tcg_temp_free(t_31);
264 }
265
266 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
267 {
268 TCGv t0, t_31;
269
270 t0 = tcg_temp_new();
271 t_31 = tcg_temp_new();
272 tcg_gen_sar_tl(d, a, b);
273
274 tcg_gen_movi_tl(t_31, 31);
275 tcg_gen_sub_tl(t0, t_31, b);
276 tcg_gen_sar_tl(t0, t0, t_31);
277 tcg_gen_or_tl(d, d, t0);
278 tcg_temp_free(t0);
279 tcg_temp_free(t_31);
280 }
281
282 /* 64-bit signed mul, lower result in d and upper in d2. */
283 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
284 {
285 TCGv_i64 t0, t1;
286
287 t0 = tcg_temp_new_i64();
288 t1 = tcg_temp_new_i64();
289
290 tcg_gen_ext_i32_i64(t0, a);
291 tcg_gen_ext_i32_i64(t1, b);
292 tcg_gen_mul_i64(t0, t0, t1);
293
294 tcg_gen_trunc_i64_i32(d, t0);
295 tcg_gen_shri_i64(t0, t0, 32);
296 tcg_gen_trunc_i64_i32(d2, t0);
297
298 tcg_temp_free_i64(t0);
299 tcg_temp_free_i64(t1);
300 }
301
302 /* 64-bit unsigned muls, lower result in d and upper in d2. */
303 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
304 {
305 TCGv_i64 t0, t1;
306
307 t0 = tcg_temp_new_i64();
308 t1 = tcg_temp_new_i64();
309
310 tcg_gen_extu_i32_i64(t0, a);
311 tcg_gen_extu_i32_i64(t1, b);
312 tcg_gen_mul_i64(t0, t0, t1);
313
314 tcg_gen_trunc_i64_i32(d, t0);
315 tcg_gen_shri_i64(t0, t0, 32);
316 tcg_gen_trunc_i64_i32(d2, t0);
317
318 tcg_temp_free_i64(t0);
319 tcg_temp_free_i64(t1);
320 }
321
322 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
323 {
324 int l1;
325
326 l1 = gen_new_label();
327
328 /*
329 * d <<= 1
330 * if (d >= s)
331 * d -= s;
332 */
333 tcg_gen_shli_tl(d, a, 1);
334 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
335 tcg_gen_sub_tl(d, d, b);
336 gen_set_label(l1);
337 }
338
339 /* Extended arithmetics on CRIS. */
340 static inline void t_gen_add_flag(TCGv d, int flag)
341 {
342 TCGv c;
343
344 c = tcg_temp_new();
345 t_gen_mov_TN_preg(c, PR_CCS);
346 /* Propagate carry into d. */
347 tcg_gen_andi_tl(c, c, 1 << flag);
348 if (flag)
349 tcg_gen_shri_tl(c, c, flag);
350 tcg_gen_add_tl(d, d, c);
351 tcg_temp_free(c);
352 }
353
354 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
355 {
356 if (dc->flagx_known) {
357 if (dc->flags_x) {
358 TCGv c;
359
360 c = tcg_temp_new();
361 t_gen_mov_TN_preg(c, PR_CCS);
362 /* C flag is already at bit 0. */
363 tcg_gen_andi_tl(c, c, C_FLAG);
364 tcg_gen_add_tl(d, d, c);
365 tcg_temp_free(c);
366 }
367 } else {
368 TCGv x, c;
369
370 x = tcg_temp_new();
371 c = tcg_temp_new();
372 t_gen_mov_TN_preg(x, PR_CCS);
373 tcg_gen_mov_tl(c, x);
374
375 /* Propagate carry into d if X is set. Branch free. */
376 tcg_gen_andi_tl(c, c, C_FLAG);
377 tcg_gen_andi_tl(x, x, X_FLAG);
378 tcg_gen_shri_tl(x, x, 4);
379
380 tcg_gen_and_tl(x, x, c);
381 tcg_gen_add_tl(d, d, x);
382 tcg_temp_free(x);
383 tcg_temp_free(c);
384 }
385 }
386
387 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
388 {
389 if (dc->flagx_known) {
390 if (dc->flags_x) {
391 TCGv c;
392
393 c = tcg_temp_new();
394 t_gen_mov_TN_preg(c, PR_CCS);
395 /* C flag is already at bit 0. */
396 tcg_gen_andi_tl(c, c, C_FLAG);
397 tcg_gen_sub_tl(d, d, c);
398 tcg_temp_free(c);
399 }
400 } else {
401 TCGv x, c;
402
403 x = tcg_temp_new();
404 c = tcg_temp_new();
405 t_gen_mov_TN_preg(x, PR_CCS);
406 tcg_gen_mov_tl(c, x);
407
408 /* Propagate carry into d if X is set. Branch free. */
409 tcg_gen_andi_tl(c, c, C_FLAG);
410 tcg_gen_andi_tl(x, x, X_FLAG);
411 tcg_gen_shri_tl(x, x, 4);
412
413 tcg_gen_and_tl(x, x, c);
414 tcg_gen_sub_tl(d, d, x);
415 tcg_temp_free(x);
416 tcg_temp_free(c);
417 }
418 }
419
420 /* Swap the two bytes within each half word of the s operand.
421 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
422 static inline void t_gen_swapb(TCGv d, TCGv s)
423 {
424 TCGv t, org_s;
425
426 t = tcg_temp_new();
427 org_s = tcg_temp_new();
428
429 /* d and s may refer to the same object. */
430 tcg_gen_mov_tl(org_s, s);
431 tcg_gen_shli_tl(t, org_s, 8);
432 tcg_gen_andi_tl(d, t, 0xff00ff00);
433 tcg_gen_shri_tl(t, org_s, 8);
434 tcg_gen_andi_tl(t, t, 0x00ff00ff);
435 tcg_gen_or_tl(d, d, t);
436 tcg_temp_free(t);
437 tcg_temp_free(org_s);
438 }
439
440 /* Swap the halfwords of the s operand. */
441 static inline void t_gen_swapw(TCGv d, TCGv s)
442 {
443 TCGv t;
444 /* d and s refer the same object. */
445 t = tcg_temp_new();
446 tcg_gen_mov_tl(t, s);
447 tcg_gen_shli_tl(d, t, 16);
448 tcg_gen_shri_tl(t, t, 16);
449 tcg_gen_or_tl(d, d, t);
450 tcg_temp_free(t);
451 }
452
453 /* Reverse the within each byte.
454 T0 = (((T0 << 7) & 0x80808080) |
455 ((T0 << 5) & 0x40404040) |
456 ((T0 << 3) & 0x20202020) |
457 ((T0 << 1) & 0x10101010) |
458 ((T0 >> 1) & 0x08080808) |
459 ((T0 >> 3) & 0x04040404) |
460 ((T0 >> 5) & 0x02020202) |
461 ((T0 >> 7) & 0x01010101));
462 */
463 static inline void t_gen_swapr(TCGv d, TCGv s)
464 {
465 struct {
466 int shift; /* LSL when positive, LSR when negative. */
467 uint32_t mask;
468 } bitrev [] = {
469 {7, 0x80808080},
470 {5, 0x40404040},
471 {3, 0x20202020},
472 {1, 0x10101010},
473 {-1, 0x08080808},
474 {-3, 0x04040404},
475 {-5, 0x02020202},
476 {-7, 0x01010101}
477 };
478 int i;
479 TCGv t, org_s;
480
481 /* d and s refer the same object. */
482 t = tcg_temp_new();
483 org_s = tcg_temp_new();
484 tcg_gen_mov_tl(org_s, s);
485
486 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
487 tcg_gen_andi_tl(d, t, bitrev[0].mask);
488 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
489 if (bitrev[i].shift >= 0) {
490 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
491 } else {
492 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
493 }
494 tcg_gen_andi_tl(t, t, bitrev[i].mask);
495 tcg_gen_or_tl(d, d, t);
496 }
497 tcg_temp_free(t);
498 tcg_temp_free(org_s);
499 }
500
501 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
502 {
503 TCGv btaken;
504 int l1;
505
506 l1 = gen_new_label();
507 btaken = tcg_temp_new();
508
509 /* Conditional jmp. */
510 tcg_gen_mov_tl(btaken, env_btaken);
511 tcg_gen_mov_tl(env_pc, pc_false);
512 tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
513 tcg_gen_mov_tl(env_pc, pc_true);
514 gen_set_label(l1);
515
516 tcg_temp_free(btaken);
517 }
518
519 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
520 {
521 TranslationBlock *tb;
522 tb = dc->tb;
523 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
524 tcg_gen_goto_tb(n);
525 tcg_gen_movi_tl(env_pc, dest);
526 tcg_gen_exit_tb((long)tb + n);
527 } else {
528 tcg_gen_movi_tl(env_pc, dest);
529 tcg_gen_exit_tb(0);
530 }
531 }
532
533 /* Sign extend at translation time. */
534 static int sign_extend(unsigned int val, unsigned int width)
535 {
536 int sval;
537
538 /* LSL. */
539 val <<= 31 - width;
540 sval = val;
541 /* ASR. */
542 sval >>= 31 - width;
543 return sval;
544 }
545
546 static inline void cris_clear_x_flag(DisasContext *dc)
547 {
548 if (dc->flagx_known && dc->flags_x)
549 dc->flags_uptodate = 0;
550
551 dc->flagx_known = 1;
552 dc->flags_x = 0;
553 }
554
555 static void cris_flush_cc_state(DisasContext *dc)
556 {
557 if (dc->cc_size_uptodate != dc->cc_size) {
558 tcg_gen_movi_tl(cc_size, dc->cc_size);
559 dc->cc_size_uptodate = dc->cc_size;
560 }
561 tcg_gen_movi_tl(cc_op, dc->cc_op);
562 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
563 }
564
565 static void cris_evaluate_flags(DisasContext *dc)
566 {
567 if (dc->flags_uptodate)
568 return;
569
570 cris_flush_cc_state(dc);
571
572 switch (dc->cc_op)
573 {
574 case CC_OP_MCP:
575 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
576 cpu_PR[PR_CCS], cc_src,
577 cc_dest, cc_result);
578 break;
579 case CC_OP_MULS:
580 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
581 cpu_PR[PR_CCS], cc_result,
582 cpu_PR[PR_MOF]);
583 break;
584 case CC_OP_MULU:
585 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
586 cpu_PR[PR_CCS], cc_result,
587 cpu_PR[PR_MOF]);
588 break;
589 case CC_OP_MOVE:
590 case CC_OP_AND:
591 case CC_OP_OR:
592 case CC_OP_XOR:
593 case CC_OP_ASR:
594 case CC_OP_LSR:
595 case CC_OP_LSL:
596 switch (dc->cc_size)
597 {
598 case 4:
599 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
600 cpu_PR[PR_CCS], cc_result);
601 break;
602 case 2:
603 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
604 cpu_PR[PR_CCS], cc_result);
605 break;
606 default:
607 gen_helper_evaluate_flags();
608 break;
609 }
610 break;
611 case CC_OP_FLAGS:
612 /* live. */
613 break;
614 case CC_OP_SUB:
615 case CC_OP_CMP:
616 if (dc->cc_size == 4)
617 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
618 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
619 else
620 gen_helper_evaluate_flags();
621
622 break;
623 default:
624 switch (dc->cc_size)
625 {
626 case 4:
627 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
628 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
629 break;
630 default:
631 gen_helper_evaluate_flags();
632 break;
633 }
634 break;
635 }
636
637 if (dc->flagx_known) {
638 if (dc->flags_x)
639 tcg_gen_ori_tl(cpu_PR[PR_CCS],
640 cpu_PR[PR_CCS], X_FLAG);
641 else
642 tcg_gen_andi_tl(cpu_PR[PR_CCS],
643 cpu_PR[PR_CCS], ~X_FLAG);
644 }
645 dc->flags_uptodate = 1;
646 }
647
648 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
649 {
650 uint32_t ovl;
651
652 if (!mask) {
653 dc->update_cc = 0;
654 return;
655 }
656
657 /* Check if we need to evaluate the condition codes due to
658 CC overlaying. */
659 ovl = (dc->cc_mask ^ mask) & ~mask;
660 if (ovl) {
661 /* TODO: optimize this case. It trigs all the time. */
662 cris_evaluate_flags (dc);
663 }
664 dc->cc_mask = mask;
665 dc->update_cc = 1;
666 }
667
668 static void cris_update_cc_op(DisasContext *dc, int op, int size)
669 {
670 dc->cc_op = op;
671 dc->cc_size = size;
672 dc->flags_uptodate = 0;
673 }
674
675 static inline void cris_update_cc_x(DisasContext *dc)
676 {
677 /* Save the x flag state at the time of the cc snapshot. */
678 if (dc->flagx_known) {
679 if (dc->cc_x_uptodate == (2 | dc->flags_x))
680 return;
681 tcg_gen_movi_tl(cc_x, dc->flags_x);
682 dc->cc_x_uptodate = 2 | dc->flags_x;
683 }
684 else {
685 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
686 dc->cc_x_uptodate = 1;
687 }
688 }
689
690 /* Update cc prior to executing ALU op. Needs source operands untouched. */
691 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
692 TCGv dst, TCGv src, int size)
693 {
694 if (dc->update_cc) {
695 cris_update_cc_op(dc, op, size);
696 tcg_gen_mov_tl(cc_src, src);
697
698 if (op != CC_OP_MOVE
699 && op != CC_OP_AND
700 && op != CC_OP_OR
701 && op != CC_OP_XOR
702 && op != CC_OP_ASR
703 && op != CC_OP_LSR
704 && op != CC_OP_LSL)
705 tcg_gen_mov_tl(cc_dest, dst);
706
707 cris_update_cc_x(dc);
708 }
709 }
710
711 /* Update cc after executing ALU op. needs the result. */
712 static inline void cris_update_result(DisasContext *dc, TCGv res)
713 {
714 if (dc->update_cc)
715 tcg_gen_mov_tl(cc_result, res);
716 }
717
718 /* Returns one if the write back stage should execute. */
719 static void cris_alu_op_exec(DisasContext *dc, int op,
720 TCGv dst, TCGv a, TCGv b, int size)
721 {
722 /* Emit the ALU insns. */
723 switch (op)
724 {
725 case CC_OP_ADD:
726 tcg_gen_add_tl(dst, a, b);
727 /* Extended arithmetics. */
728 t_gen_addx_carry(dc, dst);
729 break;
730 case CC_OP_ADDC:
731 tcg_gen_add_tl(dst, a, b);
732 t_gen_add_flag(dst, 0); /* C_FLAG. */
733 break;
734 case CC_OP_MCP:
735 tcg_gen_add_tl(dst, a, b);
736 t_gen_add_flag(dst, 8); /* R_FLAG. */
737 break;
738 case CC_OP_SUB:
739 tcg_gen_sub_tl(dst, a, b);
740 /* Extended arithmetics. */
741 t_gen_subx_carry(dc, dst);
742 break;
743 case CC_OP_MOVE:
744 tcg_gen_mov_tl(dst, b);
745 break;
746 case CC_OP_OR:
747 tcg_gen_or_tl(dst, a, b);
748 break;
749 case CC_OP_AND:
750 tcg_gen_and_tl(dst, a, b);
751 break;
752 case CC_OP_XOR:
753 tcg_gen_xor_tl(dst, a, b);
754 break;
755 case CC_OP_LSL:
756 t_gen_lsl(dst, a, b);
757 break;
758 case CC_OP_LSR:
759 t_gen_lsr(dst, a, b);
760 break;
761 case CC_OP_ASR:
762 t_gen_asr(dst, a, b);
763 break;
764 case CC_OP_NEG:
765 tcg_gen_neg_tl(dst, b);
766 /* Extended arithmetics. */
767 t_gen_subx_carry(dc, dst);
768 break;
769 case CC_OP_LZ:
770 gen_helper_lz(dst, b);
771 break;
772 case CC_OP_MULS:
773 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
774 break;
775 case CC_OP_MULU:
776 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
777 break;
778 case CC_OP_DSTEP:
779 t_gen_cris_dstep(dst, a, b);
780 break;
781 case CC_OP_BOUND:
782 {
783 int l1;
784 l1 = gen_new_label();
785 tcg_gen_mov_tl(dst, a);
786 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
787 tcg_gen_mov_tl(dst, b);
788 gen_set_label(l1);
789 }
790 break;
791 case CC_OP_CMP:
792 tcg_gen_sub_tl(dst, a, b);
793 /* Extended arithmetics. */
794 t_gen_subx_carry(dc, dst);
795 break;
796 default:
797 qemu_log("illegal ALU op.\n");
798 BUG();
799 break;
800 }
801
802 if (size == 1)
803 tcg_gen_andi_tl(dst, dst, 0xff);
804 else if (size == 2)
805 tcg_gen_andi_tl(dst, dst, 0xffff);
806 }
807
808 static void cris_alu(DisasContext *dc, int op,
809 TCGv d, TCGv op_a, TCGv op_b, int size)
810 {
811 TCGv tmp;
812 int writeback;
813
814 writeback = 1;
815
816 if (op == CC_OP_CMP) {
817 tmp = tcg_temp_new();
818 writeback = 0;
819 } else if (size == 4) {
820 tmp = d;
821 writeback = 0;
822 } else
823 tmp = tcg_temp_new();
824
825
826 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
827 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
828 cris_update_result(dc, tmp);
829
830 /* Writeback. */
831 if (writeback) {
832 if (size == 1)
833 tcg_gen_andi_tl(d, d, ~0xff);
834 else
835 tcg_gen_andi_tl(d, d, ~0xffff);
836 tcg_gen_or_tl(d, d, tmp);
837 }
838 if (!TCGV_EQUAL(tmp, d))
839 tcg_temp_free(tmp);
840 }
841
842 static int arith_cc(DisasContext *dc)
843 {
844 if (dc->update_cc) {
845 switch (dc->cc_op) {
846 case CC_OP_ADDC: return 1;
847 case CC_OP_ADD: return 1;
848 case CC_OP_SUB: return 1;
849 case CC_OP_DSTEP: return 1;
850 case CC_OP_LSL: return 1;
851 case CC_OP_LSR: return 1;
852 case CC_OP_ASR: return 1;
853 case CC_OP_CMP: return 1;
854 case CC_OP_NEG: return 1;
855 case CC_OP_OR: return 1;
856 case CC_OP_AND: return 1;
857 case CC_OP_XOR: return 1;
858 case CC_OP_MULU: return 1;
859 case CC_OP_MULS: return 1;
860 default:
861 return 0;
862 }
863 }
864 return 0;
865 }
866
867 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
868 {
869 int arith_opt, move_opt;
870
871 /* TODO: optimize more condition codes. */
872
873 /*
874 * If the flags are live, we've gotta look into the bits of CCS.
875 * Otherwise, if we just did an arithmetic operation we try to
876 * evaluate the condition code faster.
877 *
878 * When this function is done, T0 should be non-zero if the condition
879 * code is true.
880 */
881 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
882 move_opt = (dc->cc_op == CC_OP_MOVE);
883 switch (cond) {
884 case CC_EQ:
885 if (arith_opt || move_opt) {
886 /* If cc_result is zero, T0 should be
887 non-zero otherwise T0 should be zero. */
888 int l1;
889 l1 = gen_new_label();
890 tcg_gen_movi_tl(cc, 0);
891 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
892 0, l1);
893 tcg_gen_movi_tl(cc, 1);
894 gen_set_label(l1);
895 }
896 else {
897 cris_evaluate_flags(dc);
898 tcg_gen_andi_tl(cc,
899 cpu_PR[PR_CCS], Z_FLAG);
900 }
901 break;
902 case CC_NE:
903 if (arith_opt || move_opt)
904 tcg_gen_mov_tl(cc, cc_result);
905 else {
906 cris_evaluate_flags(dc);
907 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
908 Z_FLAG);
909 tcg_gen_andi_tl(cc, cc, Z_FLAG);
910 }
911 break;
912 case CC_CS:
913 cris_evaluate_flags(dc);
914 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
915 break;
916 case CC_CC:
917 cris_evaluate_flags(dc);
918 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
919 tcg_gen_andi_tl(cc, cc, C_FLAG);
920 break;
921 case CC_VS:
922 cris_evaluate_flags(dc);
923 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
924 break;
925 case CC_VC:
926 cris_evaluate_flags(dc);
927 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
928 V_FLAG);
929 tcg_gen_andi_tl(cc, cc, V_FLAG);
930 break;
931 case CC_PL:
932 if (arith_opt || move_opt) {
933 int bits = 31;
934
935 if (dc->cc_size == 1)
936 bits = 7;
937 else if (dc->cc_size == 2)
938 bits = 15;
939
940 tcg_gen_shri_tl(cc, cc_result, bits);
941 tcg_gen_xori_tl(cc, cc, 1);
942 } else {
943 cris_evaluate_flags(dc);
944 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
945 N_FLAG);
946 tcg_gen_andi_tl(cc, cc, N_FLAG);
947 }
948 break;
949 case CC_MI:
950 if (arith_opt || move_opt) {
951 int bits = 31;
952
953 if (dc->cc_size == 1)
954 bits = 7;
955 else if (dc->cc_size == 2)
956 bits = 15;
957
958 tcg_gen_shri_tl(cc, cc_result, bits);
959 tcg_gen_andi_tl(cc, cc, 1);
960 }
961 else {
962 cris_evaluate_flags(dc);
963 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
964 N_FLAG);
965 }
966 break;
967 case CC_LS:
968 cris_evaluate_flags(dc);
969 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
970 C_FLAG | Z_FLAG);
971 break;
972 case CC_HI:
973 cris_evaluate_flags(dc);
974 {
975 TCGv tmp;
976
977 tmp = tcg_temp_new();
978 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
979 C_FLAG | Z_FLAG);
980 /* Overlay the C flag on top of the Z. */
981 tcg_gen_shli_tl(cc, tmp, 2);
982 tcg_gen_and_tl(cc, tmp, cc);
983 tcg_gen_andi_tl(cc, cc, Z_FLAG);
984
985 tcg_temp_free(tmp);
986 }
987 break;
988 case CC_GE:
989 cris_evaluate_flags(dc);
990 /* Overlay the V flag on top of the N. */
991 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
992 tcg_gen_xor_tl(cc,
993 cpu_PR[PR_CCS], cc);
994 tcg_gen_andi_tl(cc, cc, N_FLAG);
995 tcg_gen_xori_tl(cc, cc, N_FLAG);
996 break;
997 case CC_LT:
998 cris_evaluate_flags(dc);
999 /* Overlay the V flag on top of the N. */
1000 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1001 tcg_gen_xor_tl(cc,
1002 cpu_PR[PR_CCS], cc);
1003 tcg_gen_andi_tl(cc, cc, N_FLAG);
1004 break;
1005 case CC_GT:
1006 cris_evaluate_flags(dc);
1007 {
1008 TCGv n, z;
1009
1010 n = tcg_temp_new();
1011 z = tcg_temp_new();
1012
1013 /* To avoid a shift we overlay everything on
1014 the V flag. */
1015 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1016 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1017 /* invert Z. */
1018 tcg_gen_xori_tl(z, z, 2);
1019
1020 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1021 tcg_gen_xori_tl(n, n, 2);
1022 tcg_gen_and_tl(cc, z, n);
1023 tcg_gen_andi_tl(cc, cc, 2);
1024
1025 tcg_temp_free(n);
1026 tcg_temp_free(z);
1027 }
1028 break;
1029 case CC_LE:
1030 cris_evaluate_flags(dc);
1031 {
1032 TCGv n, z;
1033
1034 n = tcg_temp_new();
1035 z = tcg_temp_new();
1036
1037 /* To avoid a shift we overlay everything on
1038 the V flag. */
1039 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1040 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1041
1042 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1043 tcg_gen_or_tl(cc, z, n);
1044 tcg_gen_andi_tl(cc, cc, 2);
1045
1046 tcg_temp_free(n);
1047 tcg_temp_free(z);
1048 }
1049 break;
1050 case CC_P:
1051 cris_evaluate_flags(dc);
1052 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1053 break;
1054 case CC_A:
1055 tcg_gen_movi_tl(cc, 1);
1056 break;
1057 default:
1058 BUG();
1059 break;
1060 };
1061 }
1062
1063 static void cris_store_direct_jmp(DisasContext *dc)
1064 {
1065 /* Store the direct jmp state into the cpu-state. */
1066 if (dc->jmp == JMP_DIRECT) {
1067 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1068 tcg_gen_movi_tl(env_btaken, 1);
1069 }
1070 }
1071
1072 static void cris_prepare_cc_branch (DisasContext *dc,
1073 int offset, int cond)
1074 {
1075 /* This helps us re-schedule the micro-code to insns in delay-slots
1076 before the actual jump. */
1077 dc->delayed_branch = 2;
1078 dc->jmp_pc = dc->pc + offset;
1079
1080 if (cond != CC_A)
1081 {
1082 dc->jmp = JMP_INDIRECT;
1083 gen_tst_cc (dc, env_btaken, cond);
1084 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1085 } else {
1086 /* Allow chaining. */
1087 dc->jmp = JMP_DIRECT;
1088 }
1089 }
1090
1091
1092 /* jumps, when the dest is in a live reg for example. Direct should be set
1093 when the dest addr is constant to allow tb chaining. */
1094 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1095 {
1096 /* This helps us re-schedule the micro-code to insns in delay-slots
1097 before the actual jump. */
1098 dc->delayed_branch = 2;
1099 dc->jmp = type;
1100 if (type == JMP_INDIRECT)
1101 tcg_gen_movi_tl(env_btaken, 1);
1102 }
1103
1104 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1105 {
1106 int mem_index = cpu_mmu_index(dc->env);
1107
1108 /* If we get a fault on a delayslot we must keep the jmp state in
1109 the cpu-state to be able to re-execute the jmp. */
1110 if (dc->delayed_branch == 1)
1111 cris_store_direct_jmp(dc);
1112
1113 tcg_gen_qemu_ld64(dst, addr, mem_index);
1114 }
1115
1116 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1117 unsigned int size, int sign)
1118 {
1119 int mem_index = cpu_mmu_index(dc->env);
1120
1121 /* If we get a fault on a delayslot we must keep the jmp state in
1122 the cpu-state to be able to re-execute the jmp. */
1123 if (dc->delayed_branch == 1)
1124 cris_store_direct_jmp(dc);
1125
1126 if (size == 1) {
1127 if (sign)
1128 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1129 else
1130 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1131 }
1132 else if (size == 2) {
1133 if (sign)
1134 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1135 else
1136 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1137 }
1138 else if (size == 4) {
1139 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1140 }
1141 else {
1142 abort();
1143 }
1144 }
1145
1146 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1147 unsigned int size)
1148 {
1149 int mem_index = cpu_mmu_index(dc->env);
1150
1151 /* If we get a fault on a delayslot we must keep the jmp state in
1152 the cpu-state to be able to re-execute the jmp. */
1153 if (dc->delayed_branch == 1)
1154 cris_store_direct_jmp(dc);
1155
1156
1157 /* Conditional writes. We only support the kind were X and P are known
1158 at translation time. */
1159 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1160 dc->postinc = 0;
1161 cris_evaluate_flags(dc);
1162 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1163 return;
1164 }
1165
1166 if (size == 1)
1167 tcg_gen_qemu_st8(val, addr, mem_index);
1168 else if (size == 2)
1169 tcg_gen_qemu_st16(val, addr, mem_index);
1170 else
1171 tcg_gen_qemu_st32(val, addr, mem_index);
1172
1173 if (dc->flagx_known && dc->flags_x) {
1174 cris_evaluate_flags(dc);
1175 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1176 }
1177 }
1178
1179 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1180 {
1181 if (size == 1)
1182 tcg_gen_ext8s_i32(d, s);
1183 else if (size == 2)
1184 tcg_gen_ext16s_i32(d, s);
1185 else if(!TCGV_EQUAL(d, s))
1186 tcg_gen_mov_tl(d, s);
1187 }
1188
1189 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1190 {
1191 if (size == 1)
1192 tcg_gen_ext8u_i32(d, s);
1193 else if (size == 2)
1194 tcg_gen_ext16u_i32(d, s);
1195 else if (!TCGV_EQUAL(d, s))
1196 tcg_gen_mov_tl(d, s);
1197 }
1198
1199 #if DISAS_CRIS
1200 static char memsize_char(int size)
1201 {
1202 switch (size)
1203 {
1204 case 1: return 'b'; break;
1205 case 2: return 'w'; break;
1206 case 4: return 'd'; break;
1207 default:
1208 return 'x';
1209 break;
1210 }
1211 }
1212 #endif
1213
1214 static inline unsigned int memsize_z(DisasContext *dc)
1215 {
1216 return dc->zsize + 1;
1217 }
1218
1219 static inline unsigned int memsize_zz(DisasContext *dc)
1220 {
1221 switch (dc->zzsize)
1222 {
1223 case 0: return 1;
1224 case 1: return 2;
1225 default:
1226 return 4;
1227 }
1228 }
1229
1230 static inline void do_postinc (DisasContext *dc, int size)
1231 {
1232 if (dc->postinc)
1233 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1234 }
1235
1236 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1237 int size, int s_ext, TCGv dst)
1238 {
1239 if (s_ext)
1240 t_gen_sext(dst, cpu_R[rs], size);
1241 else
1242 t_gen_zext(dst, cpu_R[rs], size);
1243 }
1244
1245 /* Prepare T0 and T1 for a register alu operation.
1246 s_ext decides if the operand1 should be sign-extended or zero-extended when
1247 needed. */
1248 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1249 int size, int s_ext, TCGv dst, TCGv src)
1250 {
1251 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1252
1253 if (s_ext)
1254 t_gen_sext(dst, cpu_R[rd], size);
1255 else
1256 t_gen_zext(dst, cpu_R[rd], size);
1257 }
1258
1259 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1260 TCGv dst)
1261 {
1262 unsigned int rs, rd;
1263 uint32_t imm;
1264 int is_imm;
1265 int insn_len = 2;
1266
1267 rs = dc->op1;
1268 rd = dc->op2;
1269 is_imm = rs == 15 && dc->postinc;
1270
1271 /* Load [$rs] onto T1. */
1272 if (is_imm) {
1273 insn_len = 2 + memsize;
1274 if (memsize == 1)
1275 insn_len++;
1276
1277 if (memsize != 4) {
1278 if (s_ext) {
1279 if (memsize == 1)
1280 imm = ldsb_code(dc->pc + 2);
1281 else
1282 imm = ldsw_code(dc->pc + 2);
1283 } else {
1284 if (memsize == 1)
1285 imm = ldub_code(dc->pc + 2);
1286 else
1287 imm = lduw_code(dc->pc + 2);
1288 }
1289 } else
1290 imm = ldl_code(dc->pc + 2);
1291
1292 tcg_gen_movi_tl(dst, imm);
1293 dc->postinc = 0;
1294 } else {
1295 cris_flush_cc_state(dc);
1296 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1297 if (s_ext)
1298 t_gen_sext(dst, dst, memsize);
1299 else
1300 t_gen_zext(dst, dst, memsize);
1301 }
1302 return insn_len;
1303 }
1304
1305 /* Prepare T0 and T1 for a memory + alu operation.
1306 s_ext decides if the operand1 should be sign-extended or zero-extended when
1307 needed. */
1308 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize,
1309 TCGv dst, TCGv src)
1310 {
1311 int insn_len;
1312
1313 insn_len = dec_prep_move_m(dc, s_ext, memsize, src);
1314 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1315 return insn_len;
1316 }
1317
1318 #if DISAS_CRIS
1319 static const char *cc_name(int cc)
1320 {
1321 static const char *cc_names[16] = {
1322 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1323 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1324 };
1325 assert(cc < 16);
1326 return cc_names[cc];
1327 }
1328 #endif
1329
1330 /* Start of insn decoders. */
1331
1332 static unsigned int dec_bccq(DisasContext *dc)
1333 {
1334 int32_t offset;
1335 int sign;
1336 uint32_t cond = dc->op2;
1337 int tmp;
1338
1339 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1340 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1341
1342 offset *= 2;
1343 offset |= sign << 8;
1344 tmp = offset;
1345 offset = sign_extend(offset, 8);
1346
1347 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1348
1349 /* op2 holds the condition-code. */
1350 cris_cc_mask(dc, 0);
1351 cris_prepare_cc_branch (dc, offset, cond);
1352 return 2;
1353 }
1354 static unsigned int dec_addoq(DisasContext *dc)
1355 {
1356 int32_t imm;
1357
1358 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1359 imm = sign_extend(dc->op1, 7);
1360
1361 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1362 cris_cc_mask(dc, 0);
1363 /* Fetch register operand, */
1364 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1365
1366 return 2;
1367 }
1368 static unsigned int dec_addq(DisasContext *dc)
1369 {
1370 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1371
1372 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1373
1374 cris_cc_mask(dc, CC_MASK_NZVC);
1375
1376 cris_alu(dc, CC_OP_ADD,
1377 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1378 return 2;
1379 }
1380 static unsigned int dec_moveq(DisasContext *dc)
1381 {
1382 uint32_t imm;
1383
1384 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1385 imm = sign_extend(dc->op1, 5);
1386 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1387
1388 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1389 return 2;
1390 }
1391 static unsigned int dec_subq(DisasContext *dc)
1392 {
1393 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1394
1395 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1396
1397 cris_cc_mask(dc, CC_MASK_NZVC);
1398 cris_alu(dc, CC_OP_SUB,
1399 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1400 return 2;
1401 }
1402 static unsigned int dec_cmpq(DisasContext *dc)
1403 {
1404 uint32_t imm;
1405 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1406 imm = sign_extend(dc->op1, 5);
1407
1408 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1409 cris_cc_mask(dc, CC_MASK_NZVC);
1410
1411 cris_alu(dc, CC_OP_CMP,
1412 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1413 return 2;
1414 }
1415 static unsigned int dec_andq(DisasContext *dc)
1416 {
1417 uint32_t imm;
1418 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1419 imm = sign_extend(dc->op1, 5);
1420
1421 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1422 cris_cc_mask(dc, CC_MASK_NZ);
1423
1424 cris_alu(dc, CC_OP_AND,
1425 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1426 return 2;
1427 }
1428 static unsigned int dec_orq(DisasContext *dc)
1429 {
1430 uint32_t imm;
1431 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1432 imm = sign_extend(dc->op1, 5);
1433 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1434 cris_cc_mask(dc, CC_MASK_NZ);
1435
1436 cris_alu(dc, CC_OP_OR,
1437 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1438 return 2;
1439 }
1440 static unsigned int dec_btstq(DisasContext *dc)
1441 {
1442 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1443 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1444
1445 cris_cc_mask(dc, CC_MASK_NZ);
1446 cris_evaluate_flags(dc);
1447 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1448 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1449 cris_alu(dc, CC_OP_MOVE,
1450 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1451 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1452 dc->flags_uptodate = 1;
1453 return 2;
1454 }
1455 static unsigned int dec_asrq(DisasContext *dc)
1456 {
1457 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1458 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1459 cris_cc_mask(dc, CC_MASK_NZ);
1460
1461 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1462 cris_alu(dc, CC_OP_MOVE,
1463 cpu_R[dc->op2],
1464 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1465 return 2;
1466 }
1467 static unsigned int dec_lslq(DisasContext *dc)
1468 {
1469 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1470 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1471
1472 cris_cc_mask(dc, CC_MASK_NZ);
1473
1474 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1475
1476 cris_alu(dc, CC_OP_MOVE,
1477 cpu_R[dc->op2],
1478 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1479 return 2;
1480 }
1481 static unsigned int dec_lsrq(DisasContext *dc)
1482 {
1483 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1484 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1485
1486 cris_cc_mask(dc, CC_MASK_NZ);
1487
1488 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1489 cris_alu(dc, CC_OP_MOVE,
1490 cpu_R[dc->op2],
1491 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1492 return 2;
1493 }
1494
1495 static unsigned int dec_move_r(DisasContext *dc)
1496 {
1497 int size = memsize_zz(dc);
1498
1499 LOG_DIS("move.%c $r%u, $r%u\n",
1500 memsize_char(size), dc->op1, dc->op2);
1501
1502 cris_cc_mask(dc, CC_MASK_NZ);
1503 if (size == 4) {
1504 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1505 cris_cc_mask(dc, CC_MASK_NZ);
1506 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1507 cris_update_cc_x(dc);
1508 cris_update_result(dc, cpu_R[dc->op2]);
1509 }
1510 else {
1511 TCGv t0;
1512
1513 t0 = tcg_temp_new();
1514 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1515 cris_alu(dc, CC_OP_MOVE,
1516 cpu_R[dc->op2],
1517 cpu_R[dc->op2], t0, size);
1518 tcg_temp_free(t0);
1519 }
1520 return 2;
1521 }
1522
1523 static unsigned int dec_scc_r(DisasContext *dc)
1524 {
1525 int cond = dc->op2;
1526
1527 LOG_DIS("s%s $r%u\n",
1528 cc_name(cond), dc->op1);
1529
1530 if (cond != CC_A)
1531 {
1532 int l1;
1533
1534 gen_tst_cc (dc, cpu_R[dc->op1], cond);
1535 l1 = gen_new_label();
1536 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1537 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1538 gen_set_label(l1);
1539 }
1540 else
1541 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1542
1543 cris_cc_mask(dc, 0);
1544 return 2;
1545 }
1546
1547 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1548 {
1549 if (size == 4) {
1550 t[0] = cpu_R[dc->op2];
1551 t[1] = cpu_R[dc->op1];
1552 } else {
1553 t[0] = tcg_temp_new();
1554 t[1] = tcg_temp_new();
1555 }
1556 }
1557
1558 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1559 {
1560 if (size != 4) {
1561 tcg_temp_free(t[0]);
1562 tcg_temp_free(t[1]);
1563 }
1564 }
1565
1566 static unsigned int dec_and_r(DisasContext *dc)
1567 {
1568 TCGv t[2];
1569 int size = memsize_zz(dc);
1570
1571 LOG_DIS("and.%c $r%u, $r%u\n",
1572 memsize_char(size), dc->op1, dc->op2);
1573
1574 cris_cc_mask(dc, CC_MASK_NZ);
1575
1576 cris_alu_alloc_temps(dc, size, t);
1577 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1578 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1579 cris_alu_free_temps(dc, size, t);
1580 return 2;
1581 }
1582
1583 static unsigned int dec_lz_r(DisasContext *dc)
1584 {
1585 TCGv t0;
1586 LOG_DIS("lz $r%u, $r%u\n",
1587 dc->op1, dc->op2);
1588 cris_cc_mask(dc, CC_MASK_NZ);
1589 t0 = tcg_temp_new();
1590 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1591 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1592 tcg_temp_free(t0);
1593 return 2;
1594 }
1595
1596 static unsigned int dec_lsl_r(DisasContext *dc)
1597 {
1598 TCGv t[2];
1599 int size = memsize_zz(dc);
1600
1601 LOG_DIS("lsl.%c $r%u, $r%u\n",
1602 memsize_char(size), dc->op1, dc->op2);
1603
1604 cris_cc_mask(dc, CC_MASK_NZ);
1605 cris_alu_alloc_temps(dc, size, t);
1606 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1607 tcg_gen_andi_tl(t[1], t[1], 63);
1608 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1609 cris_alu_alloc_temps(dc, size, t);
1610 return 2;
1611 }
1612
1613 static unsigned int dec_lsr_r(DisasContext *dc)
1614 {
1615 TCGv t[2];
1616 int size = memsize_zz(dc);
1617
1618 LOG_DIS("lsr.%c $r%u, $r%u\n",
1619 memsize_char(size), dc->op1, dc->op2);
1620
1621 cris_cc_mask(dc, CC_MASK_NZ);
1622 cris_alu_alloc_temps(dc, size, t);
1623 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1624 tcg_gen_andi_tl(t[1], t[1], 63);
1625 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1626 cris_alu_free_temps(dc, size, t);
1627 return 2;
1628 }
1629
1630 static unsigned int dec_asr_r(DisasContext *dc)
1631 {
1632 TCGv t[2];
1633 int size = memsize_zz(dc);
1634
1635 LOG_DIS("asr.%c $r%u, $r%u\n",
1636 memsize_char(size), dc->op1, dc->op2);
1637
1638 cris_cc_mask(dc, CC_MASK_NZ);
1639 cris_alu_alloc_temps(dc, size, t);
1640 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1641 tcg_gen_andi_tl(t[1], t[1], 63);
1642 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1643 cris_alu_free_temps(dc, size, t);
1644 return 2;
1645 }
1646
1647 static unsigned int dec_muls_r(DisasContext *dc)
1648 {
1649 TCGv t[2];
1650 int size = memsize_zz(dc);
1651
1652 LOG_DIS("muls.%c $r%u, $r%u\n",
1653 memsize_char(size), dc->op1, dc->op2);
1654 cris_cc_mask(dc, CC_MASK_NZV);
1655 cris_alu_alloc_temps(dc, size, t);
1656 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1657
1658 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1659 cris_alu_free_temps(dc, size, t);
1660 return 2;
1661 }
1662
1663 static unsigned int dec_mulu_r(DisasContext *dc)
1664 {
1665 TCGv t[2];
1666 int size = memsize_zz(dc);
1667
1668 LOG_DIS("mulu.%c $r%u, $r%u\n",
1669 memsize_char(size), dc->op1, dc->op2);
1670 cris_cc_mask(dc, CC_MASK_NZV);
1671 cris_alu_alloc_temps(dc, size, t);
1672 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1673
1674 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1675 cris_alu_alloc_temps(dc, size, t);
1676 return 2;
1677 }
1678
1679
1680 static unsigned int dec_dstep_r(DisasContext *dc)
1681 {
1682 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1683 cris_cc_mask(dc, CC_MASK_NZ);
1684 cris_alu(dc, CC_OP_DSTEP,
1685 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1686 return 2;
1687 }
1688
1689 static unsigned int dec_xor_r(DisasContext *dc)
1690 {
1691 TCGv t[2];
1692 int size = memsize_zz(dc);
1693 LOG_DIS("xor.%c $r%u, $r%u\n",
1694 memsize_char(size), dc->op1, dc->op2);
1695 BUG_ON(size != 4); /* xor is dword. */
1696 cris_cc_mask(dc, CC_MASK_NZ);
1697 cris_alu_alloc_temps(dc, size, t);
1698 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1699
1700 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1701 cris_alu_free_temps(dc, size, t);
1702 return 2;
1703 }
1704
1705 static unsigned int dec_bound_r(DisasContext *dc)
1706 {
1707 TCGv l0;
1708 int size = memsize_zz(dc);
1709 LOG_DIS("bound.%c $r%u, $r%u\n",
1710 memsize_char(size), dc->op1, dc->op2);
1711 cris_cc_mask(dc, CC_MASK_NZ);
1712 l0 = tcg_temp_local_new();
1713 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1714 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1715 tcg_temp_free(l0);
1716 return 2;
1717 }
1718
1719 static unsigned int dec_cmp_r(DisasContext *dc)
1720 {
1721 TCGv t[2];
1722 int size = memsize_zz(dc);
1723 LOG_DIS("cmp.%c $r%u, $r%u\n",
1724 memsize_char(size), dc->op1, dc->op2);
1725 cris_cc_mask(dc, CC_MASK_NZVC);
1726 cris_alu_alloc_temps(dc, size, t);
1727 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1728
1729 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1730 cris_alu_free_temps(dc, size, t);
1731 return 2;
1732 }
1733
1734 static unsigned int dec_abs_r(DisasContext *dc)
1735 {
1736 TCGv t0;
1737
1738 LOG_DIS("abs $r%u, $r%u\n",
1739 dc->op1, dc->op2);
1740 cris_cc_mask(dc, CC_MASK_NZ);
1741
1742 t0 = tcg_temp_new();
1743 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1744 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1745 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1746 tcg_temp_free(t0);
1747
1748 cris_alu(dc, CC_OP_MOVE,
1749 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1750 return 2;
1751 }
1752
1753 static unsigned int dec_add_r(DisasContext *dc)
1754 {
1755 TCGv t[2];
1756 int size = memsize_zz(dc);
1757 LOG_DIS("add.%c $r%u, $r%u\n",
1758 memsize_char(size), dc->op1, dc->op2);
1759 cris_cc_mask(dc, CC_MASK_NZVC);
1760 cris_alu_alloc_temps(dc, size, t);
1761 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1762
1763 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1764 cris_alu_free_temps(dc, size, t);
1765 return 2;
1766 }
1767
1768 static unsigned int dec_addc_r(DisasContext *dc)
1769 {
1770 LOG_DIS("addc $r%u, $r%u\n",
1771 dc->op1, dc->op2);
1772 cris_evaluate_flags(dc);
1773 /* Set for this insn. */
1774 dc->flagx_known = 1;
1775 dc->flags_x = X_FLAG;
1776
1777 cris_cc_mask(dc, CC_MASK_NZVC);
1778 cris_alu(dc, CC_OP_ADDC,
1779 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1780 return 2;
1781 }
1782
1783 static unsigned int dec_mcp_r(DisasContext *dc)
1784 {
1785 LOG_DIS("mcp $p%u, $r%u\n",
1786 dc->op2, dc->op1);
1787 cris_evaluate_flags(dc);
1788 cris_cc_mask(dc, CC_MASK_RNZV);
1789 cris_alu(dc, CC_OP_MCP,
1790 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1791 return 2;
1792 }
1793
1794 #if DISAS_CRIS
1795 static char * swapmode_name(int mode, char *modename) {
1796 int i = 0;
1797 if (mode & 8)
1798 modename[i++] = 'n';
1799 if (mode & 4)
1800 modename[i++] = 'w';
1801 if (mode & 2)
1802 modename[i++] = 'b';
1803 if (mode & 1)
1804 modename[i++] = 'r';
1805 modename[i++] = 0;
1806 return modename;
1807 }
1808 #endif
1809
1810 static unsigned int dec_swap_r(DisasContext *dc)
1811 {
1812 TCGv t0;
1813 #if DISAS_CRIS
1814 char modename[4];
1815 #endif
1816 LOG_DIS("swap%s $r%u\n",
1817 swapmode_name(dc->op2, modename), dc->op1);
1818
1819 cris_cc_mask(dc, CC_MASK_NZ);
1820 t0 = tcg_temp_new();
1821 t_gen_mov_TN_reg(t0, dc->op1);
1822 if (dc->op2 & 8)
1823 tcg_gen_not_tl(t0, t0);
1824 if (dc->op2 & 4)
1825 t_gen_swapw(t0, t0);
1826 if (dc->op2 & 2)
1827 t_gen_swapb(t0, t0);
1828 if (dc->op2 & 1)
1829 t_gen_swapr(t0, t0);
1830 cris_alu(dc, CC_OP_MOVE,
1831 cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1832 tcg_temp_free(t0);
1833 return 2;
1834 }
1835
1836 static unsigned int dec_or_r(DisasContext *dc)
1837 {
1838 TCGv t[2];
1839 int size = memsize_zz(dc);
1840 LOG_DIS("or.%c $r%u, $r%u\n",
1841 memsize_char(size), dc->op1, dc->op2);
1842 cris_cc_mask(dc, CC_MASK_NZ);
1843 cris_alu_alloc_temps(dc, size, t);
1844 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1845 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1846 cris_alu_free_temps(dc, size, t);
1847 return 2;
1848 }
1849
1850 static unsigned int dec_addi_r(DisasContext *dc)
1851 {
1852 TCGv t0;
1853 LOG_DIS("addi.%c $r%u, $r%u\n",
1854 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1855 cris_cc_mask(dc, 0);
1856 t0 = tcg_temp_new();
1857 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1858 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1859 tcg_temp_free(t0);
1860 return 2;
1861 }
1862
1863 static unsigned int dec_addi_acr(DisasContext *dc)
1864 {
1865 TCGv t0;
1866 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1867 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1868 cris_cc_mask(dc, 0);
1869 t0 = tcg_temp_new();
1870 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1871 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1872 tcg_temp_free(t0);
1873 return 2;
1874 }
1875
1876 static unsigned int dec_neg_r(DisasContext *dc)
1877 {
1878 TCGv t[2];
1879 int size = memsize_zz(dc);
1880 LOG_DIS("neg.%c $r%u, $r%u\n",
1881 memsize_char(size), dc->op1, dc->op2);
1882 cris_cc_mask(dc, CC_MASK_NZVC);
1883 cris_alu_alloc_temps(dc, size, t);
1884 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1885
1886 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1887 cris_alu_free_temps(dc, size, t);
1888 return 2;
1889 }
1890
1891 static unsigned int dec_btst_r(DisasContext *dc)
1892 {
1893 LOG_DIS("btst $r%u, $r%u\n",
1894 dc->op1, dc->op2);
1895 cris_cc_mask(dc, CC_MASK_NZ);
1896 cris_evaluate_flags(dc);
1897 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1898 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1899 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1900 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1901 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1902 dc->flags_uptodate = 1;
1903 return 2;
1904 }
1905
1906 static unsigned int dec_sub_r(DisasContext *dc)
1907 {
1908 TCGv t[2];
1909 int size = memsize_zz(dc);
1910 LOG_DIS("sub.%c $r%u, $r%u\n",
1911 memsize_char(size), dc->op1, dc->op2);
1912 cris_cc_mask(dc, CC_MASK_NZVC);
1913 cris_alu_alloc_temps(dc, size, t);
1914 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1915 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1916 cris_alu_free_temps(dc, size, t);
1917 return 2;
1918 }
1919
1920 /* Zero extension. From size to dword. */
1921 static unsigned int dec_movu_r(DisasContext *dc)
1922 {
1923 TCGv t0;
1924 int size = memsize_z(dc);
1925 LOG_DIS("movu.%c $r%u, $r%u\n",
1926 memsize_char(size),
1927 dc->op1, dc->op2);
1928
1929 cris_cc_mask(dc, CC_MASK_NZ);
1930 t0 = tcg_temp_new();
1931 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1932 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1933 tcg_temp_free(t0);
1934 return 2;
1935 }
1936
1937 /* Sign extension. From size to dword. */
1938 static unsigned int dec_movs_r(DisasContext *dc)
1939 {
1940 TCGv t0;
1941 int size = memsize_z(dc);
1942 LOG_DIS("movs.%c $r%u, $r%u\n",
1943 memsize_char(size),
1944 dc->op1, dc->op2);
1945
1946 cris_cc_mask(dc, CC_MASK_NZ);
1947 t0 = tcg_temp_new();
1948 /* Size can only be qi or hi. */
1949 t_gen_sext(t0, cpu_R[dc->op1], size);
1950 cris_alu(dc, CC_OP_MOVE,
1951 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1952 tcg_temp_free(t0);
1953 return 2;
1954 }
1955
1956 /* zero extension. From size to dword. */
1957 static unsigned int dec_addu_r(DisasContext *dc)
1958 {
1959 TCGv t0;
1960 int size = memsize_z(dc);
1961 LOG_DIS("addu.%c $r%u, $r%u\n",
1962 memsize_char(size),
1963 dc->op1, dc->op2);
1964
1965 cris_cc_mask(dc, CC_MASK_NZVC);
1966 t0 = tcg_temp_new();
1967 /* Size can only be qi or hi. */
1968 t_gen_zext(t0, cpu_R[dc->op1], size);
1969 cris_alu(dc, CC_OP_ADD,
1970 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1971 tcg_temp_free(t0);
1972 return 2;
1973 }
1974
1975 /* Sign extension. From size to dword. */
1976 static unsigned int dec_adds_r(DisasContext *dc)
1977 {
1978 TCGv t0;
1979 int size = memsize_z(dc);
1980 LOG_DIS("adds.%c $r%u, $r%u\n",
1981 memsize_char(size),
1982 dc->op1, dc->op2);
1983
1984 cris_cc_mask(dc, CC_MASK_NZVC);
1985 t0 = tcg_temp_new();
1986 /* Size can only be qi or hi. */
1987 t_gen_sext(t0, cpu_R[dc->op1], size);
1988 cris_alu(dc, CC_OP_ADD,
1989 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1990 tcg_temp_free(t0);
1991 return 2;
1992 }
1993
1994 /* Zero extension. From size to dword. */
1995 static unsigned int dec_subu_r(DisasContext *dc)
1996 {
1997 TCGv t0;
1998 int size = memsize_z(dc);
1999 LOG_DIS("subu.%c $r%u, $r%u\n",
2000 memsize_char(size),
2001 dc->op1, dc->op2);
2002
2003 cris_cc_mask(dc, CC_MASK_NZVC);
2004 t0 = tcg_temp_new();
2005 /* Size can only be qi or hi. */
2006 t_gen_zext(t0, cpu_R[dc->op1], size);
2007 cris_alu(dc, CC_OP_SUB,
2008 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2009 tcg_temp_free(t0);
2010 return 2;
2011 }
2012
2013 /* Sign extension. From size to dword. */
2014 static unsigned int dec_subs_r(DisasContext *dc)
2015 {
2016 TCGv t0;
2017 int size = memsize_z(dc);
2018 LOG_DIS("subs.%c $r%u, $r%u\n",
2019 memsize_char(size),
2020 dc->op1, dc->op2);
2021
2022 cris_cc_mask(dc, CC_MASK_NZVC);
2023 t0 = tcg_temp_new();
2024 /* Size can only be qi or hi. */
2025 t_gen_sext(t0, cpu_R[dc->op1], size);
2026 cris_alu(dc, CC_OP_SUB,
2027 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2028 tcg_temp_free(t0);
2029 return 2;
2030 }
2031
2032 static unsigned int dec_setclrf(DisasContext *dc)
2033 {
2034 uint32_t flags;
2035 int set = (~dc->opcode >> 2) & 1;
2036
2037
2038 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2039 | EXTRACT_FIELD(dc->ir, 0, 3);
2040 if (set && flags == 0) {
2041 LOG_DIS("nop\n");
2042 return 2;
2043 } else if (!set && (flags & 0x20)) {
2044 LOG_DIS("di\n");
2045 }
2046 else {
2047 LOG_DIS("%sf %x\n",
2048 set ? "set" : "clr",
2049 flags);
2050 }
2051
2052 /* User space is not allowed to touch these. Silently ignore. */
2053 if (dc->tb_flags & U_FLAG) {
2054 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2055 }
2056
2057 if (flags & X_FLAG) {
2058 dc->flagx_known = 1;
2059 if (set)
2060 dc->flags_x = X_FLAG;
2061 else
2062 dc->flags_x = 0;
2063 }
2064
2065 /* Break the TB if the P flag changes. */
2066 if (flags & P_FLAG) {
2067 if ((set && !(dc->tb_flags & P_FLAG))
2068 || (!set && (dc->tb_flags & P_FLAG))) {
2069 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2070 dc->is_jmp = DISAS_UPDATE;
2071 dc->cpustate_changed = 1;
2072 }
2073 }
2074 if (flags & S_FLAG) {
2075 dc->cpustate_changed = 1;
2076 }
2077
2078
2079 /* Simply decode the flags. */
2080 cris_evaluate_flags (dc);
2081 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2082 cris_update_cc_x(dc);
2083 tcg_gen_movi_tl(cc_op, dc->cc_op);
2084
2085 if (set) {
2086 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2087 /* Enter user mode. */
2088 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2089 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2090 dc->cpustate_changed = 1;
2091 }
2092 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2093 }
2094 else
2095 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2096
2097 dc->flags_uptodate = 1;
2098 dc->clear_x = 0;
2099 return 2;
2100 }
2101
2102 static unsigned int dec_move_rs(DisasContext *dc)
2103 {
2104 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2105 cris_cc_mask(dc, 0);
2106 gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2107 return 2;
2108 }
2109 static unsigned int dec_move_sr(DisasContext *dc)
2110 {
2111 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2112 cris_cc_mask(dc, 0);
2113 gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2114 return 2;
2115 }
2116
2117 static unsigned int dec_move_rp(DisasContext *dc)
2118 {
2119 TCGv t[2];
2120 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2121 cris_cc_mask(dc, 0);
2122
2123 t[0] = tcg_temp_new();
2124 if (dc->op2 == PR_CCS) {
2125 cris_evaluate_flags(dc);
2126 t_gen_mov_TN_reg(t[0], dc->op1);
2127 if (dc->tb_flags & U_FLAG) {
2128 t[1] = tcg_temp_new();
2129 /* User space is not allowed to touch all flags. */
2130 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2131 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2132 tcg_gen_or_tl(t[0], t[1], t[0]);
2133 tcg_temp_free(t[1]);
2134 }
2135 }
2136 else
2137 t_gen_mov_TN_reg(t[0], dc->op1);
2138
2139 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2140 if (dc->op2 == PR_CCS) {
2141 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2142 dc->flags_uptodate = 1;
2143 }
2144 tcg_temp_free(t[0]);
2145 return 2;
2146 }
2147 static unsigned int dec_move_pr(DisasContext *dc)
2148 {
2149 TCGv t0;
2150 LOG_DIS("move $p%u, $r%u\n", dc->op1, dc->op2);
2151 cris_cc_mask(dc, 0);
2152
2153 if (dc->op2 == PR_CCS)
2154 cris_evaluate_flags(dc);
2155
2156 t0 = tcg_temp_new();
2157 t_gen_mov_TN_preg(t0, dc->op2);
2158 cris_alu(dc, CC_OP_MOVE,
2159 cpu_R[dc->op1], cpu_R[dc->op1], t0, preg_sizes[dc->op2]);
2160 tcg_temp_free(t0);
2161 return 2;
2162 }
2163
2164 static unsigned int dec_move_mr(DisasContext *dc)
2165 {
2166 int memsize = memsize_zz(dc);
2167 int insn_len;
2168 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2169 memsize_char(memsize),
2170 dc->op1, dc->postinc ? "+]" : "]",
2171 dc->op2);
2172
2173 if (memsize == 4) {
2174 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2175 cris_cc_mask(dc, CC_MASK_NZ);
2176 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2177 cris_update_cc_x(dc);
2178 cris_update_result(dc, cpu_R[dc->op2]);
2179 }
2180 else {
2181 TCGv t0;
2182
2183 t0 = tcg_temp_new();
2184 insn_len = dec_prep_move_m(dc, 0, memsize, t0);
2185 cris_cc_mask(dc, CC_MASK_NZ);
2186 cris_alu(dc, CC_OP_MOVE,
2187 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2188 tcg_temp_free(t0);
2189 }
2190 do_postinc(dc, memsize);
2191 return insn_len;
2192 }
2193
2194 static inline void cris_alu_m_alloc_temps(TCGv *t)
2195 {
2196 t[0] = tcg_temp_new();
2197 t[1] = tcg_temp_new();
2198 }
2199
2200 static inline void cris_alu_m_free_temps(TCGv *t)
2201 {
2202 tcg_temp_free(t[0]);
2203 tcg_temp_free(t[1]);
2204 }
2205
2206 static unsigned int dec_movs_m(DisasContext *dc)
2207 {
2208 TCGv t[2];
2209 int memsize = memsize_z(dc);
2210 int insn_len;
2211 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2212 memsize_char(memsize),
2213 dc->op1, dc->postinc ? "+]" : "]",
2214 dc->op2);
2215
2216 cris_alu_m_alloc_temps(t);
2217 /* sign extend. */
2218 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2219 cris_cc_mask(dc, CC_MASK_NZ);
2220 cris_alu(dc, CC_OP_MOVE,
2221 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2222 do_postinc(dc, memsize);
2223 cris_alu_m_free_temps(t);
2224 return insn_len;
2225 }
2226
2227 static unsigned int dec_addu_m(DisasContext *dc)
2228 {
2229 TCGv t[2];
2230 int memsize = memsize_z(dc);
2231 int insn_len;
2232 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2233 memsize_char(memsize),
2234 dc->op1, dc->postinc ? "+]" : "]",
2235 dc->op2);
2236
2237 cris_alu_m_alloc_temps(t);
2238 /* sign extend. */
2239 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2240 cris_cc_mask(dc, CC_MASK_NZVC);
2241 cris_alu(dc, CC_OP_ADD,
2242 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2243 do_postinc(dc, memsize);
2244 cris_alu_m_free_temps(t);
2245 return insn_len;
2246 }
2247
2248 static unsigned int dec_adds_m(DisasContext *dc)
2249 {
2250 TCGv t[2];
2251 int memsize = memsize_z(dc);
2252 int insn_len;
2253 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2254 memsize_char(memsize),
2255 dc->op1, dc->postinc ? "+]" : "]",
2256 dc->op2);
2257
2258 cris_alu_m_alloc_temps(t);
2259 /* sign extend. */
2260 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2261 cris_cc_mask(dc, CC_MASK_NZVC);
2262 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2263 do_postinc(dc, memsize);
2264 cris_alu_m_free_temps(t);
2265 return insn_len;
2266 }
2267
2268 static unsigned int dec_subu_m(DisasContext *dc)
2269 {
2270 TCGv t[2];
2271 int memsize = memsize_z(dc);
2272 int insn_len;
2273 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2274 memsize_char(memsize),
2275 dc->op1, dc->postinc ? "+]" : "]",
2276 dc->op2);
2277
2278 cris_alu_m_alloc_temps(t);
2279 /* sign extend. */
2280 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2281 cris_cc_mask(dc, CC_MASK_NZVC);
2282 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2283 do_postinc(dc, memsize);
2284 cris_alu_m_free_temps(t);
2285 return insn_len;
2286 }
2287
2288 static unsigned int dec_subs_m(DisasContext *dc)
2289 {
2290 TCGv t[2];
2291 int memsize = memsize_z(dc);
2292 int insn_len;
2293 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2294 memsize_char(memsize),
2295 dc->op1, dc->postinc ? "+]" : "]",
2296 dc->op2);
2297
2298 cris_alu_m_alloc_temps(t);
2299 /* sign extend. */
2300 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2301 cris_cc_mask(dc, CC_MASK_NZVC);
2302 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2303 do_postinc(dc, memsize);
2304 cris_alu_m_free_temps(t);
2305 return insn_len;
2306 }
2307
2308 static unsigned int dec_movu_m(DisasContext *dc)
2309 {
2310 TCGv t[2];
2311 int memsize = memsize_z(dc);
2312 int insn_len;
2313
2314 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2315 memsize_char(memsize),
2316 dc->op1, dc->postinc ? "+]" : "]",
2317 dc->op2);
2318
2319 cris_alu_m_alloc_temps(t);
2320 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2321 cris_cc_mask(dc, CC_MASK_NZ);
2322 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2323 do_postinc(dc, memsize);
2324 cris_alu_m_free_temps(t);
2325 return insn_len;
2326 }
2327
2328 static unsigned int dec_cmpu_m(DisasContext *dc)
2329 {
2330 TCGv t[2];
2331 int memsize = memsize_z(dc);
2332 int insn_len;
2333 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2334 memsize_char(memsize),
2335 dc->op1, dc->postinc ? "+]" : "]",
2336 dc->op2);
2337
2338 cris_alu_m_alloc_temps(t);
2339 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2340 cris_cc_mask(dc, CC_MASK_NZVC);
2341 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2342 do_postinc(dc, memsize);
2343 cris_alu_m_free_temps(t);
2344 return insn_len;
2345 }
2346
2347 static unsigned int dec_cmps_m(DisasContext *dc)
2348 {
2349 TCGv t[2];
2350 int memsize = memsize_z(dc);
2351 int insn_len;
2352 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2353 memsize_char(memsize),
2354 dc->op1, dc->postinc ? "+]" : "]",
2355 dc->op2);
2356
2357 cris_alu_m_alloc_temps(t);
2358 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2359 cris_cc_mask(dc, CC_MASK_NZVC);
2360 cris_alu(dc, CC_OP_CMP,
2361 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2362 memsize_zz(dc));
2363 do_postinc(dc, memsize);
2364 cris_alu_m_free_temps(t);
2365 return insn_len;
2366 }
2367
2368 static unsigned int dec_cmp_m(DisasContext *dc)
2369 {
2370 TCGv t[2];
2371 int memsize = memsize_zz(dc);
2372 int insn_len;
2373 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2374 memsize_char(memsize),
2375 dc->op1, dc->postinc ? "+]" : "]",
2376 dc->op2);
2377
2378 cris_alu_m_alloc_temps(t);
2379 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2380 cris_cc_mask(dc, CC_MASK_NZVC);
2381 cris_alu(dc, CC_OP_CMP,
2382 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2383 memsize_zz(dc));
2384 do_postinc(dc, memsize);
2385 cris_alu_m_free_temps(t);
2386 return insn_len;
2387 }
2388
2389 static unsigned int dec_test_m(DisasContext *dc)
2390 {
2391 TCGv t[2];
2392 int memsize = memsize_zz(dc);
2393 int insn_len;
2394 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2395 memsize_char(memsize),
2396 dc->op1, dc->postinc ? "+]" : "]",
2397 dc->op2);
2398
2399 cris_evaluate_flags(dc);
2400
2401 cris_alu_m_alloc_temps(t);
2402 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2403 cris_cc_mask(dc, CC_MASK_NZ);
2404 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2405
2406 cris_alu(dc, CC_OP_CMP,
2407 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2408 do_postinc(dc, memsize);
2409 cris_alu_m_free_temps(t);
2410 return insn_len;
2411 }
2412
2413 static unsigned int dec_and_m(DisasContext *dc)
2414 {
2415 TCGv t[2];
2416 int memsize = memsize_zz(dc);
2417 int insn_len;
2418 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2419 memsize_char(memsize),
2420 dc->op1, dc->postinc ? "+]" : "]",
2421 dc->op2);
2422
2423 cris_alu_m_alloc_temps(t);
2424 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2425 cris_cc_mask(dc, CC_MASK_NZ);
2426 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2427 do_postinc(dc, memsize);
2428 cris_alu_m_free_temps(t);
2429 return insn_len;
2430 }
2431
2432 static unsigned int dec_add_m(DisasContext *dc)
2433 {
2434 TCGv t[2];
2435 int memsize = memsize_zz(dc);
2436 int insn_len;
2437 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2438 memsize_char(memsize),
2439 dc->op1, dc->postinc ? "+]" : "]",
2440 dc->op2);
2441
2442 cris_alu_m_alloc_temps(t);
2443 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2444 cris_cc_mask(dc, CC_MASK_NZVC);
2445 cris_alu(dc, CC_OP_ADD,
2446 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2447 do_postinc(dc, memsize);
2448 cris_alu_m_free_temps(t);
2449 return insn_len;
2450 }
2451
2452 static unsigned int dec_addo_m(DisasContext *dc)
2453 {
2454 TCGv t[2];
2455 int memsize = memsize_zz(dc);
2456 int insn_len;
2457 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2458 memsize_char(memsize),
2459 dc->op1, dc->postinc ? "+]" : "]",
2460 dc->op2);
2461
2462 cris_alu_m_alloc_temps(t);
2463 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2464 cris_cc_mask(dc, 0);
2465 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2466 do_postinc(dc, memsize);
2467 cris_alu_m_free_temps(t);
2468 return insn_len;
2469 }
2470
2471 static unsigned int dec_bound_m(DisasContext *dc)
2472 {
2473 TCGv l[2];
2474 int memsize = memsize_zz(dc);
2475 int insn_len;
2476 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2477 memsize_char(memsize),
2478 dc->op1, dc->postinc ? "+]" : "]",
2479 dc->op2);
2480
2481 l[0] = tcg_temp_local_new();
2482 l[1] = tcg_temp_local_new();
2483 insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]);
2484 cris_cc_mask(dc, CC_MASK_NZ);
2485 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2486 do_postinc(dc, memsize);
2487 tcg_temp_free(l[0]);
2488 tcg_temp_free(l[1]);
2489 return insn_len;
2490 }
2491
2492 static unsigned int dec_addc_mr(DisasContext *dc)
2493 {
2494 TCGv t[2];
2495 int insn_len = 2;
2496 LOG_DIS("addc [$r%u%s, $r%u\n",
2497 dc->op1, dc->postinc ? "+]" : "]",
2498 dc->op2);
2499
2500 cris_evaluate_flags(dc);
2501
2502 /* Set for this insn. */
2503 dc->flagx_known = 1;
2504 dc->flags_x = X_FLAG;
2505
2506 cris_alu_m_alloc_temps(t);
2507 insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
2508 cris_cc_mask(dc, CC_MASK_NZVC);
2509 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2510 do_postinc(dc, 4);
2511 cris_alu_m_free_temps(t);
2512 return insn_len;
2513 }
2514
2515 static unsigned int dec_sub_m(DisasContext *dc)
2516 {
2517 TCGv t[2];
2518 int memsize = memsize_zz(dc);
2519 int insn_len;
2520 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2521 memsize_char(memsize),
2522 dc->op1, dc->postinc ? "+]" : "]",
2523 dc->op2, dc->ir, dc->zzsize);
2524
2525 cris_alu_m_alloc_temps(t);
2526 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2527 cris_cc_mask(dc, CC_MASK_NZVC);
2528 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2529 do_postinc(dc, memsize);
2530 cris_alu_m_free_temps(t);
2531 return insn_len;
2532 }
2533
2534 static unsigned int dec_or_m(DisasContext *dc)
2535 {
2536 TCGv t[2];
2537 int memsize = memsize_zz(dc);
2538 int insn_len;
2539 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2540 memsize_char(memsize),
2541 dc->op1, dc->postinc ? "+]" : "]",
2542 dc->op2, dc->pc);
2543
2544 cris_alu_m_alloc_temps(t);
2545 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2546 cris_cc_mask(dc, CC_MASK_NZ);
2547 cris_alu(dc, CC_OP_OR,
2548 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2549 do_postinc(dc, memsize);
2550 cris_alu_m_free_temps(t);
2551 return insn_len;
2552 }
2553
2554 static unsigned int dec_move_mp(DisasContext *dc)
2555 {
2556 TCGv t[2];
2557 int memsize = memsize_zz(dc);
2558 int insn_len = 2;
2559
2560 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2561 memsize_char(memsize),
2562 dc->op1,
2563 dc->postinc ? "+]" : "]",
2564 dc->op2);
2565
2566 cris_alu_m_alloc_temps(t);
2567 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2568 cris_cc_mask(dc, 0);
2569 if (dc->op2 == PR_CCS) {
2570 cris_evaluate_flags(dc);
2571 if (dc->tb_flags & U_FLAG) {
2572 /* User space is not allowed to touch all flags. */
2573 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2574 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2575 tcg_gen_or_tl(t[1], t[0], t[1]);
2576 }
2577 }
2578
2579 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2580
2581 do_postinc(dc, memsize);
2582 cris_alu_m_free_temps(t);
2583 return insn_len;
2584 }
2585
2586 static unsigned int dec_move_pm(DisasContext *dc)
2587 {
2588 TCGv t0;
2589 int memsize;
2590
2591 memsize = preg_sizes[dc->op2];
2592
2593 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2594 memsize_char(memsize),
2595 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2596
2597 /* prepare store. Address in T0, value in T1. */
2598 if (dc->op2 == PR_CCS)
2599 cris_evaluate_flags(dc);
2600 t0 = tcg_temp_new();
2601 t_gen_mov_TN_preg(t0, dc->op2);
2602 cris_flush_cc_state(dc);
2603 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2604 tcg_temp_free(t0);
2605
2606 cris_cc_mask(dc, 0);
2607 if (dc->postinc)
2608 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2609 return 2;
2610 }
2611
2612 static unsigned int dec_movem_mr(DisasContext *dc)
2613 {
2614 TCGv_i64 tmp[16];
2615 TCGv tmp32;
2616 TCGv addr;
2617 int i;
2618 int nr = dc->op2 + 1;
2619
2620 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2621 dc->postinc ? "+]" : "]", dc->op2);
2622
2623 addr = tcg_temp_new();
2624 /* There are probably better ways of doing this. */
2625 cris_flush_cc_state(dc);
2626 for (i = 0; i < (nr >> 1); i++) {
2627 tmp[i] = tcg_temp_new_i64();
2628 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2629 gen_load64(dc, tmp[i], addr);
2630 }
2631 if (nr & 1) {
2632 tmp32 = tcg_temp_new_i32();
2633 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2634 gen_load(dc, tmp32, addr, 4, 0);
2635 } else
2636 TCGV_UNUSED(tmp32);
2637 tcg_temp_free(addr);
2638
2639 for (i = 0; i < (nr >> 1); i++) {
2640 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2641 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2642 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2643 tcg_temp_free_i64(tmp[i]);
2644 }
2645 if (nr & 1) {
2646 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2647 tcg_temp_free(tmp32);
2648 }
2649
2650 /* writeback the updated pointer value. */
2651 if (dc->postinc)
2652 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2653
2654 /* gen_load might want to evaluate the previous insns flags. */
2655 cris_cc_mask(dc, 0);
2656 return 2;
2657 }
2658
2659 static unsigned int dec_movem_rm(DisasContext *dc)
2660 {
2661 TCGv tmp;
2662 TCGv addr;
2663 int i;
2664
2665 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2666 dc->postinc ? "+]" : "]");
2667
2668 cris_flush_cc_state(dc);
2669
2670 tmp = tcg_temp_new();
2671 addr = tcg_temp_new();
2672 tcg_gen_movi_tl(tmp, 4);
2673 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2674 for (i = 0; i <= dc->op2; i++) {
2675 /* Displace addr. */
2676 /* Perform the store. */
2677 gen_store(dc, addr, cpu_R[i], 4);
2678 tcg_gen_add_tl(addr, addr, tmp);
2679 }
2680 if (dc->postinc)
2681 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2682 cris_cc_mask(dc, 0);
2683 tcg_temp_free(tmp);
2684 tcg_temp_free(addr);
2685 return 2;
2686 }
2687
2688 static unsigned int dec_move_rm(DisasContext *dc)
2689 {
2690 int memsize;
2691
2692 memsize = memsize_zz(dc);
2693
2694 LOG_DIS("move.%c $r%u, [$r%u]\n",
2695 memsize_char(memsize), dc->op2, dc->op1);
2696
2697 /* prepare store. */
2698 cris_flush_cc_state(dc);
2699 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2700
2701 if (dc->postinc)
2702 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2703 cris_cc_mask(dc, 0);
2704 return 2;
2705 }
2706
2707 static unsigned int dec_lapcq(DisasContext *dc)
2708 {
2709 LOG_DIS("lapcq %x, $r%u\n",
2710 dc->pc + dc->op1*2, dc->op2);
2711 cris_cc_mask(dc, 0);
2712 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2713 return 2;
2714 }
2715
2716 static unsigned int dec_lapc_im(DisasContext *dc)
2717 {
2718 unsigned int rd;
2719 int32_t imm;
2720 int32_t pc;
2721
2722 rd = dc->op2;
2723
2724 cris_cc_mask(dc, 0);
2725 imm = ldl_code(dc->pc + 2);
2726 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2727
2728 pc = dc->pc;
2729 pc += imm;
2730 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2731 return 6;
2732 }
2733
2734 /* Jump to special reg. */
2735 static unsigned int dec_jump_p(DisasContext *dc)
2736 {
2737 LOG_DIS("jump $p%u\n", dc->op2);
2738
2739 if (dc->op2 == PR_CCS)
2740 cris_evaluate_flags(dc);
2741 t_gen_mov_TN_preg(env_btarget, dc->op2);
2742 /* rete will often have low bit set to indicate delayslot. */
2743 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2744 cris_cc_mask(dc, 0);
2745 cris_prepare_jmp(dc, JMP_INDIRECT);
2746 return 2;
2747 }
2748
2749 /* Jump and save. */
2750 static unsigned int dec_jas_r(DisasContext *dc)
2751 {
2752 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2753 cris_cc_mask(dc, 0);
2754 /* Store the return address in Pd. */
2755 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2756 if (dc->op2 > 15)
2757 abort();
2758 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2759
2760 cris_prepare_jmp(dc, JMP_INDIRECT);
2761 return 2;
2762 }
2763
2764 static unsigned int dec_jas_im(DisasContext *dc)
2765 {
2766 uint32_t imm;
2767
2768 imm = ldl_code(dc->pc + 2);
2769
2770 LOG_DIS("jas 0x%x\n", imm);
2771 cris_cc_mask(dc, 0);
2772 /* Store the return address in Pd. */
2773 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2774
2775 dc->jmp_pc = imm;
2776 cris_prepare_jmp(dc, JMP_DIRECT);
2777 return 6;
2778 }
2779
2780 static unsigned int dec_jasc_im(DisasContext *dc)
2781 {
2782 uint32_t imm;
2783
2784 imm = ldl_code(dc->pc + 2);
2785
2786 LOG_DIS("jasc 0x%x\n", imm);
2787 cris_cc_mask(dc, 0);
2788 /* Store the return address in Pd. */
2789 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2790
2791 dc->jmp_pc = imm;
2792 cris_prepare_jmp(dc, JMP_DIRECT);
2793 return 6;
2794 }
2795
2796 static unsigned int dec_jasc_r(DisasContext *dc)
2797 {
2798 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2799 cris_cc_mask(dc, 0);
2800 /* Store the return address in Pd. */
2801 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2802 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2803 cris_prepare_jmp(dc, JMP_INDIRECT);
2804 return 2;
2805 }
2806
2807 static unsigned int dec_bcc_im(DisasContext *dc)
2808 {
2809 int32_t offset;
2810 uint32_t cond = dc->op2;
2811
2812 offset = ldsw_code(dc->pc + 2);
2813
2814 LOG_DIS("b%s %d pc=%x dst=%x\n",
2815 cc_name(cond), offset,
2816 dc->pc, dc->pc + offset);
2817
2818 cris_cc_mask(dc, 0);
2819 /* op2 holds the condition-code. */
2820 cris_prepare_cc_branch (dc, offset, cond);
2821 return 4;
2822 }
2823
2824 static unsigned int dec_bas_im(DisasContext *dc)
2825 {
2826 int32_t simm;
2827
2828
2829 simm = ldl_code(dc->pc + 2);
2830
2831 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2832 cris_cc_mask(dc, 0);
2833 /* Store the return address in Pd. */
2834 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2835
2836 dc->jmp_pc = dc->pc + simm;
2837 cris_prepare_jmp(dc, JMP_DIRECT);
2838 return 6;
2839 }
2840
2841 static unsigned int dec_basc_im(DisasContext *dc)
2842 {
2843 int32_t simm;
2844 simm = ldl_code(dc->pc + 2);
2845
2846 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2847 cris_cc_mask(dc, 0);
2848 /* Store the return address in Pd. */
2849 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2850
2851 dc->jmp_pc = dc->pc + simm;
2852 cris_prepare_jmp(dc, JMP_DIRECT);
2853 return 6;
2854 }
2855
2856 static unsigned int dec_rfe_etc(DisasContext *dc)
2857 {
2858 cris_cc_mask(dc, 0);
2859
2860 if (dc->op2 == 15) {
2861 t_gen_mov_env_TN(halted, tcg_const_tl(1));
2862 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2863 t_gen_raise_exception(EXCP_HLT);
2864 return 2;
2865 }
2866
2867 switch (dc->op2 & 7) {
2868 case 2:
2869 /* rfe. */
2870 LOG_DIS("rfe\n");
2871 cris_evaluate_flags(dc);
2872 gen_helper_rfe();
2873 dc->is_jmp = DISAS_UPDATE;
2874 break;
2875 case 5:
2876 /* rfn. */
2877 LOG_DIS("rfn\n");
2878 cris_evaluate_flags(dc);
2879 gen_helper_rfn();
2880 dc->is_jmp = DISAS_UPDATE;
2881 break;
2882 case 6:
2883 LOG_DIS("break %d\n", dc->op1);
2884 cris_evaluate_flags (dc);
2885 /* break. */
2886 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2887
2888 /* Breaks start at 16 in the exception vector. */
2889 t_gen_mov_env_TN(trap_vector,
2890 tcg_const_tl(dc->op1 + 16));
2891 t_gen_raise_exception(EXCP_BREAK);
2892 dc->is_jmp = DISAS_UPDATE;
2893 break;
2894 default:
2895 printf ("op2=%x\n", dc->op2);
2896 BUG();
2897 break;
2898
2899 }
2900 return 2;
2901 }
2902
2903 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2904 {
2905 return 2;
2906 }
2907
2908 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2909 {
2910 return 2;
2911 }
2912
2913 static unsigned int dec_null(DisasContext *dc)
2914 {
2915 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2916 dc->pc, dc->opcode, dc->op1, dc->op2);
2917 fflush(NULL);
2918 BUG();
2919 return 2;
2920 }
2921
2922 static struct decoder_info {
2923 struct {
2924 uint32_t bits;
2925 uint32_t mask;
2926 };
2927 unsigned int (*dec)(DisasContext *dc);
2928 } decinfo[] = {
2929 /* Order matters here. */
2930 {DEC_MOVEQ, dec_moveq},
2931 {DEC_BTSTQ, dec_btstq},
2932 {DEC_CMPQ, dec_cmpq},
2933 {DEC_ADDOQ, dec_addoq},
2934 {DEC_ADDQ, dec_addq},
2935 {DEC_SUBQ, dec_subq},
2936 {DEC_ANDQ, dec_andq},
2937 {DEC_ORQ, dec_orq},
2938 {DEC_ASRQ, dec_asrq},
2939 {DEC_LSLQ, dec_lslq},
2940 {DEC_LSRQ, dec_lsrq},
2941 {DEC_BCCQ, dec_bccq},
2942
2943 {DEC_BCC_IM, dec_bcc_im},
2944 {DEC_JAS_IM, dec_jas_im},
2945 {DEC_JAS_R, dec_jas_r},
2946 {DEC_JASC_IM, dec_jasc_im},
2947 {DEC_JASC_R, dec_jasc_r},
2948 {DEC_BAS_IM, dec_bas_im},
2949 {DEC_BASC_IM, dec_basc_im},
2950 {DEC_JUMP_P, dec_jump_p},
2951 {DEC_LAPC_IM, dec_lapc_im},
2952 {DEC_LAPCQ, dec_lapcq},
2953
2954 {DEC_RFE_ETC, dec_rfe_etc},
2955 {DEC_ADDC_MR, dec_addc_mr},
2956
2957 {DEC_MOVE_MP, dec_move_mp},
2958 {DEC_MOVE_PM, dec_move_pm},
2959 {DEC_MOVEM_MR, dec_movem_mr},
2960 {DEC_MOVEM_RM, dec_movem_rm},
2961 {DEC_MOVE_PR, dec_move_pr},
2962 {DEC_SCC_R, dec_scc_r},
2963 {DEC_SETF, dec_setclrf},
2964 {DEC_CLEARF, dec_setclrf},
2965
2966 {DEC_MOVE_SR, dec_move_sr},
2967 {DEC_MOVE_RP, dec_move_rp},
2968 {DEC_SWAP_R, dec_swap_r},
2969 {DEC_ABS_R, dec_abs_r},
2970 {DEC_LZ_R, dec_lz_r},
2971 {DEC_MOVE_RS, dec_move_rs},
2972 {DEC_BTST_R, dec_btst_r},
2973 {DEC_ADDC_R, dec_addc_r},
2974
2975 {DEC_DSTEP_R, dec_dstep_r},
2976 {DEC_XOR_R, dec_xor_r},
2977 {DEC_MCP_R, dec_mcp_r},
2978 {DEC_CMP_R, dec_cmp_r},
2979
2980 {DEC_ADDI_R, dec_addi_r},
2981 {DEC_ADDI_ACR, dec_addi_acr},
2982
2983 {DEC_ADD_R, dec_add_r},
2984 {DEC_SUB_R, dec_sub_r},
2985
2986 {DEC_ADDU_R, dec_addu_r},
2987 {DEC_ADDS_R, dec_adds_r},
2988 {DEC_SUBU_R, dec_subu_r},
2989 {DEC_SUBS_R, dec_subs_r},
2990 {DEC_LSL_R, dec_lsl_r},
2991
2992 {DEC_AND_R, dec_and_r},
2993 {DEC_OR_R, dec_or_r},
2994 {DEC_BOUND_R, dec_bound_r},
2995 {DEC_ASR_R, dec_asr_r},
2996 {DEC_LSR_R, dec_lsr_r},
2997
2998 {DEC_MOVU_R, dec_movu_r},
2999 {DEC_MOVS_R, dec_movs_r},
3000 {DEC_NEG_R, dec_neg_r},
3001 {DEC_MOVE_R, dec_move_r},
3002
3003 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3004 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3005
3006 {DEC_MULS_R, dec_muls_r},
3007 {DEC_MULU_R, dec_mulu_r},
3008
3009 {DEC_ADDU_M, dec_addu_m},
3010 {DEC_ADDS_M, dec_adds_m},
3011 {DEC_SUBU_M, dec_subu_m},
3012 {DEC_SUBS_M, dec_subs_m},
3013
3014 {DEC_CMPU_M, dec_cmpu_m},
3015 {DEC_CMPS_M, dec_cmps_m},
3016 {DEC_MOVU_M, dec_movu_m},
3017 {DEC_MOVS_M, dec_movs_m},
3018
3019 {DEC_CMP_M, dec_cmp_m},
3020 {DEC_ADDO_M, dec_addo_m},
3021 {DEC_BOUND_M, dec_bound_m},
3022 {DEC_ADD_M, dec_add_m},
3023 {DEC_SUB_M, dec_sub_m},
3024 {DEC_AND_M, dec_and_m},
3025 {DEC_OR_M, dec_or_m},
3026 {DEC_MOVE_RM, dec_move_rm},
3027 {DEC_TEST_M, dec_test_m},
3028 {DEC_MOVE_MR, dec_move_mr},
3029
3030 {{0, 0}, dec_null}
3031 };
3032
3033 static inline unsigned int
3034 cris_decoder(DisasContext *dc)
3035 {
3036 unsigned int insn_len = 2;
3037 int i;
3038
3039 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
3040 tcg_gen_debug_insn_start(dc->pc);
3041
3042 /* Load a halfword onto the instruction register. */
3043 dc->ir = lduw_code(dc->pc);
3044
3045 /* Now decode it. */
3046 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3047 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3048 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3049 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3050 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3051 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3052
3053 /* Large switch for all insns. */
3054 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3055 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
3056 {
3057 insn_len = decinfo[i].dec(dc);
3058 break;
3059 }
3060 }
3061
3062 #if !defined(CONFIG_USER_ONLY)
3063 /* Single-stepping ? */
3064 if (dc->tb_flags & S_FLAG) {
3065 int l1;
3066
3067 l1 = gen_new_label();
3068 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3069 /* We treat SPC as a break with an odd trap vector. */
3070 cris_evaluate_flags (dc);
3071 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3072 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3073 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3074 t_gen_raise_exception(EXCP_BREAK);
3075 gen_set_label(l1);
3076 }
3077 #endif
3078 return insn_len;
3079 }
3080
3081 static void check_breakpoint(CPUState *env, DisasContext *dc)
3082 {
3083 CPUBreakpoint *bp;
3084
3085 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
3086 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
3087 if (bp->pc == dc->pc) {
3088 cris_evaluate_flags (dc);
3089 tcg_gen_movi_tl(env_pc, dc->pc);
3090 t_gen_raise_exception(EXCP_DEBUG);
3091 dc->is_jmp = DISAS_UPDATE;
3092 }
3093 }
3094 }
3095 }
3096
3097
3098 /*
3099 * Delay slots on QEMU/CRIS.
3100 *
3101 * If an exception hits on a delayslot, the core will let ERP (the Exception
3102 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3103 * to give SW a hint that the exception actually hit on the dslot.
3104 *
3105 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3106 * the core and any jmp to an odd addresses will mask off that lsb. It is
3107 * simply there to let sw know there was an exception on a dslot.
3108 *
3109 * When the software returns from an exception, the branch will re-execute.
3110 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3111 * and the branch and delayslot dont share pages.
3112 *
3113 * The TB contaning the branch insn will set up env->btarget and evaluate
3114 * env->btaken. When the translation loop exits we will note that the branch
3115 * sequence is broken and let env->dslot be the size of the branch insn (those
3116 * vary in length).
3117 *
3118 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3119 * set). It will also expect to have env->dslot setup with the size of the
3120 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3121 * will execute the dslot and take the branch, either to btarget or just one
3122 * insn ahead.
3123 *
3124 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3125 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3126 * branch and set lsb). Then env->dslot gets cleared so that the exception
3127 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3128 * masked off and we will reexecute the branch insn.
3129 *
3130 */
3131
3132 /* generate intermediate code for basic block 'tb'. */
3133 static void
3134 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3135 int search_pc)
3136 {
3137 uint16_t *gen_opc_end;
3138 uint32_t pc_start;
3139 unsigned int insn_len;
3140 int j, lj;
3141 struct DisasContext ctx;
3142 struct DisasContext *dc = &ctx;
3143 uint32_t next_page_start;
3144 target_ulong npc;
3145 int num_insns;
3146 int max_insns;
3147
3148 qemu_log_try_set_file(stderr);
3149
3150 /* Odd PC indicates that branch is rexecuting due to exception in the
3151 * delayslot, like in real hw.
3152 */
3153 pc_start = tb->pc & ~1;
3154 dc->env = env;
3155 dc->tb = tb;
3156
3157 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3158
3159 dc->is_jmp = DISAS_NEXT;
3160 dc->ppc = pc_start;
3161 dc->pc = pc_start;
3162 dc->singlestep_enabled = env->singlestep_enabled;
3163 dc->flags_uptodate = 1;
3164 dc->flagx_known = 1;
3165 dc->flags_x = tb->flags & X_FLAG;
3166 dc->cc_x_uptodate = 0;
3167 dc->cc_mask = 0;
3168 dc->update_cc = 0;
3169
3170 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3171 dc->cc_size_uptodate = -1;
3172
3173 /* Decode TB flags. */
3174 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG);
3175 dc->delayed_branch = !!(tb->flags & 7);
3176 if (dc->delayed_branch)
3177 dc->jmp = JMP_INDIRECT;
3178 else
3179 dc->jmp = JMP_NOJMP;
3180
3181 dc->cpustate_changed = 0;
3182
3183 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3184 qemu_log(
3185 "srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
3186 "pid=%x usp=%x\n"
3187 "%x.%x.%x.%x\n"
3188 "%x.%x.%x.%x\n"
3189 "%x.%x.%x.%x\n"
3190 "%x.%x.%x.%x\n",
3191 search_pc, dc->pc, dc->ppc,
3192 (unsigned long long)tb->flags,
3193 env->btarget, (unsigned)tb->flags & 7,
3194 env->pregs[PR_CCS],
3195 env->pregs[PR_PID], env->pregs[PR_USP],
3196 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3197 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3198 env->regs[8], env->regs[9],
3199 env->regs[10], env->regs[11],
3200 env->regs[12], env->regs[13],
3201 env->regs[14], env->regs[15]);
3202 qemu_log("--------------\n");
3203 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3204 }
3205
3206 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3207 lj = -1;
3208 num_insns = 0;
3209 max_insns = tb->cflags & CF_COUNT_MASK;
3210 if (max_insns == 0)
3211 max_insns = CF_COUNT_MASK;
3212
3213 gen_icount_start();
3214 do
3215 {
3216 check_breakpoint(env, dc);
3217
3218 if (search_pc) {
3219 j = gen_opc_ptr - gen_opc_buf;
3220 if (lj < j) {
3221 lj++;
3222 while (lj < j)
3223 gen_opc_instr_start[lj++] = 0;
3224 }
3225 if (dc->delayed_branch == 1)
3226 gen_opc_pc[lj] = dc->ppc | 1;
3227 else
3228 gen_opc_pc[lj] = dc->pc;
3229 gen_opc_instr_start[lj] = 1;
3230 gen_opc_icount[lj] = num_insns;
3231 }
3232
3233 /* Pretty disas. */
3234 LOG_DIS("%8.8x:\t", dc->pc);
3235
3236 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3237 gen_io_start();
3238 dc->clear_x = 1;
3239
3240 insn_len = cris_decoder(dc);
3241 dc->ppc = dc->pc;
3242 dc->pc += insn_len;
3243 if (dc->clear_x)
3244 cris_clear_x_flag(dc);
3245
3246 num_insns++;
3247 /* Check for delayed branches here. If we do it before
3248 actually generating any host code, the simulator will just
3249 loop doing nothing for on this program location. */
3250 if (dc->delayed_branch) {
3251 dc->delayed_branch--;
3252 if (dc->delayed_branch == 0)
3253 {
3254 if (tb->flags & 7)
3255 t_gen_mov_env_TN(dslot,
3256 tcg_const_tl(0));
3257 if (dc->jmp == JMP_DIRECT) {
3258 dc->is_jmp = DISAS_NEXT;
3259 } else {
3260 t_gen_cc_jmp(env_btarget,
3261 tcg_const_tl(dc->pc));
3262 dc->is_jmp = DISAS_JUMP;
3263 }
3264 break;
3265 }
3266 }
3267
3268 /* If we are rexecuting a branch due to exceptions on
3269 delay slots dont break. */
3270 if (!(tb->pc & 1) && env->singlestep_enabled)
3271 break;
3272 } while (!dc->is_jmp && !dc->cpustate_changed
3273 && gen_opc_ptr < gen_opc_end
3274 && !singlestep
3275 && (dc->pc < next_page_start)
3276 && num_insns < max_insns);
3277
3278 npc = dc->pc;
3279 if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
3280 npc = dc->jmp_pc;
3281
3282 if (tb->cflags & CF_LAST_IO)
3283 gen_io_end();
3284 /* Force an update if the per-tb cpu state has changed. */
3285 if (dc->is_jmp == DISAS_NEXT
3286 && (dc->cpustate_changed || !dc->flagx_known
3287 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3288 dc->is_jmp = DISAS_UPDATE;
3289 tcg_gen_movi_tl(env_pc, npc);
3290 }
3291 /* Broken branch+delayslot sequence. */
3292 if (dc->delayed_branch == 1) {
3293 /* Set env->dslot to the size of the branch insn. */
3294 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3295 cris_store_direct_jmp(dc);
3296 }
3297
3298 cris_evaluate_flags (dc);
3299
3300 if (unlikely(env->singlestep_enabled)) {
3301 if (dc->is_jmp == DISAS_NEXT)
3302 tcg_gen_movi_tl(env_pc, npc);
3303 t_gen_raise_exception(EXCP_DEBUG);
3304 } else {
3305 switch(dc->is_jmp) {
3306 case DISAS_NEXT:
3307 gen_goto_tb(dc, 1, npc);
3308 break;
3309 default:
3310 case DISAS_JUMP:
3311 case DISAS_UPDATE:
3312 /* indicate that the hash table must be used
3313 to find the next TB */
3314 tcg_gen_exit_tb(0);
3315 break;
3316 case DISAS_SWI:
3317 case DISAS_TB_JUMP:
3318 /* nothing more to generate */
3319 break;
3320 }
3321 }
3322 gen_icount_end(tb, num_insns);
3323 *gen_opc_ptr = INDEX_op_end;
3324 if (search_pc) {
3325 j = gen_opc_ptr - gen_opc_buf;
3326 lj++;
3327 while (lj <= j)
3328 gen_opc_instr_start[lj++] = 0;
3329 } else {
3330 tb->size = dc->pc - pc_start;
3331 tb->icount = num_insns;
3332 }
3333
3334 #ifdef DEBUG_DISAS
3335 #if !DISAS_CRIS
3336 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3337 log_target_disas(pc_start, dc->pc - pc_start, 0);
3338 qemu_log("\nisize=%d osize=%zd\n",
3339 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3340 }
3341 #endif
3342 #endif
3343 }
3344
3345 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3346 {
3347 gen_intermediate_code_internal(env, tb, 0);
3348 }
3349
3350 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3351 {
3352 gen_intermediate_code_internal(env, tb, 1);
3353 }
3354
3355 void cpu_dump_state (CPUState *env, FILE *f,
3356 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3357 int flags)
3358 {
3359 int i;
3360 uint32_t srs;
3361
3362 if (!env || !f)
3363 return;
3364
3365 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3366 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3367 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3368 env->cc_op,
3369 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3370
3371
3372 for (i = 0; i < 16; i++) {
3373 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3374 if ((i + 1) % 4 == 0)
3375 cpu_fprintf(f, "\n");
3376 }
3377 cpu_fprintf(f, "\nspecial regs:\n");
3378 for (i = 0; i < 16; i++) {
3379 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3380 if ((i + 1) % 4 == 0)
3381 cpu_fprintf(f, "\n");
3382 }
3383 srs = env->pregs[PR_SRS];
3384 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3385 if (srs < 256) {
3386 for (i = 0; i < 16; i++) {
3387 cpu_fprintf(f, "s%2.2d=%8.8x ",
3388 i, env->sregs[srs][i]);
3389 if ((i + 1) % 4 == 0)
3390 cpu_fprintf(f, "\n");
3391 }
3392 }
3393 cpu_fprintf(f, "\n\n");
3394
3395 }
3396
3397 CPUCRISState *cpu_cris_init (const char *cpu_model)
3398 {
3399 CPUCRISState *env;
3400 static int tcg_initialized = 0;
3401 int i;
3402
3403 env = qemu_mallocz(sizeof(CPUCRISState));
3404
3405 cpu_exec_init(env);
3406 cpu_reset(env);
3407 qemu_init_vcpu(env);
3408
3409 if (tcg_initialized)
3410 return env;
3411
3412 tcg_initialized = 1;
3413
3414 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3415 cc_x = tcg_global_mem_new(TCG_AREG0,
3416 offsetof(CPUState, cc_x), "cc_x");
3417 cc_src = tcg_global_mem_new(TCG_AREG0,
3418 offsetof(CPUState, cc_src), "cc_src");
3419 cc_dest = tcg_global_mem_new(TCG_AREG0,
3420 offsetof(CPUState, cc_dest),
3421 "cc_dest");
3422 cc_result = tcg_global_mem_new(TCG_AREG0,
3423 offsetof(CPUState, cc_result),
3424 "cc_result");
3425 cc_op = tcg_global_mem_new(TCG_AREG0,
3426 offsetof(CPUState, cc_op), "cc_op");
3427 cc_size = tcg_global_mem_new(TCG_AREG0,
3428 offsetof(CPUState, cc_size),
3429 "cc_size");
3430 cc_mask = tcg_global_mem_new(TCG_AREG0,
3431 offsetof(CPUState, cc_mask),
3432 "cc_mask");
3433
3434 env_pc = tcg_global_mem_new(TCG_AREG0,
3435 offsetof(CPUState, pc),
3436 "pc");
3437 env_btarget = tcg_global_mem_new(TCG_AREG0,
3438 offsetof(CPUState, btarget),
3439 "btarget");
3440 env_btaken = tcg_global_mem_new(TCG_AREG0,
3441 offsetof(CPUState, btaken),
3442 "btaken");
3443 for (i = 0; i < 16; i++) {
3444 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3445 offsetof(CPUState, regs[i]),
3446 regnames[i]);
3447 }
3448 for (i = 0; i < 16; i++) {
3449 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3450 offsetof(CPUState, pregs[i]),
3451 pregnames[i]);
3452 }
3453
3454 #define GEN_HELPER 2
3455 #include "helper.h"
3456
3457 return env;
3458 }
3459
3460 void cpu_reset (CPUCRISState *env)
3461 {
3462 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
3463 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
3464 log_cpu_state(env, 0);
3465 }
3466
3467 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3468 tlb_flush(env, 1);
3469
3470 env->pregs[PR_VR] = 32;
3471 #if defined(CONFIG_USER_ONLY)
3472 /* start in user mode with interrupts enabled. */
3473 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3474 #else
3475 cris_mmu_init(env);
3476 env->pregs[PR_CCS] = 0;
3477 #endif
3478 }
3479
3480 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3481 unsigned long searched_pc, int pc_pos, void *puc)
3482 {
3483 env->pc = gen_opc_pc[pc_pos];
3484 }
Adding pft support to QEMU's arm cpus