hw/rc4030.c

   1 /*
   2  * QEMU JAZZ RC4030 chipset
   3  *
   4  * Copyright (c) 2007-2009 Herve Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "qemu-timer.h"
  28
  29 /********************************************************/
  30 /* debug rc4030 */
  31
  32 //#define DEBUG_RC4030
  33 //#define DEBUG_RC4030_DMA
  34
  35 #ifdef DEBUG_RC4030
  36 #define DPRINTF(fmt, ...) \
  37 do { printf("rc4030: " fmt , ## __VA_ARGS__); } while (0)
  38 static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
  39             "network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
  40 #else
  41 #define DPRINTF(fmt, ...)
  42 #endif
  43
  44 #define RC4030_ERROR(fmt, ...) \
  45 do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  46
  47 /********************************************************/
  48 /* rc4030 emulation                                     */
  49
  50 typedef struct dma_pagetable_entry {
  51     int32_t frame;
  52     int32_t owner;
  53 } __attribute__((packed)) dma_pagetable_entry;
  54
  55 #define DMA_PAGESIZE    4096
  56 #define DMA_REG_ENABLE  1
  57 #define DMA_REG_COUNT   2
  58 #define DMA_REG_ADDRESS 3
  59
  60 #define DMA_FLAG_ENABLE     0x0001
  61 #define DMA_FLAG_MEM_TO_DEV 0x0002
  62 #define DMA_FLAG_TC_INTR    0x0100
  63 #define DMA_FLAG_MEM_INTR   0x0200
  64 #define DMA_FLAG_ADDR_INTR  0x0400
  65
  66 typedef struct rc4030State
  67 {
  68     uint32_t config; /* 0x0000: RC4030 config register */
  69     uint32_t revision; /* 0x0008: RC4030 Revision register */
  70     uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
  71
  72     /* DMA */
  73     uint32_t dma_regs[8][4];
  74     uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
  75     uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
  76
  77     /* cache */
  78     uint32_t cache_maint; /* 0x0030: Cache Maintenance */
  79     uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
  80     uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
  81     uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
  82     uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
  83     uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
  84
  85     uint32_t nmi_interrupt; /* 0x0200: interrupt source */
  86     uint32_t offset210;
  87     uint32_t nvram_protect; /* 0x0220: NV ram protect register */
  88     uint32_t rem_speed[16];
  89     uint32_t imr_jazz; /* Local bus int enable mask */
  90     uint32_t isr_jazz; /* Local bus int source */
  91
  92     /* timer */
  93     QEMUTimer *periodic_timer;
  94     uint32_t itr; /* Interval timer reload */
  95
  96     qemu_irq timer_irq;
  97     qemu_irq jazz_bus_irq;
  98 } rc4030State;
  99
 100 static void set_next_tick(rc4030State *s)
 101 {
 102     qemu_irq_lower(s->timer_irq);
 103     uint32_t tm_hz;
 104
 105     tm_hz = 1000 / (s->itr + 1);
 106
 107     qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) +
 108                    get_ticks_per_sec() / tm_hz);
 109 }
 110
 111 /* called for accesses to rc4030 */
 112 static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
 113 {
 114     rc4030State *s = opaque;
 115     uint32_t val;
 116
 117     addr &= 0x3fff;
 118     switch (addr & ~0x3) {
 119     /* Global config register */
 120     case 0x0000:
 121         val = s->config;
 122         break;
 123     /* Revision register */
 124     case 0x0008:
 125         val = s->revision;
 126         break;
 127     /* Invalid Address register */
 128     case 0x0010:
 129         val = s->invalid_address_register;
 130         break;
 131     /* DMA transl. table base */
 132     case 0x0018:
 133         val = s->dma_tl_base;
 134         break;
 135     /* DMA transl. table limit */
 136     case 0x0020:
 137         val = s->dma_tl_limit;
 138         break;
 139     /* Remote Failed Address */
 140     case 0x0038:
 141         val = s->remote_failed_address;
 142         break;
 143     /* Memory Failed Address */
 144     case 0x0040:
 145         val = s->memory_failed_address;
 146         break;
 147     /* I/O Cache Byte Mask */
 148     case 0x0058:
 149         val = s->cache_bmask;
 150         /* HACK */
 151         if (s->cache_bmask == (uint32_t)-1)
 152             s->cache_bmask = 0;
 153         break;
 154     /* Remote Speed Registers */
 155     case 0x0070:
 156     case 0x0078:
 157     case 0x0080:
 158     case 0x0088:
 159     case 0x0090:
 160     case 0x0098:
 161     case 0x00a0:
 162     case 0x00a8:
 163     case 0x00b0:
 164     case 0x00b8:
 165     case 0x00c0:
 166     case 0x00c8:
 167     case 0x00d0:
 168     case 0x00d8:
 169     case 0x00e0:
 170     case 0x00e8:
 171         val = s->rem_speed[(addr - 0x0070) >> 3];
 172         break;
 173     /* DMA channel base address */
 174     case 0x0100:
 175     case 0x0108:
 176     case 0x0110:
 177     case 0x0118:
 178     case 0x0120:
 179     case 0x0128:
 180     case 0x0130:
 181     case 0x0138:
 182     case 0x0140:
 183     case 0x0148:
 184     case 0x0150:
 185     case 0x0158:
 186     case 0x0160:
 187     case 0x0168:
 188     case 0x0170:
 189     case 0x0178:
 190     case 0x0180:
 191     case 0x0188:
 192     case 0x0190:
 193     case 0x0198:
 194     case 0x01a0:
 195     case 0x01a8:
 196     case 0x01b0:
 197     case 0x01b8:
 198     case 0x01c0:
 199     case 0x01c8:
 200     case 0x01d0:
 201     case 0x01d8:
 202     case 0x01e0:
 203     case 0x01e8:
 204     case 0x01f0:
 205     case 0x01f8:
 206         {
 207             int entry = (addr - 0x0100) >> 5;
 208             int idx = (addr & 0x1f) >> 3;
 209             val = s->dma_regs[entry][idx];
 210         }
 211         break;
 212     /* Interrupt source */
 213     case 0x0200:
 214         val = s->nmi_interrupt;
 215         break;
 216     /* Error type */
 217     case 0x0208:
 218         val = 0;
 219         break;
 220     /* Offset 0x0210 */
 221     case 0x0210:
 222         val = s->offset210;
 223         break;
 224     /* NV ram protect register */
 225     case 0x0220:
 226         val = s->nvram_protect;
 227         break;
 228     /* Interval timer count */
 229     case 0x0230:
 230         val = 0;
 231         qemu_irq_lower(s->timer_irq);
 232         break;
 233     /* EISA interrupt */
 234     case 0x0238:
 235         val = 7; /* FIXME: should be read from EISA controller */
 236         break;
 237     default:
 238         RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr);
 239         val = 0;
 240         break;
 241     }
 242
 243     if ((addr & ~3) != 0x230)
 244         DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr);
 245
 246     return val;
 247 }
 248
 249 static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
 250 {
 251     uint32_t v = rc4030_readl(opaque, addr & ~0x3);
 252     if (addr & 0x2)
 253         return v >> 16;
 254     else
 255         return v & 0xffff;
 256 }
 257
 258 static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
 259 {
 260     uint32_t v = rc4030_readl(opaque, addr & ~0x3);
 261     return (v >> (8 * (addr & 0x3))) & 0xff;
 262 }
 263
 264 static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 265 {
 266     rc4030State *s = opaque;
 267     addr &= 0x3fff;
 268
 269     DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr);
 270
 271     switch (addr & ~0x3) {
 272     /* Global config register */
 273     case 0x0000:
 274         s->config = val;
 275         break;
 276     /* DMA transl. table base */
 277     case 0x0018:
 278         s->dma_tl_base = val;
 279         break;
 280     /* DMA transl. table limit */
 281     case 0x0020:
 282         s->dma_tl_limit = val;
 283         break;
 284     /* DMA transl. table invalidated */
 285     case 0x0028:
 286         break;
 287     /* Cache Maintenance */
 288     case 0x0030:
 289         s->cache_maint = val;
 290         break;
 291     /* I/O Cache Physical Tag */
 292     case 0x0048:
 293         s->cache_ptag = val;
 294         break;
 295     /* I/O Cache Logical Tag */
 296     case 0x0050:
 297         s->cache_ltag = val;
 298         break;
 299     /* I/O Cache Byte Mask */
 300     case 0x0058:
 301         s->cache_bmask |= val; /* HACK */
 302         break;
 303     /* I/O Cache Buffer Window */
 304     case 0x0060:
 305         /* HACK */
 306         if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
 307             target_phys_addr_t dest = s->cache_ptag & ~0x1;
 308             dest += (s->cache_maint & 0x3) << 3;
 309             cpu_physical_memory_rw(dest, (uint8_t*)&val, 4, 1);
 310         }
 311         break;
 312     /* Remote Speed Registers */
 313     case 0x0070:
 314     case 0x0078:
 315     case 0x0080:
 316     case 0x0088:
 317     case 0x0090:
 318     case 0x0098:
 319     case 0x00a0:
 320     case 0x00a8:
 321     case 0x00b0:
 322     case 0x00b8:
 323     case 0x00c0:
 324     case 0x00c8:
 325     case 0x00d0:
 326     case 0x00d8:
 327     case 0x00e0:
 328     case 0x00e8:
 329         s->rem_speed[(addr - 0x0070) >> 3] = val;
 330         break;
 331     /* DMA channel base address */
 332     case 0x0100:
 333     case 0x0108:
 334     case 0x0110:
 335     case 0x0118:
 336     case 0x0120:
 337     case 0x0128:
 338     case 0x0130:
 339     case 0x0138:
 340     case 0x0140:
 341     case 0x0148:
 342     case 0x0150:
 343     case 0x0158:
 344     case 0x0160:
 345     case 0x0168:
 346     case 0x0170:
 347     case 0x0178:
 348     case 0x0180:
 349     case 0x0188:
 350     case 0x0190:
 351     case 0x0198:
 352     case 0x01a0:
 353     case 0x01a8:
 354     case 0x01b0:
 355     case 0x01b8:
 356     case 0x01c0:
 357     case 0x01c8:
 358     case 0x01d0:
 359     case 0x01d8:
 360     case 0x01e0:
 361     case 0x01e8:
 362     case 0x01f0:
 363     case 0x01f8:
 364         {
 365             int entry = (addr - 0x0100) >> 5;
 366             int idx = (addr & 0x1f) >> 3;
 367             s->dma_regs[entry][idx] = val;
 368         }
 369         break;
 370     /* Offset 0x0210 */
 371     case 0x0210:
 372         s->offset210 = val;
 373         break;
 374     /* Interval timer reload */
 375     case 0x0228:
 376         s->itr = val;
 377         qemu_irq_lower(s->timer_irq);
 378         set_next_tick(s);
 379         break;
 380     /* EISA interrupt */
 381     case 0x0238:
 382         break;
 383     default:
 384         RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr);
 385         break;
 386     }
 387 }
 388
 389 static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 390 {
 391     uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
 392
 393     if (addr & 0x2)
 394         val = (val << 16) | (old_val & 0x0000ffff);
 395     else
 396         val = val | (old_val & 0xffff0000);
 397     rc4030_writel(opaque, addr & ~0x3, val);
 398 }
 399
 400 static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 401 {
 402     uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
 403
 404     switch (addr & 3) {
 405     case 0:
 406         val = val | (old_val & 0xffffff00);
 407         break;
 408     case 1:
 409         val = (val << 8) | (old_val & 0xffff00ff);
 410         break;
 411     case 2:
 412         val = (val << 16) | (old_val & 0xff00ffff);
 413         break;
 414     case 3:
 415         val = (val << 24) | (old_val & 0x00ffffff);
 416         break;
 417     }
 418     rc4030_writel(opaque, addr & ~0x3, val);
 419 }
 420
 421 static CPUReadMemoryFunc * const rc4030_read[3] = {
 422     rc4030_readb,
 423     rc4030_readw,
 424     rc4030_readl,
 425 };
 426
 427 static CPUWriteMemoryFunc * const rc4030_write[3] = {
 428     rc4030_writeb,
 429     rc4030_writew,
 430     rc4030_writel,
 431 };
 432
 433 static void update_jazz_irq(rc4030State *s)
 434 {
 435     uint16_t pending;
 436
 437     pending = s->isr_jazz & s->imr_jazz;
 438
 439 #ifdef DEBUG_RC4030
 440     if (s->isr_jazz != 0) {
 441         uint32_t irq = 0;
 442         DPRINTF("pending irqs:");
 443         for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) {
 444             if (s->isr_jazz & (1 << irq)) {
 445                 printf(" %s", irq_names[irq]);
 446                 if (!(s->imr_jazz & (1 << irq))) {
 447                     printf("(ignored)");
 448                 }
 449             }
 450         }
 451         printf("\n");
 452     }
 453 #endif
 454
 455     if (pending != 0)
 456         qemu_irq_raise(s->jazz_bus_irq);
 457     else
 458         qemu_irq_lower(s->jazz_bus_irq);
 459 }
 460
 461 static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
 462 {
 463     rc4030State *s = opaque;
 464
 465     if (level) {
 466         s->isr_jazz |= 1 << irq;
 467     } else {
 468         s->isr_jazz &= ~(1 << irq);
 469     }
 470
 471     update_jazz_irq(s);
 472 }
 473
 474 static void rc4030_periodic_timer(void *opaque)
 475 {
 476     rc4030State *s = opaque;
 477
 478     set_next_tick(s);
 479     qemu_irq_raise(s->timer_irq);
 480 }
 481
 482 static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
 483 {
 484     rc4030State *s = opaque;
 485     uint32_t val;
 486     uint32_t irq;
 487     addr &= 0xfff;
 488
 489     switch (addr) {
 490     /* Local bus int source */
 491     case 0x00: {
 492         uint32_t pending = s->isr_jazz & s->imr_jazz;
 493         val = 0;
 494         irq = 0;
 495         while (pending) {
 496             if (pending & 1) {
 497                 DPRINTF("returning irq %s\n", irq_names[irq]);
 498                 val = (irq + 1) << 2;
 499                 break;
 500             }
 501             irq++;
 502             pending >>= 1;
 503         }
 504         break;
 505     }
 506     /* Local bus int enable mask */
 507     case 0x02:
 508         val = s->imr_jazz;
 509         break;
 510     default:
 511         RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr);
 512         val = 0;
 513     }
 514
 515     DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr);
 516
 517     return val;
 518 }
 519
 520 static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
 521 {
 522     uint32_t v;
 523     v = jazzio_readw(opaque, addr & ~0x1);
 524     return (v >> (8 * (addr & 0x1))) & 0xff;
 525 }
 526
 527 static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
 528 {
 529     uint32_t v;
 530     v = jazzio_readw(opaque, addr);
 531     v |= jazzio_readw(opaque, addr + 2) << 16;
 532     return v;
 533 }
 534
 535 static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 536 {
 537     rc4030State *s = opaque;
 538     addr &= 0xfff;
 539
 540     DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr);
 541
 542     switch (addr) {
 543     /* Local bus int enable mask */
 544     case 0x02:
 545         s->imr_jazz = val;
 546         update_jazz_irq(s);
 547         break;
 548     default:
 549         RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr);
 550         break;
 551     }
 552 }
 553
 554 static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 555 {
 556     uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
 557
 558     switch (addr & 1) {
 559     case 0:
 560         val = val | (old_val & 0xff00);
 561         break;
 562     case 1:
 563         val = (val << 8) | (old_val & 0x00ff);
 564         break;
 565     }
 566     jazzio_writew(opaque, addr & ~0x1, val);
 567 }
 568
 569 static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 570 {
 571     jazzio_writew(opaque, addr, val & 0xffff);
 572     jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
 573 }
 574
 575 static CPUReadMemoryFunc * const jazzio_read[3] = {
 576     jazzio_readb,
 577     jazzio_readw,
 578     jazzio_readl,
 579 };
 580
 581 static CPUWriteMemoryFunc * const jazzio_write[3] = {
 582     jazzio_writeb,
 583     jazzio_writew,
 584     jazzio_writel,
 585 };
 586
 587 static void rc4030_reset(void *opaque)
 588 {
 589     rc4030State *s = opaque;
 590     int i;
 591
 592     s->config = 0x410; /* some boards seem to accept 0x104 too */
 593     s->revision = 1;
 594     s->invalid_address_register = 0;
 595
 596     memset(s->dma_regs, 0, sizeof(s->dma_regs));
 597     s->dma_tl_base = s->dma_tl_limit = 0;
 598
 599     s->remote_failed_address = s->memory_failed_address = 0;
 600     s->cache_maint = 0;
 601     s->cache_ptag = s->cache_ltag = 0;
 602     s->cache_bmask = 0;
 603
 604     s->offset210 = 0x18186;
 605     s->nvram_protect = 7;
 606     for (i = 0; i < 15; i++)
 607         s->rem_speed[i] = 7;
 608     s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
 609     s->isr_jazz = 0;
 610
 611     s->itr = 0;
 612
 613     qemu_irq_lower(s->timer_irq);
 614     qemu_irq_lower(s->jazz_bus_irq);
 615 }
 616
 617 static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
 618 {
 619     rc4030State* s = opaque;
 620     int i, j;
 621
 622     if (version_id != 2)
 623         return -EINVAL;
 624
 625     s->config = qemu_get_be32(f);
 626     s->invalid_address_register = qemu_get_be32(f);
 627     for (i = 0; i < 8; i++)
 628         for (j = 0; j < 4; j++)
 629             s->dma_regs[i][j] = qemu_get_be32(f);
 630     s->dma_tl_base = qemu_get_be32(f);
 631     s->dma_tl_limit = qemu_get_be32(f);
 632     s->cache_maint = qemu_get_be32(f);
 633     s->remote_failed_address = qemu_get_be32(f);
 634     s->memory_failed_address = qemu_get_be32(f);
 635     s->cache_ptag = qemu_get_be32(f);
 636     s->cache_ltag = qemu_get_be32(f);
 637     s->cache_bmask = qemu_get_be32(f);
 638     s->offset210 = qemu_get_be32(f);
 639     s->nvram_protect = qemu_get_be32(f);
 640     for (i = 0; i < 15; i++)
 641         s->rem_speed[i] = qemu_get_be32(f);
 642     s->imr_jazz = qemu_get_be32(f);
 643     s->isr_jazz = qemu_get_be32(f);
 644     s->itr = qemu_get_be32(f);
 645
 646     set_next_tick(s);
 647     update_jazz_irq(s);
 648
 649     return 0;
 650 }
 651
 652 static void rc4030_save(QEMUFile *f, void *opaque)
 653 {
 654     rc4030State* s = opaque;
 655     int i, j;
 656
 657     qemu_put_be32(f, s->config);
 658     qemu_put_be32(f, s->invalid_address_register);
 659     for (i = 0; i < 8; i++)
 660         for (j = 0; j < 4; j++)
 661             qemu_put_be32(f, s->dma_regs[i][j]);
 662     qemu_put_be32(f, s->dma_tl_base);
 663     qemu_put_be32(f, s->dma_tl_limit);
 664     qemu_put_be32(f, s->cache_maint);
 665     qemu_put_be32(f, s->remote_failed_address);
 666     qemu_put_be32(f, s->memory_failed_address);
 667     qemu_put_be32(f, s->cache_ptag);
 668     qemu_put_be32(f, s->cache_ltag);
 669     qemu_put_be32(f, s->cache_bmask);
 670     qemu_put_be32(f, s->offset210);
 671     qemu_put_be32(f, s->nvram_protect);
 672     for (i = 0; i < 15; i++)
 673         qemu_put_be32(f, s->rem_speed[i]);
 674     qemu_put_be32(f, s->imr_jazz);
 675     qemu_put_be32(f, s->isr_jazz);
 676     qemu_put_be32(f, s->itr);
 677 }
 678
 679 void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
 680 {
 681     rc4030State *s = opaque;
 682     target_phys_addr_t entry_addr;
 683     target_phys_addr_t phys_addr;
 684     dma_pagetable_entry entry;
 685     int index;
 686     int ncpy, i;
 687
 688     i = 0;
 689     for (;;) {
 690         if (i == len) {
 691             break;
 692         }
 693
 694         ncpy = DMA_PAGESIZE - (addr & (DMA_PAGESIZE - 1));
 695         if (ncpy > len - i)
 696             ncpy = len - i;
 697
 698         /* Get DMA translation table entry */
 699         index = addr / DMA_PAGESIZE;
 700         if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) {
 701             break;
 702         }
 703         entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
 704         /* XXX: not sure. should we really use only lowest bits? */
 705         entry_addr &= 0x7fffffff;
 706         cpu_physical_memory_rw(entry_addr, (uint8_t *)&entry, sizeof(entry), 0);
 707
 708         /* Read/write data at right place */
 709         phys_addr = entry.frame + (addr & (DMA_PAGESIZE - 1));
 710         cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write);
 711
 712         i += ncpy;
 713         addr += ncpy;
 714     }
 715 }
 716
 717 static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
 718 {
 719     rc4030State *s = opaque;
 720     target_phys_addr_t dma_addr;
 721     int dev_to_mem;
 722
 723     s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
 724
 725     /* Check DMA channel consistency */
 726     dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
 727     if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
 728         (is_write != dev_to_mem)) {
 729         s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
 730         s->nmi_interrupt |= 1 << n;
 731         return;
 732     }
 733
 734     /* Get start address and len */
 735     if (len > s->dma_regs[n][DMA_REG_COUNT])
 736         len = s->dma_regs[n][DMA_REG_COUNT];
 737     dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
 738
 739     /* Read/write data at right place */
 740     rc4030_dma_memory_rw(opaque, dma_addr, buf, len, is_write);
 741
 742     s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
 743     s->dma_regs[n][DMA_REG_COUNT] -= len;
 744
 745 #ifdef DEBUG_RC4030_DMA
 746     {
 747         int i, j;
 748         printf("rc4030 dma: Copying %d bytes %s host %p\n",
 749             len, is_write ? "from" : "to", buf);
 750         for (i = 0; i < len; i += 16) {
 751             int n = min(16, len - i);
 752             for (j = 0; j < n; j++)
 753                 printf("%02x ", buf[i + j]);
 754             while (j++ < 16)
 755                 printf("   ");
 756             printf("| ");
 757             for (j = 0; j < n; j++)
 758                 printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.');
 759             printf("\n");
 760         }
 761     }
 762 #endif
 763 }
 764
 765 struct rc4030DMAState {
 766     void *opaque;
 767     int n;
 768 };
 769
 770 void rc4030_dma_read(void *dma, uint8_t *buf, int len)
 771 {
 772     rc4030_dma s = dma;
 773     rc4030_do_dma(s->opaque, s->n, buf, len, 0);
 774 }
 775
 776 void rc4030_dma_write(void *dma, uint8_t *buf, int len)
 777 {
 778     rc4030_dma s = dma;
 779     rc4030_do_dma(s->opaque, s->n, buf, len, 1);
 780 }
 781
 782 static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
 783 {
 784     rc4030_dma *s;
 785     struct rc4030DMAState *p;
 786     int i;
 787
 788     s = (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n);
 789     p = (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAState) * n);
 790     for (i = 0; i < n; i++) {
 791         p->opaque = opaque;
 792         p->n = i;
 793         s[i] = p;
 794         p++;
 795     }
 796     return s;
 797 }
 798
 799 void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
 800                   qemu_irq **irqs, rc4030_dma **dmas)
 801 {
 802     rc4030State *s;
 803     int s_chipset, s_jazzio;
 804
 805     s = qemu_mallocz(sizeof(rc4030State));
 806
 807     *irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
 808     *dmas = rc4030_allocate_dmas(s, 4);
 809
 810     s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
 811     s->timer_irq = timer;
 812     s->jazz_bus_irq = jazz_bus;
 813
 814     qemu_register_reset(rc4030_reset, s);
 815     register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s);
 816     rc4030_reset(s);
 817
 818     s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s);
 819     cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
 820     s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s);
 821     cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio);
 822
 823     return s;
 824 }