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qcow2: Make cache=writethrough default
[armpft.git] / linux-user / main.c
blobd49605bd44d568599dec95321a080102fba4e409
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <stdarg.h>
24 #include <string.h>
25 #include <errno.h>
26 #include <unistd.h>
27 #include <sys/mman.h>
28 #include <sys/syscall.h>
29
30 #include "qemu.h"
31 #include "qemu-common.h"
32 #include "cache-utils.h"
33 /* For tb_lock */
34 #include "exec-all.h"
35
36
37 #include "envlist.h"
38
39 #define DEBUG_LOGFILE "/tmp/qemu.log"
40
41 char *exec_path;
42
43 int singlestep;
44
45 static const char *interp_prefix = CONFIG_QEMU_PREFIX;
46 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
47
48 #if defined(__i386__) && !defined(CONFIG_STATIC)
49 /* Force usage of an ELF interpreter even if it is an ELF shared
50 object ! */
51 const char interp[] __attribute__((section(".interp"))) = "/lib/ld-linux.so.2";
52 #endif
53
54 /* for recent libc, we add these dummy symbols which are not declared
55 when generating a linked object (bug in ld ?) */
56 #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(CONFIG_STATIC)
57 asm(".globl __preinit_array_start\n"
58 ".globl __preinit_array_end\n"
59 ".globl __init_array_start\n"
60 ".globl __init_array_end\n"
61 ".globl __fini_array_start\n"
62 ".globl __fini_array_end\n"
63 ".section \".rodata\"\n"
64 "__preinit_array_start:\n"
65 "__preinit_array_end:\n"
66 "__init_array_start:\n"
67 "__init_array_end:\n"
68 "__fini_array_start:\n"
69 "__fini_array_end:\n"
70 ".long 0\n"
71 ".previous\n");
72 #endif
73
74 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
77 unsigned long x86_stack_size = 512 * 1024;
78
79 void gemu_log(const char *fmt, ...)
80 {
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86 }
87
88 void cpu_outb(CPUState *env, int addr, int val)
89 {
90 fprintf(stderr, "outb: port=0x%04x, data=%02x\n", addr, val);
91 }
92
93 void cpu_outw(CPUState *env, int addr, int val)
94 {
95 fprintf(stderr, "outw: port=0x%04x, data=%04x\n", addr, val);
96 }
97
98 void cpu_outl(CPUState *env, int addr, int val)
99 {
100 fprintf(stderr, "outl: port=0x%04x, data=%08x\n", addr, val);
101 }
102
103 int cpu_inb(CPUState *env, int addr)
104 {
105 fprintf(stderr, "inb: port=0x%04x\n", addr);
106 return 0;
107 }
108
109 int cpu_inw(CPUState *env, int addr)
110 {
111 fprintf(stderr, "inw: port=0x%04x\n", addr);
112 return 0;
113 }
114
115 int cpu_inl(CPUState *env, int addr)
116 {
117 fprintf(stderr, "inl: port=0x%04x\n", addr);
118 return 0;
119 }
120
121 #if defined(TARGET_I386)
122 int cpu_get_pic_interrupt(CPUState *env)
123 {
124 return -1;
125 }
126 #endif
127
128 /* timers for rdtsc */
129
130 #if 0
131
132 static uint64_t emu_time;
133
134 int64_t cpu_get_real_ticks(void)
135 {
136 return emu_time++;
137 }
138
139 #endif
140
141 #if defined(USE_NPTL)
142 /***********************************************************/
143 /* Helper routines for implementing atomic operations. */
144
145 /* To implement exclusive operations we force all cpus to syncronise.
146 We don't require a full sync, only that no cpus are executing guest code.
147 The alternative is to map target atomic ops onto host equivalents,
148 which requires quite a lot of per host/target work. */
149 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
150 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
151 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
152 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
153 static int pending_cpus;
154
155 /* Make sure everything is in a consistent state for calling fork(). */
156 void fork_start(void)
157 {
158 mmap_fork_start();
159 pthread_mutex_lock(&tb_lock);
160 pthread_mutex_lock(&exclusive_lock);
161 }
162
163 void fork_end(int child)
164 {
165 if (child) {
166 /* Child processes created by fork() only have a single thread.
167 Discard information about the parent threads. */
168 first_cpu = thread_env;
169 thread_env->next_cpu = NULL;
170 pending_cpus = 0;
171 pthread_mutex_init(&exclusive_lock, NULL);
172 pthread_mutex_init(&cpu_list_mutex, NULL);
173 pthread_cond_init(&exclusive_cond, NULL);
174 pthread_cond_init(&exclusive_resume, NULL);
175 pthread_mutex_init(&tb_lock, NULL);
176 gdbserver_fork(thread_env);
177 } else {
178 pthread_mutex_unlock(&exclusive_lock);
179 pthread_mutex_unlock(&tb_lock);
180 }
181 mmap_fork_end(child);
182 }
183
184 /* Wait for pending exclusive operations to complete. The exclusive lock
185 must be held. */
186 static inline void exclusive_idle(void)
187 {
188 while (pending_cpus) {
189 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
190 }
191 }
192
193 /* Start an exclusive operation.
194 Must only be called from outside cpu_arm_exec. */
195 static inline void start_exclusive(void)
196 {
197 CPUState *other;
198 pthread_mutex_lock(&exclusive_lock);
199 exclusive_idle();
200
201 pending_cpus = 1;
202 /* Make all other cpus stop executing. */
203 for (other = first_cpu; other; other = other->next_cpu) {
204 if (other->running) {
205 pending_cpus++;
206 cpu_exit(other);
207 }
208 }
209 if (pending_cpus > 1) {
210 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
211 }
212 }
213
214 /* Finish an exclusive operation. */
215 static inline void end_exclusive(void)
216 {
217 pending_cpus = 0;
218 pthread_cond_broadcast(&exclusive_resume);
219 pthread_mutex_unlock(&exclusive_lock);
220 }
221
222 /* Wait for exclusive ops to finish, and begin cpu execution. */
223 static inline void cpu_exec_start(CPUState *env)
224 {
225 pthread_mutex_lock(&exclusive_lock);
226 exclusive_idle();
227 env->running = 1;
228 pthread_mutex_unlock(&exclusive_lock);
229 }
230
231 /* Mark cpu as not executing, and release pending exclusive ops. */
232 static inline void cpu_exec_end(CPUState *env)
233 {
234 pthread_mutex_lock(&exclusive_lock);
235 env->running = 0;
236 if (pending_cpus > 1) {
237 pending_cpus--;
238 if (pending_cpus == 1) {
239 pthread_cond_signal(&exclusive_cond);
240 }
241 }
242 exclusive_idle();
243 pthread_mutex_unlock(&exclusive_lock);
244 }
245
246 void cpu_list_lock(void)
247 {
248 pthread_mutex_lock(&cpu_list_mutex);
249 }
250
251 void cpu_list_unlock(void)
252 {
253 pthread_mutex_unlock(&cpu_list_mutex);
254 }
255 #else /* if !USE_NPTL */
256 /* These are no-ops because we are not threadsafe. */
257 static inline void cpu_exec_start(CPUState *env)
258 {
259 }
260
261 static inline void cpu_exec_end(CPUState *env)
262 {
263 }
264
265 static inline void start_exclusive(void)
266 {
267 }
268
269 static inline void end_exclusive(void)
270 {
271 }
272
273 void fork_start(void)
274 {
275 }
276
277 void fork_end(int child)
278 {
279 if (child) {
280 gdbserver_fork(thread_env);
281 }
282 }
283
284 void cpu_list_lock(void)
285 {
286 }
287
288 void cpu_list_unlock(void)
289 {
290 }
291 #endif
292
293
294 #ifdef TARGET_I386
295 /***********************************************************/
296 /* CPUX86 core interface */
297
298 void cpu_smm_update(CPUState *env)
299 {
300 }
301
302 uint64_t cpu_get_tsc(CPUX86State *env)
303 {
304 return cpu_get_real_ticks();
305 }
306
307 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
308 int flags)
309 {
310 unsigned int e1, e2;
311 uint32_t *p;
312 e1 = (addr << 16) | (limit & 0xffff);
313 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
314 e2 |= flags;
315 p = ptr;
316 p[0] = tswap32(e1);
317 p[1] = tswap32(e2);
318 }
319
320 static uint64_t *idt_table;
321 #ifdef TARGET_X86_64
322 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
323 uint64_t addr, unsigned int sel)
324 {
325 uint32_t *p, e1, e2;
326 e1 = (addr & 0xffff) | (sel << 16);
327 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
328 p = ptr;
329 p[0] = tswap32(e1);
330 p[1] = tswap32(e2);
331 p[2] = tswap32(addr >> 32);
332 p[3] = 0;
333 }
334 /* only dpl matters as we do only user space emulation */
335 static void set_idt(int n, unsigned int dpl)
336 {
337 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
338 }
339 #else
340 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
341 uint32_t addr, unsigned int sel)
342 {
343 uint32_t *p, e1, e2;
344 e1 = (addr & 0xffff) | (sel << 16);
345 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
346 p = ptr;
347 p[0] = tswap32(e1);
348 p[1] = tswap32(e2);
349 }
350
351 /* only dpl matters as we do only user space emulation */
352 static void set_idt(int n, unsigned int dpl)
353 {
354 set_gate(idt_table + n, 0, dpl, 0, 0);
355 }
356 #endif
357
358 void cpu_loop(CPUX86State *env)
359 {
360 int trapnr;
361 abi_ulong pc;
362 target_siginfo_t info;
363
364 for(;;) {
365 trapnr = cpu_x86_exec(env);
366 switch(trapnr) {
367 case 0x80:
368 /* linux syscall from int $0x80 */
369 env->regs[R_EAX] = do_syscall(env,
370 env->regs[R_EAX],
371 env->regs[R_EBX],
372 env->regs[R_ECX],
373 env->regs[R_EDX],
374 env->regs[R_ESI],
375 env->regs[R_EDI],
376 env->regs[R_EBP]);
377 break;
378 #ifndef TARGET_ABI32
379 case EXCP_SYSCALL:
380 /* linux syscall from syscall intruction */
381 env->regs[R_EAX] = do_syscall(env,
382 env->regs[R_EAX],
383 env->regs[R_EDI],
384 env->regs[R_ESI],
385 env->regs[R_EDX],
386 env->regs[10],
387 env->regs[8],
388 env->regs[9]);
389 env->eip = env->exception_next_eip;
390 break;
391 #endif
392 case EXCP0B_NOSEG:
393 case EXCP0C_STACK:
394 info.si_signo = SIGBUS;
395 info.si_errno = 0;
396 info.si_code = TARGET_SI_KERNEL;
397 info._sifields._sigfault._addr = 0;
398 queue_signal(env, info.si_signo, &info);
399 break;
400 case EXCP0D_GPF:
401 /* XXX: potential problem if ABI32 */
402 #ifndef TARGET_X86_64
403 if (env->eflags & VM_MASK) {
404 handle_vm86_fault(env);
405 } else
406 #endif
407 {
408 info.si_signo = SIGSEGV;
409 info.si_errno = 0;
410 info.si_code = TARGET_SI_KERNEL;
411 info._sifields._sigfault._addr = 0;
412 queue_signal(env, info.si_signo, &info);
413 }
414 break;
415 case EXCP0E_PAGE:
416 info.si_signo = SIGSEGV;
417 info.si_errno = 0;
418 if (!(env->error_code & 1))
419 info.si_code = TARGET_SEGV_MAPERR;
420 else
421 info.si_code = TARGET_SEGV_ACCERR;
422 info._sifields._sigfault._addr = env->cr[2];
423 queue_signal(env, info.si_signo, &info);
424 break;
425 case EXCP00_DIVZ:
426 #ifndef TARGET_X86_64
427 if (env->eflags & VM_MASK) {
428 handle_vm86_trap(env, trapnr);
429 } else
430 #endif
431 {
432 /* division by zero */
433 info.si_signo = SIGFPE;
434 info.si_errno = 0;
435 info.si_code = TARGET_FPE_INTDIV;
436 info._sifields._sigfault._addr = env->eip;
437 queue_signal(env, info.si_signo, &info);
438 }
439 break;
440 case EXCP01_DB:
441 case EXCP03_INT3:
442 #ifndef TARGET_X86_64
443 if (env->eflags & VM_MASK) {
444 handle_vm86_trap(env, trapnr);
445 } else
446 #endif
447 {
448 info.si_signo = SIGTRAP;
449 info.si_errno = 0;
450 if (trapnr == EXCP01_DB) {
451 info.si_code = TARGET_TRAP_BRKPT;
452 info._sifields._sigfault._addr = env->eip;
453 } else {
454 info.si_code = TARGET_SI_KERNEL;
455 info._sifields._sigfault._addr = 0;
456 }
457 queue_signal(env, info.si_signo, &info);
458 }
459 break;
460 case EXCP04_INTO:
461 case EXCP05_BOUND:
462 #ifndef TARGET_X86_64
463 if (env->eflags & VM_MASK) {
464 handle_vm86_trap(env, trapnr);
465 } else
466 #endif
467 {
468 info.si_signo = SIGSEGV;
469 info.si_errno = 0;
470 info.si_code = TARGET_SI_KERNEL;
471 info._sifields._sigfault._addr = 0;
472 queue_signal(env, info.si_signo, &info);
473 }
474 break;
475 case EXCP06_ILLOP:
476 info.si_signo = SIGILL;
477 info.si_errno = 0;
478 info.si_code = TARGET_ILL_ILLOPN;
479 info._sifields._sigfault._addr = env->eip;
480 queue_signal(env, info.si_signo, &info);
481 break;
482 case EXCP_INTERRUPT:
483 /* just indicate that signals should be handled asap */
484 break;
485 case EXCP_DEBUG:
486 {
487 int sig;
488
489 sig = gdb_handlesig (env, TARGET_SIGTRAP);
490 if (sig)
491 {
492 info.si_signo = sig;
493 info.si_errno = 0;
494 info.si_code = TARGET_TRAP_BRKPT;
495 queue_signal(env, info.si_signo, &info);
496 }
497 }
498 break;
499 default:
500 pc = env->segs[R_CS].base + env->eip;
501 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
502 (long)pc, trapnr);
503 abort();
504 }
505 process_pending_signals(env);
506 }
507 }
508 #endif
509
510 #ifdef TARGET_ARM
511
512 static void arm_cache_flush(abi_ulong start, abi_ulong last)
513 {
514 abi_ulong addr, last1;
515
516 if (last < start)
517 return;
518 addr = start;
519 for(;;) {
520 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
521 if (last1 > last)
522 last1 = last;
523 tb_invalidate_page_range(addr, last1 + 1);
524 if (last1 == last)
525 break;
526 addr = last1 + 1;
527 }
528 }
529
530 /* Handle a jump to the kernel code page. */
531 static int
532 do_kernel_trap(CPUARMState *env)
533 {
534 uint32_t addr;
535 uint32_t cpsr;
536 uint32_t val;
537
538 switch (env->regs[15]) {
539 case 0xffff0fa0: /* __kernel_memory_barrier */
540 /* ??? No-op. Will need to do better for SMP. */
541 break;
542 case 0xffff0fc0: /* __kernel_cmpxchg */
543 /* XXX: This only works between threads, not between processes.
544 It's probably possible to implement this with native host
545 operations. However things like ldrex/strex are much harder so
546 there's not much point trying. */
547 start_exclusive();
548 cpsr = cpsr_read(env);
549 addr = env->regs[2];
550 /* FIXME: This should SEGV if the access fails. */
551 if (get_user_u32(val, addr))
552 val = ~env->regs[0];
553 if (val == env->regs[0]) {
554 val = env->regs[1];
555 /* FIXME: Check for segfaults. */
556 put_user_u32(val, addr);
557 env->regs[0] = 0;
558 cpsr |= CPSR_C;
559 } else {
560 env->regs[0] = -1;
561 cpsr &= ~CPSR_C;
562 }
563 cpsr_write(env, cpsr, CPSR_C);
564 end_exclusive();
565 break;
566 case 0xffff0fe0: /* __kernel_get_tls */
567 env->regs[0] = env->cp15.c13_tls2;
568 break;
569 default:
570 return 1;
571 }
572 /* Jump back to the caller. */
573 addr = env->regs[14];
574 if (addr & 1) {
575 env->thumb = 1;
576 addr &= ~1;
577 }
578 env->regs[15] = addr;
579
580 return 0;
581 }
582
583 void cpu_loop(CPUARMState *env)
584 {
585 int trapnr;
586 unsigned int n, insn;
587 target_siginfo_t info;
588 uint32_t addr;
589
590 for(;;) {
591 cpu_exec_start(env);
592 trapnr = cpu_arm_exec(env);
593 cpu_exec_end(env);
594 switch(trapnr) {
595 case EXCP_UDEF:
596 {
597 TaskState *ts = env->opaque;
598 uint32_t opcode;
599 int rc;
600
601 /* we handle the FPU emulation here, as Linux */
602 /* we get the opcode */
603 /* FIXME - what to do if get_user() fails? */
604 get_user_u32(opcode, env->regs[15]);
605
606 rc = EmulateAll(opcode, &ts->fpa, env);
607 if (rc == 0) { /* illegal instruction */
608 info.si_signo = SIGILL;
609 info.si_errno = 0;
610 info.si_code = TARGET_ILL_ILLOPN;
611 info._sifields._sigfault._addr = env->regs[15];
612 queue_signal(env, info.si_signo, &info);
613 } else if (rc < 0) { /* FP exception */
614 int arm_fpe=0;
615
616 /* translate softfloat flags to FPSR flags */
617 if (-rc & float_flag_invalid)
618 arm_fpe |= BIT_IOC;
619 if (-rc & float_flag_divbyzero)
620 arm_fpe |= BIT_DZC;
621 if (-rc & float_flag_overflow)
622 arm_fpe |= BIT_OFC;
623 if (-rc & float_flag_underflow)
624 arm_fpe |= BIT_UFC;
625 if (-rc & float_flag_inexact)
626 arm_fpe |= BIT_IXC;
627
628 FPSR fpsr = ts->fpa.fpsr;
629 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
630
631 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
632 info.si_signo = SIGFPE;
633 info.si_errno = 0;
634
635 /* ordered by priority, least first */
636 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
637 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
638 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
639 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
640 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
641
642 info._sifields._sigfault._addr = env->regs[15];
643 queue_signal(env, info.si_signo, &info);
644 } else {
645 env->regs[15] += 4;
646 }
647
648 /* accumulate unenabled exceptions */
649 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
650 fpsr |= BIT_IXC;
651 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
652 fpsr |= BIT_UFC;
653 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
654 fpsr |= BIT_OFC;
655 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
656 fpsr |= BIT_DZC;
657 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
658 fpsr |= BIT_IOC;
659 ts->fpa.fpsr=fpsr;
660 } else { /* everything OK */
661 /* increment PC */
662 env->regs[15] += 4;
663 }
664 }
665 break;
666 case EXCP_SWI:
667 case EXCP_BKPT:
668 {
669 env->eabi = 1;
670 /* system call */
671 if (trapnr == EXCP_BKPT) {
672 if (env->thumb) {
673 /* FIXME - what to do if get_user() fails? */
674 get_user_u16(insn, env->regs[15]);
675 n = insn & 0xff;
676 env->regs[15] += 2;
677 } else {
678 /* FIXME - what to do if get_user() fails? */
679 get_user_u32(insn, env->regs[15]);
680 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
681 env->regs[15] += 4;
682 }
683 } else {
684 if (env->thumb) {
685 /* FIXME - what to do if get_user() fails? */
686 get_user_u16(insn, env->regs[15] - 2);
687 n = insn & 0xff;
688 } else {
689 /* FIXME - what to do if get_user() fails? */
690 get_user_u32(insn, env->regs[15] - 4);
691 n = insn & 0xffffff;
692 }
693 }
694
695 if (n == ARM_NR_cacheflush) {
696 arm_cache_flush(env->regs[0], env->regs[1]);
697 } else if (n == ARM_NR_semihosting
698 || n == ARM_NR_thumb_semihosting) {
699 env->regs[0] = do_arm_semihosting (env);
700 } else if (n == 0 || n >= ARM_SYSCALL_BASE
701 || (env->thumb && n == ARM_THUMB_SYSCALL)) {
702 /* linux syscall */
703 if (env->thumb || n == 0) {
704 n = env->regs[7];
705 } else {
706 n -= ARM_SYSCALL_BASE;
707 env->eabi = 0;
708 }
709 if ( n > ARM_NR_BASE) {
710 switch (n) {
711 case ARM_NR_cacheflush:
712 arm_cache_flush(env->regs[0], env->regs[1]);
713 break;
714 case ARM_NR_set_tls:
715 cpu_set_tls(env, env->regs[0]);
716 env->regs[0] = 0;
717 break;
718 default:
719 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
720 n);
721 env->regs[0] = -TARGET_ENOSYS;
722 break;
723 }
724 } else {
725 env->regs[0] = do_syscall(env,
726 n,
727 env->regs[0],
728 env->regs[1],
729 env->regs[2],
730 env->regs[3],
731 env->regs[4],
732 env->regs[5]);
733 }
734 } else {
735 goto error;
736 }
737 }
738 break;
739 case EXCP_INTERRUPT:
740 /* just indicate that signals should be handled asap */
741 break;
742 case EXCP_PREFETCH_ABORT:
743 addr = env->cp15.c6_insn;
744 goto do_segv;
745 case EXCP_DATA_ABORT:
746 addr = env->cp15.c6_data;
747 goto do_segv;
748 do_segv:
749 {
750 info.si_signo = SIGSEGV;
751 info.si_errno = 0;
752 /* XXX: check env->error_code */
753 info.si_code = TARGET_SEGV_MAPERR;
754 info._sifields._sigfault._addr = addr;
755 queue_signal(env, info.si_signo, &info);
756 }
757 break;
758 case EXCP_DEBUG:
759 {
760 int sig;
761
762 sig = gdb_handlesig (env, TARGET_SIGTRAP);
763 if (sig)
764 {
765 info.si_signo = sig;
766 info.si_errno = 0;
767 info.si_code = TARGET_TRAP_BRKPT;
768 queue_signal(env, info.si_signo, &info);
769 }
770 }
771 break;
772 case EXCP_KERNEL_TRAP:
773 if (do_kernel_trap(env))
774 goto error;
775 break;
776 default:
777 error:
778 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
779 trapnr);
780 cpu_dump_state(env, stderr, fprintf, 0);
781 abort();
782 }
783 process_pending_signals(env);
784 }
785 }
786
787 #endif
788
789 #ifdef TARGET_SPARC
790 #define SPARC64_STACK_BIAS 2047
791
792 //#define DEBUG_WIN
793
794 /* WARNING: dealing with register windows _is_ complicated. More info
795 can be found at http://www.sics.se/~psm/sparcstack.html */
796 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
797 {
798 index = (index + cwp * 16) % (16 * env->nwindows);
799 /* wrap handling : if cwp is on the last window, then we use the
800 registers 'after' the end */
801 if (index < 8 && env->cwp == env->nwindows - 1)
802 index += 16 * env->nwindows;
803 return index;
804 }
805
806 /* save the register window 'cwp1' */
807 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
808 {
809 unsigned int i;
810 abi_ulong sp_ptr;
811
812 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
813 #ifdef TARGET_SPARC64
814 if (sp_ptr & 3)
815 sp_ptr += SPARC64_STACK_BIAS;
816 #endif
817 #if defined(DEBUG_WIN)
818 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
819 sp_ptr, cwp1);
820 #endif
821 for(i = 0; i < 16; i++) {
822 /* FIXME - what to do if put_user() fails? */
823 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
824 sp_ptr += sizeof(abi_ulong);
825 }
826 }
827
828 static void save_window(CPUSPARCState *env)
829 {
830 #ifndef TARGET_SPARC64
831 unsigned int new_wim;
832 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
833 ((1LL << env->nwindows) - 1);
834 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
835 env->wim = new_wim;
836 #else
837 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
838 env->cansave++;
839 env->canrestore--;
840 #endif
841 }
842
843 static void restore_window(CPUSPARCState *env)
844 {
845 #ifndef TARGET_SPARC64
846 unsigned int new_wim;
847 #endif
848 unsigned int i, cwp1;
849 abi_ulong sp_ptr;
850
851 #ifndef TARGET_SPARC64
852 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
853 ((1LL << env->nwindows) - 1);
854 #endif
855
856 /* restore the invalid window */
857 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
858 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
859 #ifdef TARGET_SPARC64
860 if (sp_ptr & 3)
861 sp_ptr += SPARC64_STACK_BIAS;
862 #endif
863 #if defined(DEBUG_WIN)
864 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
865 sp_ptr, cwp1);
866 #endif
867 for(i = 0; i < 16; i++) {
868 /* FIXME - what to do if get_user() fails? */
869 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
870 sp_ptr += sizeof(abi_ulong);
871 }
872 #ifdef TARGET_SPARC64
873 env->canrestore++;
874 if (env->cleanwin < env->nwindows - 1)
875 env->cleanwin++;
876 env->cansave--;
877 #else
878 env->wim = new_wim;
879 #endif
880 }
881
882 static void flush_windows(CPUSPARCState *env)
883 {
884 int offset, cwp1;
885
886 offset = 1;
887 for(;;) {
888 /* if restore would invoke restore_window(), then we can stop */
889 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
890 #ifndef TARGET_SPARC64
891 if (env->wim & (1 << cwp1))
892 break;
893 #else
894 if (env->canrestore == 0)
895 break;
896 env->cansave++;
897 env->canrestore--;
898 #endif
899 save_window_offset(env, cwp1);
900 offset++;
901 }
902 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
903 #ifndef TARGET_SPARC64
904 /* set wim so that restore will reload the registers */
905 env->wim = 1 << cwp1;
906 #endif
907 #if defined(DEBUG_WIN)
908 printf("flush_windows: nb=%d\n", offset - 1);
909 #endif
910 }
911
912 void cpu_loop (CPUSPARCState *env)
913 {
914 int trapnr, ret;
915 target_siginfo_t info;
916
917 while (1) {
918 trapnr = cpu_sparc_exec (env);
919
920 switch (trapnr) {
921 #ifndef TARGET_SPARC64
922 case 0x88:
923 case 0x90:
924 #else
925 case 0x110:
926 case 0x16d:
927 #endif
928 ret = do_syscall (env, env->gregs[1],
929 env->regwptr[0], env->regwptr[1],
930 env->regwptr[2], env->regwptr[3],
931 env->regwptr[4], env->regwptr[5]);
932 if ((unsigned int)ret >= (unsigned int)(-515)) {
933 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
934 env->xcc |= PSR_CARRY;
935 #else
936 env->psr |= PSR_CARRY;
937 #endif
938 ret = -ret;
939 } else {
940 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
941 env->xcc &= ~PSR_CARRY;
942 #else
943 env->psr &= ~PSR_CARRY;
944 #endif
945 }
946 env->regwptr[0] = ret;
947 /* next instruction */
948 env->pc = env->npc;
949 env->npc = env->npc + 4;
950 break;
951 case 0x83: /* flush windows */
952 #ifdef TARGET_ABI32
953 case 0x103:
954 #endif
955 flush_windows(env);
956 /* next instruction */
957 env->pc = env->npc;
958 env->npc = env->npc + 4;
959 break;
960 #ifndef TARGET_SPARC64
961 case TT_WIN_OVF: /* window overflow */
962 save_window(env);
963 break;
964 case TT_WIN_UNF: /* window underflow */
965 restore_window(env);
966 break;
967 case TT_TFAULT:
968 case TT_DFAULT:
969 {
970 info.si_signo = SIGSEGV;
971 info.si_errno = 0;
972 /* XXX: check env->error_code */
973 info.si_code = TARGET_SEGV_MAPERR;
974 info._sifields._sigfault._addr = env->mmuregs[4];
975 queue_signal(env, info.si_signo, &info);
976 }
977 break;
978 #else
979 case TT_SPILL: /* window overflow */
980 save_window(env);
981 break;
982 case TT_FILL: /* window underflow */
983 restore_window(env);
984 break;
985 case TT_TFAULT:
986 case TT_DFAULT:
987 {
988 info.si_signo = SIGSEGV;
989 info.si_errno = 0;
990 /* XXX: check env->error_code */
991 info.si_code = TARGET_SEGV_MAPERR;
992 if (trapnr == TT_DFAULT)
993 info._sifields._sigfault._addr = env->dmmuregs[4];
994 else
995 info._sifields._sigfault._addr = env->tsptr->tpc;
996 queue_signal(env, info.si_signo, &info);
997 }
998 break;
999 #ifndef TARGET_ABI32
1000 case 0x16e:
1001 flush_windows(env);
1002 sparc64_get_context(env);
1003 break;
1004 case 0x16f:
1005 flush_windows(env);
1006 sparc64_set_context(env);
1007 break;
1008 #endif
1009 #endif
1010 case EXCP_INTERRUPT:
1011 /* just indicate that signals should be handled asap */
1012 break;
1013 case EXCP_DEBUG:
1014 {
1015 int sig;
1016
1017 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1018 if (sig)
1019 {
1020 info.si_signo = sig;
1021 info.si_errno = 0;
1022 info.si_code = TARGET_TRAP_BRKPT;
1023 queue_signal(env, info.si_signo, &info);
1024 }
1025 }
1026 break;
1027 default:
1028 printf ("Unhandled trap: 0x%x\n", trapnr);
1029 cpu_dump_state(env, stderr, fprintf, 0);
1030 exit (1);
1031 }
1032 process_pending_signals (env);
1033 }
1034 }
1035
1036 #endif
1037
1038 #ifdef TARGET_PPC
1039 static inline uint64_t cpu_ppc_get_tb (CPUState *env)
1040 {
1041 /* TO FIX */
1042 return 0;
1043 }
1044
1045 uint32_t cpu_ppc_load_tbl (CPUState *env)
1046 {
1047 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1048 }
1049
1050 uint32_t cpu_ppc_load_tbu (CPUState *env)
1051 {
1052 return cpu_ppc_get_tb(env) >> 32;
1053 }
1054
1055 uint32_t cpu_ppc_load_atbl (CPUState *env)
1056 {
1057 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1058 }
1059
1060 uint32_t cpu_ppc_load_atbu (CPUState *env)
1061 {
1062 return cpu_ppc_get_tb(env) >> 32;
1063 }
1064
1065 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
1066 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1067
1068 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
1069 {
1070 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1071 }
1072
1073 /* XXX: to be fixed */
1074 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
1075 {
1076 return -1;
1077 }
1078
1079 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
1080 {
1081 return -1;
1082 }
1083
1084 #define EXCP_DUMP(env, fmt, ...) \
1085 do { \
1086 fprintf(stderr, fmt , ## __VA_ARGS__); \
1087 cpu_dump_state(env, stderr, fprintf, 0); \
1088 qemu_log(fmt, ## __VA_ARGS__); \
1089 log_cpu_state(env, 0); \
1090 } while (0)
1091
1092 void cpu_loop(CPUPPCState *env)
1093 {
1094 target_siginfo_t info;
1095 int trapnr;
1096 uint32_t ret;
1097
1098 for(;;) {
1099 trapnr = cpu_ppc_exec(env);
1100 switch(trapnr) {
1101 case POWERPC_EXCP_NONE:
1102 /* Just go on */
1103 break;
1104 case POWERPC_EXCP_CRITICAL: /* Critical input */
1105 cpu_abort(env, "Critical interrupt while in user mode. "
1106 "Aborting\n");
1107 break;
1108 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1109 cpu_abort(env, "Machine check exception while in user mode. "
1110 "Aborting\n");
1111 break;
1112 case POWERPC_EXCP_DSI: /* Data storage exception */
1113 EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n",
1114 env->spr[SPR_DAR]);
1115 /* XXX: check this. Seems bugged */
1116 switch (env->error_code & 0xFF000000) {
1117 case 0x40000000:
1118 info.si_signo = TARGET_SIGSEGV;
1119 info.si_errno = 0;
1120 info.si_code = TARGET_SEGV_MAPERR;
1121 break;
1122 case 0x04000000:
1123 info.si_signo = TARGET_SIGILL;
1124 info.si_errno = 0;
1125 info.si_code = TARGET_ILL_ILLADR;
1126 break;
1127 case 0x08000000:
1128 info.si_signo = TARGET_SIGSEGV;
1129 info.si_errno = 0;
1130 info.si_code = TARGET_SEGV_ACCERR;
1131 break;
1132 default:
1133 /* Let's send a regular segfault... */
1134 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1135 env->error_code);
1136 info.si_signo = TARGET_SIGSEGV;
1137 info.si_errno = 0;
1138 info.si_code = TARGET_SEGV_MAPERR;
1139 break;
1140 }
1141 info._sifields._sigfault._addr = env->nip;
1142 queue_signal(env, info.si_signo, &info);
1143 break;
1144 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1145 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n",
1146 env->spr[SPR_SRR0]);
1147 /* XXX: check this */
1148 switch (env->error_code & 0xFF000000) {
1149 case 0x40000000:
1150 info.si_signo = TARGET_SIGSEGV;
1151 info.si_errno = 0;
1152 info.si_code = TARGET_SEGV_MAPERR;
1153 break;
1154 case 0x10000000:
1155 case 0x08000000:
1156 info.si_signo = TARGET_SIGSEGV;
1157 info.si_errno = 0;
1158 info.si_code = TARGET_SEGV_ACCERR;
1159 break;
1160 default:
1161 /* Let's send a regular segfault... */
1162 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1163 env->error_code);
1164 info.si_signo = TARGET_SIGSEGV;
1165 info.si_errno = 0;
1166 info.si_code = TARGET_SEGV_MAPERR;
1167 break;
1168 }
1169 info._sifields._sigfault._addr = env->nip - 4;
1170 queue_signal(env, info.si_signo, &info);
1171 break;
1172 case POWERPC_EXCP_EXTERNAL: /* External input */
1173 cpu_abort(env, "External interrupt while in user mode. "
1174 "Aborting\n");
1175 break;
1176 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1177 EXCP_DUMP(env, "Unaligned memory access\n");
1178 /* XXX: check this */
1179 info.si_signo = TARGET_SIGBUS;
1180 info.si_errno = 0;
1181 info.si_code = TARGET_BUS_ADRALN;
1182 info._sifields._sigfault._addr = env->nip - 4;
1183 queue_signal(env, info.si_signo, &info);
1184 break;
1185 case POWERPC_EXCP_PROGRAM: /* Program exception */
1186 /* XXX: check this */
1187 switch (env->error_code & ~0xF) {
1188 case POWERPC_EXCP_FP:
1189 EXCP_DUMP(env, "Floating point program exception\n");
1190 info.si_signo = TARGET_SIGFPE;
1191 info.si_errno = 0;
1192 switch (env->error_code & 0xF) {
1193 case POWERPC_EXCP_FP_OX:
1194 info.si_code = TARGET_FPE_FLTOVF;
1195 break;
1196 case POWERPC_EXCP_FP_UX:
1197 info.si_code = TARGET_FPE_FLTUND;
1198 break;
1199 case POWERPC_EXCP_FP_ZX:
1200 case POWERPC_EXCP_FP_VXZDZ:
1201 info.si_code = TARGET_FPE_FLTDIV;
1202 break;
1203 case POWERPC_EXCP_FP_XX:
1204 info.si_code = TARGET_FPE_FLTRES;
1205 break;
1206 case POWERPC_EXCP_FP_VXSOFT:
1207 info.si_code = TARGET_FPE_FLTINV;
1208 break;
1209 case POWERPC_EXCP_FP_VXSNAN:
1210 case POWERPC_EXCP_FP_VXISI:
1211 case POWERPC_EXCP_FP_VXIDI:
1212 case POWERPC_EXCP_FP_VXIMZ:
1213 case POWERPC_EXCP_FP_VXVC:
1214 case POWERPC_EXCP_FP_VXSQRT:
1215 case POWERPC_EXCP_FP_VXCVI:
1216 info.si_code = TARGET_FPE_FLTSUB;
1217 break;
1218 default:
1219 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1220 env->error_code);
1221 break;
1222 }
1223 break;
1224 case POWERPC_EXCP_INVAL:
1225 EXCP_DUMP(env, "Invalid instruction\n");
1226 info.si_signo = TARGET_SIGILL;
1227 info.si_errno = 0;
1228 switch (env->error_code & 0xF) {
1229 case POWERPC_EXCP_INVAL_INVAL:
1230 info.si_code = TARGET_ILL_ILLOPC;
1231 break;
1232 case POWERPC_EXCP_INVAL_LSWX:
1233 info.si_code = TARGET_ILL_ILLOPN;
1234 break;
1235 case POWERPC_EXCP_INVAL_SPR:
1236 info.si_code = TARGET_ILL_PRVREG;
1237 break;
1238 case POWERPC_EXCP_INVAL_FP:
1239 info.si_code = TARGET_ILL_COPROC;
1240 break;
1241 default:
1242 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1243 env->error_code & 0xF);
1244 info.si_code = TARGET_ILL_ILLADR;
1245 break;
1246 }
1247 break;
1248 case POWERPC_EXCP_PRIV:
1249 EXCP_DUMP(env, "Privilege violation\n");
1250 info.si_signo = TARGET_SIGILL;
1251 info.si_errno = 0;
1252 switch (env->error_code & 0xF) {
1253 case POWERPC_EXCP_PRIV_OPC:
1254 info.si_code = TARGET_ILL_PRVOPC;
1255 break;
1256 case POWERPC_EXCP_PRIV_REG:
1257 info.si_code = TARGET_ILL_PRVREG;
1258 break;
1259 default:
1260 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1261 env->error_code & 0xF);
1262 info.si_code = TARGET_ILL_PRVOPC;
1263 break;
1264 }
1265 break;
1266 case POWERPC_EXCP_TRAP:
1267 cpu_abort(env, "Tried to call a TRAP\n");
1268 break;
1269 default:
1270 /* Should not happen ! */
1271 cpu_abort(env, "Unknown program exception (%02x)\n",
1272 env->error_code);
1273 break;
1274 }
1275 info._sifields._sigfault._addr = env->nip - 4;
1276 queue_signal(env, info.si_signo, &info);
1277 break;
1278 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1279 EXCP_DUMP(env, "No floating point allowed\n");
1280 info.si_signo = TARGET_SIGILL;
1281 info.si_errno = 0;
1282 info.si_code = TARGET_ILL_COPROC;
1283 info._sifields._sigfault._addr = env->nip - 4;
1284 queue_signal(env, info.si_signo, &info);
1285 break;
1286 case POWERPC_EXCP_SYSCALL: /* System call exception */
1287 cpu_abort(env, "Syscall exception while in user mode. "
1288 "Aborting\n");
1289 break;
1290 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1291 EXCP_DUMP(env, "No APU instruction allowed\n");
1292 info.si_signo = TARGET_SIGILL;
1293 info.si_errno = 0;
1294 info.si_code = TARGET_ILL_COPROC;
1295 info._sifields._sigfault._addr = env->nip - 4;
1296 queue_signal(env, info.si_signo, &info);
1297 break;
1298 case POWERPC_EXCP_DECR: /* Decrementer exception */
1299 cpu_abort(env, "Decrementer interrupt while in user mode. "
1300 "Aborting\n");
1301 break;
1302 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1303 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1304 "Aborting\n");
1305 break;
1306 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1307 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1308 "Aborting\n");
1309 break;
1310 case POWERPC_EXCP_DTLB: /* Data TLB error */
1311 cpu_abort(env, "Data TLB exception while in user mode. "
1312 "Aborting\n");
1313 break;
1314 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1315 cpu_abort(env, "Instruction TLB exception while in user mode. "
1316 "Aborting\n");
1317 break;
1318 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1319 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1320 info.si_signo = TARGET_SIGILL;
1321 info.si_errno = 0;
1322 info.si_code = TARGET_ILL_COPROC;
1323 info._sifields._sigfault._addr = env->nip - 4;
1324 queue_signal(env, info.si_signo, &info);
1325 break;
1326 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1327 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1328 break;
1329 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1330 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1331 break;
1332 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1333 cpu_abort(env, "Performance monitor exception not handled\n");
1334 break;
1335 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1336 cpu_abort(env, "Doorbell interrupt while in user mode. "
1337 "Aborting\n");
1338 break;
1339 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1340 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1341 "Aborting\n");
1342 break;
1343 case POWERPC_EXCP_RESET: /* System reset exception */
1344 cpu_abort(env, "Reset interrupt while in user mode. "
1345 "Aborting\n");
1346 break;
1347 case POWERPC_EXCP_DSEG: /* Data segment exception */
1348 cpu_abort(env, "Data segment exception while in user mode. "
1349 "Aborting\n");
1350 break;
1351 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1352 cpu_abort(env, "Instruction segment exception "
1353 "while in user mode. Aborting\n");
1354 break;
1355 /* PowerPC 64 with hypervisor mode support */
1356 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1357 cpu_abort(env, "Hypervisor decrementer interrupt "
1358 "while in user mode. Aborting\n");
1359 break;
1360 case POWERPC_EXCP_TRACE: /* Trace exception */
1361 /* Nothing to do:
1362 * we use this exception to emulate step-by-step execution mode.
1363 */
1364 break;
1365 /* PowerPC 64 with hypervisor mode support */
1366 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1367 cpu_abort(env, "Hypervisor data storage exception "
1368 "while in user mode. Aborting\n");
1369 break;
1370 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1371 cpu_abort(env, "Hypervisor instruction storage exception "
1372 "while in user mode. Aborting\n");
1373 break;
1374 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1375 cpu_abort(env, "Hypervisor data segment exception "
1376 "while in user mode. Aborting\n");
1377 break;
1378 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1379 cpu_abort(env, "Hypervisor instruction segment exception "
1380 "while in user mode. Aborting\n");
1381 break;
1382 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1383 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1384 info.si_signo = TARGET_SIGILL;
1385 info.si_errno = 0;
1386 info.si_code = TARGET_ILL_COPROC;
1387 info._sifields._sigfault._addr = env->nip - 4;
1388 queue_signal(env, info.si_signo, &info);
1389 break;
1390 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1391 cpu_abort(env, "Programable interval timer interrupt "
1392 "while in user mode. Aborting\n");
1393 break;
1394 case POWERPC_EXCP_IO: /* IO error exception */
1395 cpu_abort(env, "IO error exception while in user mode. "
1396 "Aborting\n");
1397 break;
1398 case POWERPC_EXCP_RUNM: /* Run mode exception */
1399 cpu_abort(env, "Run mode exception while in user mode. "
1400 "Aborting\n");
1401 break;
1402 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1403 cpu_abort(env, "Emulation trap exception not handled\n");
1404 break;
1405 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1406 cpu_abort(env, "Instruction fetch TLB exception "
1407 "while in user-mode. Aborting");
1408 break;
1409 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1410 cpu_abort(env, "Data load TLB exception while in user-mode. "
1411 "Aborting");
1412 break;
1413 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1414 cpu_abort(env, "Data store TLB exception while in user-mode. "
1415 "Aborting");
1416 break;
1417 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1418 cpu_abort(env, "Floating-point assist exception not handled\n");
1419 break;
1420 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1421 cpu_abort(env, "Instruction address breakpoint exception "
1422 "not handled\n");
1423 break;
1424 case POWERPC_EXCP_SMI: /* System management interrupt */
1425 cpu_abort(env, "System management interrupt while in user mode. "
1426 "Aborting\n");
1427 break;
1428 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1429 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1430 "Aborting\n");
1431 break;
1432 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1433 cpu_abort(env, "Performance monitor exception not handled\n");
1434 break;
1435 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1436 cpu_abort(env, "Vector assist exception not handled\n");
1437 break;
1438 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1439 cpu_abort(env, "Soft patch exception not handled\n");
1440 break;
1441 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1442 cpu_abort(env, "Maintenance exception while in user mode. "
1443 "Aborting\n");
1444 break;
1445 case POWERPC_EXCP_STOP: /* stop translation */
1446 /* We did invalidate the instruction cache. Go on */
1447 break;
1448 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1449 /* We just stopped because of a branch. Go on */
1450 break;
1451 case POWERPC_EXCP_SYSCALL_USER:
1452 /* system call in user-mode emulation */
1453 /* WARNING:
1454 * PPC ABI uses overflow flag in cr0 to signal an error
1455 * in syscalls.
1456 */
1457 #if 0
1458 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
1459 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
1460 #endif
1461 env->crf[0] &= ~0x1;
1462 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1463 env->gpr[5], env->gpr[6], env->gpr[7],
1464 env->gpr[8]);
1465 if (ret == (uint32_t)(-TARGET_QEMU_ESIGRETURN)) {
1466 /* Returning from a successful sigreturn syscall.
1467 Avoid corrupting register state. */
1468 break;
1469 }
1470 if (ret > (uint32_t)(-515)) {
1471 env->crf[0] |= 0x1;
1472 ret = -ret;
1473 }
1474 env->gpr[3] = ret;
1475 #if 0
1476 printf("syscall returned 0x%08x (%d)\n", ret, ret);
1477 #endif
1478 break;
1479 case EXCP_DEBUG:
1480 {
1481 int sig;
1482
1483 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1484 if (sig) {
1485 info.si_signo = sig;
1486 info.si_errno = 0;
1487 info.si_code = TARGET_TRAP_BRKPT;
1488 queue_signal(env, info.si_signo, &info);
1489 }
1490 }
1491 break;
1492 case EXCP_INTERRUPT:
1493 /* just indicate that signals should be handled asap */
1494 break;
1495 default:
1496 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1497 break;
1498 }
1499 process_pending_signals(env);
1500 }
1501 }
1502 #endif
1503
1504 #ifdef TARGET_MIPS
1505
1506 #define MIPS_SYS(name, args) args,
1507
1508 static const uint8_t mips_syscall_args[] = {
1509 MIPS_SYS(sys_syscall , 0) /* 4000 */
1510 MIPS_SYS(sys_exit , 1)
1511 MIPS_SYS(sys_fork , 0)
1512 MIPS_SYS(sys_read , 3)
1513 MIPS_SYS(sys_write , 3)
1514 MIPS_SYS(sys_open , 3) /* 4005 */
1515 MIPS_SYS(sys_close , 1)
1516 MIPS_SYS(sys_waitpid , 3)
1517 MIPS_SYS(sys_creat , 2)
1518 MIPS_SYS(sys_link , 2)
1519 MIPS_SYS(sys_unlink , 1) /* 4010 */
1520 MIPS_SYS(sys_execve , 0)
1521 MIPS_SYS(sys_chdir , 1)
1522 MIPS_SYS(sys_time , 1)
1523 MIPS_SYS(sys_mknod , 3)
1524 MIPS_SYS(sys_chmod , 2) /* 4015 */
1525 MIPS_SYS(sys_lchown , 3)
1526 MIPS_SYS(sys_ni_syscall , 0)
1527 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1528 MIPS_SYS(sys_lseek , 3)
1529 MIPS_SYS(sys_getpid , 0) /* 4020 */
1530 MIPS_SYS(sys_mount , 5)
1531 MIPS_SYS(sys_oldumount , 1)
1532 MIPS_SYS(sys_setuid , 1)
1533 MIPS_SYS(sys_getuid , 0)
1534 MIPS_SYS(sys_stime , 1) /* 4025 */
1535 MIPS_SYS(sys_ptrace , 4)
1536 MIPS_SYS(sys_alarm , 1)
1537 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1538 MIPS_SYS(sys_pause , 0)
1539 MIPS_SYS(sys_utime , 2) /* 4030 */
1540 MIPS_SYS(sys_ni_syscall , 0)
1541 MIPS_SYS(sys_ni_syscall , 0)
1542 MIPS_SYS(sys_access , 2)
1543 MIPS_SYS(sys_nice , 1)
1544 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1545 MIPS_SYS(sys_sync , 0)
1546 MIPS_SYS(sys_kill , 2)
1547 MIPS_SYS(sys_rename , 2)
1548 MIPS_SYS(sys_mkdir , 2)
1549 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1550 MIPS_SYS(sys_dup , 1)
1551 MIPS_SYS(sys_pipe , 0)
1552 MIPS_SYS(sys_times , 1)
1553 MIPS_SYS(sys_ni_syscall , 0)
1554 MIPS_SYS(sys_brk , 1) /* 4045 */
1555 MIPS_SYS(sys_setgid , 1)
1556 MIPS_SYS(sys_getgid , 0)
1557 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1558 MIPS_SYS(sys_geteuid , 0)
1559 MIPS_SYS(sys_getegid , 0) /* 4050 */
1560 MIPS_SYS(sys_acct , 0)
1561 MIPS_SYS(sys_umount , 2)
1562 MIPS_SYS(sys_ni_syscall , 0)
1563 MIPS_SYS(sys_ioctl , 3)
1564 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1565 MIPS_SYS(sys_ni_syscall , 2)
1566 MIPS_SYS(sys_setpgid , 2)
1567 MIPS_SYS(sys_ni_syscall , 0)
1568 MIPS_SYS(sys_olduname , 1)
1569 MIPS_SYS(sys_umask , 1) /* 4060 */
1570 MIPS_SYS(sys_chroot , 1)
1571 MIPS_SYS(sys_ustat , 2)
1572 MIPS_SYS(sys_dup2 , 2)
1573 MIPS_SYS(sys_getppid , 0)
1574 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1575 MIPS_SYS(sys_setsid , 0)
1576 MIPS_SYS(sys_sigaction , 3)
1577 MIPS_SYS(sys_sgetmask , 0)
1578 MIPS_SYS(sys_ssetmask , 1)
1579 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1580 MIPS_SYS(sys_setregid , 2)
1581 MIPS_SYS(sys_sigsuspend , 0)
1582 MIPS_SYS(sys_sigpending , 1)
1583 MIPS_SYS(sys_sethostname , 2)
1584 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1585 MIPS_SYS(sys_getrlimit , 2)
1586 MIPS_SYS(sys_getrusage , 2)
1587 MIPS_SYS(sys_gettimeofday, 2)
1588 MIPS_SYS(sys_settimeofday, 2)
1589 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1590 MIPS_SYS(sys_setgroups , 2)
1591 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1592 MIPS_SYS(sys_symlink , 2)
1593 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1594 MIPS_SYS(sys_readlink , 3) /* 4085 */
1595 MIPS_SYS(sys_uselib , 1)
1596 MIPS_SYS(sys_swapon , 2)
1597 MIPS_SYS(sys_reboot , 3)
1598 MIPS_SYS(old_readdir , 3)
1599 MIPS_SYS(old_mmap , 6) /* 4090 */
1600 MIPS_SYS(sys_munmap , 2)
1601 MIPS_SYS(sys_truncate , 2)
1602 MIPS_SYS(sys_ftruncate , 2)
1603 MIPS_SYS(sys_fchmod , 2)
1604 MIPS_SYS(sys_fchown , 3) /* 4095 */
1605 MIPS_SYS(sys_getpriority , 2)
1606 MIPS_SYS(sys_setpriority , 3)
1607 MIPS_SYS(sys_ni_syscall , 0)
1608 MIPS_SYS(sys_statfs , 2)
1609 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1610 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1611 MIPS_SYS(sys_socketcall , 2)
1612 MIPS_SYS(sys_syslog , 3)
1613 MIPS_SYS(sys_setitimer , 3)
1614 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1615 MIPS_SYS(sys_newstat , 2)
1616 MIPS_SYS(sys_newlstat , 2)
1617 MIPS_SYS(sys_newfstat , 2)
1618 MIPS_SYS(sys_uname , 1)
1619 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1620 MIPS_SYS(sys_vhangup , 0)
1621 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1622 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1623 MIPS_SYS(sys_wait4 , 4)
1624 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1625 MIPS_SYS(sys_sysinfo , 1)
1626 MIPS_SYS(sys_ipc , 6)
1627 MIPS_SYS(sys_fsync , 1)
1628 MIPS_SYS(sys_sigreturn , 0)
1629 MIPS_SYS(sys_clone , 6) /* 4120 */
1630 MIPS_SYS(sys_setdomainname, 2)
1631 MIPS_SYS(sys_newuname , 1)
1632 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1633 MIPS_SYS(sys_adjtimex , 1)
1634 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1635 MIPS_SYS(sys_sigprocmask , 3)
1636 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1637 MIPS_SYS(sys_init_module , 5)
1638 MIPS_SYS(sys_delete_module, 1)
1639 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1640 MIPS_SYS(sys_quotactl , 0)
1641 MIPS_SYS(sys_getpgid , 1)
1642 MIPS_SYS(sys_fchdir , 1)
1643 MIPS_SYS(sys_bdflush , 2)
1644 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1645 MIPS_SYS(sys_personality , 1)
1646 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1647 MIPS_SYS(sys_setfsuid , 1)
1648 MIPS_SYS(sys_setfsgid , 1)
1649 MIPS_SYS(sys_llseek , 5) /* 4140 */
1650 MIPS_SYS(sys_getdents , 3)
1651 MIPS_SYS(sys_select , 5)
1652 MIPS_SYS(sys_flock , 2)
1653 MIPS_SYS(sys_msync , 3)
1654 MIPS_SYS(sys_readv , 3) /* 4145 */
1655 MIPS_SYS(sys_writev , 3)
1656 MIPS_SYS(sys_cacheflush , 3)
1657 MIPS_SYS(sys_cachectl , 3)
1658 MIPS_SYS(sys_sysmips , 4)
1659 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1660 MIPS_SYS(sys_getsid , 1)
1661 MIPS_SYS(sys_fdatasync , 0)
1662 MIPS_SYS(sys_sysctl , 1)
1663 MIPS_SYS(sys_mlock , 2)
1664 MIPS_SYS(sys_munlock , 2) /* 4155 */
1665 MIPS_SYS(sys_mlockall , 1)
1666 MIPS_SYS(sys_munlockall , 0)
1667 MIPS_SYS(sys_sched_setparam, 2)
1668 MIPS_SYS(sys_sched_getparam, 2)
1669 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1670 MIPS_SYS(sys_sched_getscheduler, 1)
1671 MIPS_SYS(sys_sched_yield , 0)
1672 MIPS_SYS(sys_sched_get_priority_max, 1)
1673 MIPS_SYS(sys_sched_get_priority_min, 1)
1674 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1675 MIPS_SYS(sys_nanosleep, 2)
1676 MIPS_SYS(sys_mremap , 4)
1677 MIPS_SYS(sys_accept , 3)
1678 MIPS_SYS(sys_bind , 3)
1679 MIPS_SYS(sys_connect , 3) /* 4170 */
1680 MIPS_SYS(sys_getpeername , 3)
1681 MIPS_SYS(sys_getsockname , 3)
1682 MIPS_SYS(sys_getsockopt , 5)
1683 MIPS_SYS(sys_listen , 2)
1684 MIPS_SYS(sys_recv , 4) /* 4175 */
1685 MIPS_SYS(sys_recvfrom , 6)
1686 MIPS_SYS(sys_recvmsg , 3)
1687 MIPS_SYS(sys_send , 4)
1688 MIPS_SYS(sys_sendmsg , 3)
1689 MIPS_SYS(sys_sendto , 6) /* 4180 */
1690 MIPS_SYS(sys_setsockopt , 5)
1691 MIPS_SYS(sys_shutdown , 2)
1692 MIPS_SYS(sys_socket , 3)
1693 MIPS_SYS(sys_socketpair , 4)
1694 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1695 MIPS_SYS(sys_getresuid , 3)
1696 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1697 MIPS_SYS(sys_poll , 3)
1698 MIPS_SYS(sys_nfsservctl , 3)
1699 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1700 MIPS_SYS(sys_getresgid , 3)
1701 MIPS_SYS(sys_prctl , 5)
1702 MIPS_SYS(sys_rt_sigreturn, 0)
1703 MIPS_SYS(sys_rt_sigaction, 4)
1704 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1705 MIPS_SYS(sys_rt_sigpending, 2)
1706 MIPS_SYS(sys_rt_sigtimedwait, 4)
1707 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1708 MIPS_SYS(sys_rt_sigsuspend, 0)
1709 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1710 MIPS_SYS(sys_pwrite64 , 6)
1711 MIPS_SYS(sys_chown , 3)
1712 MIPS_SYS(sys_getcwd , 2)
1713 MIPS_SYS(sys_capget , 2)
1714 MIPS_SYS(sys_capset , 2) /* 4205 */
1715 MIPS_SYS(sys_sigaltstack , 0)
1716 MIPS_SYS(sys_sendfile , 4)
1717 MIPS_SYS(sys_ni_syscall , 0)
1718 MIPS_SYS(sys_ni_syscall , 0)
1719 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1720 MIPS_SYS(sys_truncate64 , 4)
1721 MIPS_SYS(sys_ftruncate64 , 4)
1722 MIPS_SYS(sys_stat64 , 2)
1723 MIPS_SYS(sys_lstat64 , 2)
1724 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1725 MIPS_SYS(sys_pivot_root , 2)
1726 MIPS_SYS(sys_mincore , 3)
1727 MIPS_SYS(sys_madvise , 3)
1728 MIPS_SYS(sys_getdents64 , 3)
1729 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1730 MIPS_SYS(sys_ni_syscall , 0)
1731 MIPS_SYS(sys_gettid , 0)
1732 MIPS_SYS(sys_readahead , 5)
1733 MIPS_SYS(sys_setxattr , 5)
1734 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1735 MIPS_SYS(sys_fsetxattr , 5)
1736 MIPS_SYS(sys_getxattr , 4)
1737 MIPS_SYS(sys_lgetxattr , 4)
1738 MIPS_SYS(sys_fgetxattr , 4)
1739 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1740 MIPS_SYS(sys_llistxattr , 3)
1741 MIPS_SYS(sys_flistxattr , 3)
1742 MIPS_SYS(sys_removexattr , 2)
1743 MIPS_SYS(sys_lremovexattr, 2)
1744 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1745 MIPS_SYS(sys_tkill , 2)
1746 MIPS_SYS(sys_sendfile64 , 5)
1747 MIPS_SYS(sys_futex , 2)
1748 MIPS_SYS(sys_sched_setaffinity, 3)
1749 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1750 MIPS_SYS(sys_io_setup , 2)
1751 MIPS_SYS(sys_io_destroy , 1)
1752 MIPS_SYS(sys_io_getevents, 5)
1753 MIPS_SYS(sys_io_submit , 3)
1754 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
1755 MIPS_SYS(sys_exit_group , 1)
1756 MIPS_SYS(sys_lookup_dcookie, 3)
1757 MIPS_SYS(sys_epoll_create, 1)
1758 MIPS_SYS(sys_epoll_ctl , 4)
1759 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
1760 MIPS_SYS(sys_remap_file_pages, 5)
1761 MIPS_SYS(sys_set_tid_address, 1)
1762 MIPS_SYS(sys_restart_syscall, 0)
1763 MIPS_SYS(sys_fadvise64_64, 7)
1764 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
1765 MIPS_SYS(sys_fstatfs64 , 2)
1766 MIPS_SYS(sys_timer_create, 3)
1767 MIPS_SYS(sys_timer_settime, 4)
1768 MIPS_SYS(sys_timer_gettime, 2)
1769 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
1770 MIPS_SYS(sys_timer_delete, 1)
1771 MIPS_SYS(sys_clock_settime, 2)
1772 MIPS_SYS(sys_clock_gettime, 2)
1773 MIPS_SYS(sys_clock_getres, 2)
1774 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
1775 MIPS_SYS(sys_tgkill , 3)
1776 MIPS_SYS(sys_utimes , 2)
1777 MIPS_SYS(sys_mbind , 4)
1778 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
1779 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
1780 MIPS_SYS(sys_mq_open , 4)
1781 MIPS_SYS(sys_mq_unlink , 1)
1782 MIPS_SYS(sys_mq_timedsend, 5)
1783 MIPS_SYS(sys_mq_timedreceive, 5)
1784 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
1785 MIPS_SYS(sys_mq_getsetattr, 3)
1786 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
1787 MIPS_SYS(sys_waitid , 4)
1788 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
1789 MIPS_SYS(sys_add_key , 5)
1790 MIPS_SYS(sys_request_key, 4)
1791 MIPS_SYS(sys_keyctl , 5)
1792 MIPS_SYS(sys_set_thread_area, 1)
1793 MIPS_SYS(sys_inotify_init, 0)
1794 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
1795 MIPS_SYS(sys_inotify_rm_watch, 2)
1796 MIPS_SYS(sys_migrate_pages, 4)
1797 MIPS_SYS(sys_openat, 4)
1798 MIPS_SYS(sys_mkdirat, 3)
1799 MIPS_SYS(sys_mknodat, 4) /* 4290 */
1800 MIPS_SYS(sys_fchownat, 5)
1801 MIPS_SYS(sys_futimesat, 3)
1802 MIPS_SYS(sys_fstatat64, 4)
1803 MIPS_SYS(sys_unlinkat, 3)
1804 MIPS_SYS(sys_renameat, 4) /* 4295 */
1805 MIPS_SYS(sys_linkat, 5)
1806 MIPS_SYS(sys_symlinkat, 3)
1807 MIPS_SYS(sys_readlinkat, 4)
1808 MIPS_SYS(sys_fchmodat, 3)
1809 MIPS_SYS(sys_faccessat, 3) /* 4300 */
1810 MIPS_SYS(sys_pselect6, 6)
1811 MIPS_SYS(sys_ppoll, 5)
1812 MIPS_SYS(sys_unshare, 1)
1813 MIPS_SYS(sys_splice, 4)
1814 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
1815 MIPS_SYS(sys_tee, 4)
1816 MIPS_SYS(sys_vmsplice, 4)
1817 MIPS_SYS(sys_move_pages, 6)
1818 MIPS_SYS(sys_set_robust_list, 2)
1819 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
1820 MIPS_SYS(sys_kexec_load, 4)
1821 MIPS_SYS(sys_getcpu, 3)
1822 MIPS_SYS(sys_epoll_pwait, 6)
1823 MIPS_SYS(sys_ioprio_set, 3)
1824 MIPS_SYS(sys_ioprio_get, 2)
1825 };
1826
1827 #undef MIPS_SYS
1828
1829 static int do_store_exclusive(CPUMIPSState *env)
1830 {
1831 target_ulong addr;
1832 target_ulong page_addr;
1833 target_ulong val;
1834 int flags;
1835 int segv = 0;
1836 int reg;
1837 int d;
1838
1839 addr = env->CP0_LLAddr;
1840 page_addr = addr & TARGET_PAGE_MASK;
1841 start_exclusive();
1842 mmap_lock();
1843 flags = page_get_flags(page_addr);
1844 if ((flags & PAGE_READ) == 0) {
1845 segv = 1;
1846 } else {
1847 reg = env->llreg & 0x1f;
1848 d = (env->llreg & 0x20) != 0;
1849 if (d) {
1850 segv = get_user_s64(val, addr);
1851 } else {
1852 segv = get_user_s32(val, addr);
1853 }
1854 if (!segv) {
1855 if (val != env->llval) {
1856 env->active_tc.gpr[reg] = 0;
1857 } else {
1858 if (d) {
1859 segv = put_user_u64(env->llnewval, addr);
1860 } else {
1861 segv = put_user_u32(env->llnewval, addr);
1862 }
1863 if (!segv) {
1864 env->active_tc.gpr[reg] = 1;
1865 }
1866 }
1867 }
1868 }
1869 env->CP0_LLAddr = -1;
1870 if (!segv) {
1871 env->active_tc.PC += 4;
1872 }
1873 mmap_unlock();
1874 end_exclusive();
1875 return segv;
1876 }
1877
1878 void cpu_loop(CPUMIPSState *env)
1879 {
1880 target_siginfo_t info;
1881 int trapnr, ret;
1882 unsigned int syscall_num;
1883
1884 for(;;) {
1885 cpu_exec_start(env);
1886 trapnr = cpu_mips_exec(env);
1887 cpu_exec_end(env);
1888 switch(trapnr) {
1889 case EXCP_SYSCALL:
1890 syscall_num = env->active_tc.gpr[2] - 4000;
1891 env->active_tc.PC += 4;
1892 if (syscall_num >= sizeof(mips_syscall_args)) {
1893 ret = -ENOSYS;
1894 } else {
1895 int nb_args;
1896 abi_ulong sp_reg;
1897 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
1898
1899 nb_args = mips_syscall_args[syscall_num];
1900 sp_reg = env->active_tc.gpr[29];
1901 switch (nb_args) {
1902 /* these arguments are taken from the stack */
1903 /* FIXME - what to do if get_user() fails? */
1904 case 8: get_user_ual(arg8, sp_reg + 28);
1905 case 7: get_user_ual(arg7, sp_reg + 24);
1906 case 6: get_user_ual(arg6, sp_reg + 20);
1907 case 5: get_user_ual(arg5, sp_reg + 16);
1908 default:
1909 break;
1910 }
1911 ret = do_syscall(env, env->active_tc.gpr[2],
1912 env->active_tc.gpr[4],
1913 env->active_tc.gpr[5],
1914 env->active_tc.gpr[6],
1915 env->active_tc.gpr[7],
1916 arg5, arg6/*, arg7, arg8*/);
1917 }
1918 if (ret == -TARGET_QEMU_ESIGRETURN) {
1919 /* Returning from a successful sigreturn syscall.
1920 Avoid clobbering register state. */
1921 break;
1922 }
1923 if ((unsigned int)ret >= (unsigned int)(-1133)) {
1924 env->active_tc.gpr[7] = 1; /* error flag */
1925 ret = -ret;
1926 } else {
1927 env->active_tc.gpr[7] = 0; /* error flag */
1928 }
1929 env->active_tc.gpr[2] = ret;
1930 break;
1931 case EXCP_TLBL:
1932 case EXCP_TLBS:
1933 info.si_signo = TARGET_SIGSEGV;
1934 info.si_errno = 0;
1935 /* XXX: check env->error_code */
1936 info.si_code = TARGET_SEGV_MAPERR;
1937 info._sifields._sigfault._addr = env->CP0_BadVAddr;
1938 queue_signal(env, info.si_signo, &info);
1939 break;
1940 case EXCP_CpU:
1941 case EXCP_RI:
1942 info.si_signo = TARGET_SIGILL;
1943 info.si_errno = 0;
1944 info.si_code = 0;
1945 queue_signal(env, info.si_signo, &info);
1946 break;
1947 case EXCP_INTERRUPT:
1948 /* just indicate that signals should be handled asap */
1949 break;
1950 case EXCP_DEBUG:
1951 {
1952 int sig;
1953
1954 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1955 if (sig)
1956 {
1957 info.si_signo = sig;
1958 info.si_errno = 0;
1959 info.si_code = TARGET_TRAP_BRKPT;
1960 queue_signal(env, info.si_signo, &info);
1961 }
1962 }
1963 break;
1964 case EXCP_SC:
1965 if (do_store_exclusive(env)) {
1966 info.si_signo = TARGET_SIGSEGV;
1967 info.si_errno = 0;
1968 info.si_code = TARGET_SEGV_MAPERR;
1969 info._sifields._sigfault._addr = env->active_tc.PC;
1970 queue_signal(env, info.si_signo, &info);
1971 }
1972 break;
1973 default:
1974 // error:
1975 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1976 trapnr);
1977 cpu_dump_state(env, stderr, fprintf, 0);
1978 abort();
1979 }
1980 process_pending_signals(env);
1981 }
1982 }
1983 #endif
1984
1985 #ifdef TARGET_SH4
1986 void cpu_loop (CPUState *env)
1987 {
1988 int trapnr, ret;
1989 target_siginfo_t info;
1990
1991 while (1) {
1992 trapnr = cpu_sh4_exec (env);
1993
1994 switch (trapnr) {
1995 case 0x160:
1996 env->pc += 2;
1997 ret = do_syscall(env,
1998 env->gregs[3],
1999 env->gregs[4],
2000 env->gregs[5],
2001 env->gregs[6],
2002 env->gregs[7],
2003 env->gregs[0],
2004 env->gregs[1]);
2005 env->gregs[0] = ret;
2006 break;
2007 case EXCP_INTERRUPT:
2008 /* just indicate that signals should be handled asap */
2009 break;
2010 case EXCP_DEBUG:
2011 {
2012 int sig;
2013
2014 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2015 if (sig)
2016 {
2017 info.si_signo = sig;
2018 info.si_errno = 0;
2019 info.si_code = TARGET_TRAP_BRKPT;
2020 queue_signal(env, info.si_signo, &info);
2021 }
2022 }
2023 break;
2024 case 0xa0:
2025 case 0xc0:
2026 info.si_signo = SIGSEGV;
2027 info.si_errno = 0;
2028 info.si_code = TARGET_SEGV_MAPERR;
2029 info._sifields._sigfault._addr = env->tea;
2030 queue_signal(env, info.si_signo, &info);
2031 break;
2032
2033 default:
2034 printf ("Unhandled trap: 0x%x\n", trapnr);
2035 cpu_dump_state(env, stderr, fprintf, 0);
2036 exit (1);
2037 }
2038 process_pending_signals (env);
2039 }
2040 }
2041 #endif
2042
2043 #ifdef TARGET_CRIS
2044 void cpu_loop (CPUState *env)
2045 {
2046 int trapnr, ret;
2047 target_siginfo_t info;
2048
2049 while (1) {
2050 trapnr = cpu_cris_exec (env);
2051 switch (trapnr) {
2052 case 0xaa:
2053 {
2054 info.si_signo = SIGSEGV;
2055 info.si_errno = 0;
2056 /* XXX: check env->error_code */
2057 info.si_code = TARGET_SEGV_MAPERR;
2058 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2059 queue_signal(env, info.si_signo, &info);
2060 }
2061 break;
2062 case EXCP_INTERRUPT:
2063 /* just indicate that signals should be handled asap */
2064 break;
2065 case EXCP_BREAK:
2066 ret = do_syscall(env,
2067 env->regs[9],
2068 env->regs[10],
2069 env->regs[11],
2070 env->regs[12],
2071 env->regs[13],
2072 env->pregs[7],
2073 env->pregs[11]);
2074 env->regs[10] = ret;
2075 break;
2076 case EXCP_DEBUG:
2077 {
2078 int sig;
2079
2080 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2081 if (sig)
2082 {
2083 info.si_signo = sig;
2084 info.si_errno = 0;
2085 info.si_code = TARGET_TRAP_BRKPT;
2086 queue_signal(env, info.si_signo, &info);
2087 }
2088 }
2089 break;
2090 default:
2091 printf ("Unhandled trap: 0x%x\n", trapnr);
2092 cpu_dump_state(env, stderr, fprintf, 0);
2093 exit (1);
2094 }
2095 process_pending_signals (env);
2096 }
2097 }
2098 #endif
2099
2100 #ifdef TARGET_MICROBLAZE
2101 void cpu_loop (CPUState *env)
2102 {
2103 int trapnr, ret;
2104 target_siginfo_t info;
2105
2106 while (1) {
2107 trapnr = cpu_mb_exec (env);
2108 switch (trapnr) {
2109 case 0xaa:
2110 {
2111 info.si_signo = SIGSEGV;
2112 info.si_errno = 0;
2113 /* XXX: check env->error_code */
2114 info.si_code = TARGET_SEGV_MAPERR;
2115 info._sifields._sigfault._addr = 0;
2116 queue_signal(env, info.si_signo, &info);
2117 }
2118 break;
2119 case EXCP_INTERRUPT:
2120 /* just indicate that signals should be handled asap */
2121 break;
2122 case EXCP_BREAK:
2123 /* Return address is 4 bytes after the call. */
2124 env->regs[14] += 4;
2125 ret = do_syscall(env,
2126 env->regs[12],
2127 env->regs[5],
2128 env->regs[6],
2129 env->regs[7],
2130 env->regs[8],
2131 env->regs[9],
2132 env->regs[10]);
2133 env->regs[3] = ret;
2134 env->sregs[SR_PC] = env->regs[14];
2135 break;
2136 case EXCP_DEBUG:
2137 {
2138 int sig;
2139
2140 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2141 if (sig)
2142 {
2143 info.si_signo = sig;
2144 info.si_errno = 0;
2145 info.si_code = TARGET_TRAP_BRKPT;
2146 queue_signal(env, info.si_signo, &info);
2147 }
2148 }
2149 break;
2150 default:
2151 printf ("Unhandled trap: 0x%x\n", trapnr);
2152 cpu_dump_state(env, stderr, fprintf, 0);
2153 exit (1);
2154 }
2155 process_pending_signals (env);
2156 }
2157 }
2158 #endif
2159
2160 #ifdef TARGET_M68K
2161
2162 void cpu_loop(CPUM68KState *env)
2163 {
2164 int trapnr;
2165 unsigned int n;
2166 target_siginfo_t info;
2167 TaskState *ts = env->opaque;
2168
2169 for(;;) {
2170 trapnr = cpu_m68k_exec(env);
2171 switch(trapnr) {
2172 case EXCP_ILLEGAL:
2173 {
2174 if (ts->sim_syscalls) {
2175 uint16_t nr;
2176 nr = lduw(env->pc + 2);
2177 env->pc += 4;
2178 do_m68k_simcall(env, nr);
2179 } else {
2180 goto do_sigill;
2181 }
2182 }
2183 break;
2184 case EXCP_HALT_INSN:
2185 /* Semihosing syscall. */
2186 env->pc += 4;
2187 do_m68k_semihosting(env, env->dregs[0]);
2188 break;
2189 case EXCP_LINEA:
2190 case EXCP_LINEF:
2191 case EXCP_UNSUPPORTED:
2192 do_sigill:
2193 info.si_signo = SIGILL;
2194 info.si_errno = 0;
2195 info.si_code = TARGET_ILL_ILLOPN;
2196 info._sifields._sigfault._addr = env->pc;
2197 queue_signal(env, info.si_signo, &info);
2198 break;
2199 case EXCP_TRAP0:
2200 {
2201 ts->sim_syscalls = 0;
2202 n = env->dregs[0];
2203 env->pc += 2;
2204 env->dregs[0] = do_syscall(env,
2205 n,
2206 env->dregs[1],
2207 env->dregs[2],
2208 env->dregs[3],
2209 env->dregs[4],
2210 env->dregs[5],
2211 env->aregs[0]);
2212 }
2213 break;
2214 case EXCP_INTERRUPT:
2215 /* just indicate that signals should be handled asap */
2216 break;
2217 case EXCP_ACCESS:
2218 {
2219 info.si_signo = SIGSEGV;
2220 info.si_errno = 0;
2221 /* XXX: check env->error_code */
2222 info.si_code = TARGET_SEGV_MAPERR;
2223 info._sifields._sigfault._addr = env->mmu.ar;
2224 queue_signal(env, info.si_signo, &info);
2225 }
2226 break;
2227 case EXCP_DEBUG:
2228 {
2229 int sig;
2230
2231 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2232 if (sig)
2233 {
2234 info.si_signo = sig;
2235 info.si_errno = 0;
2236 info.si_code = TARGET_TRAP_BRKPT;
2237 queue_signal(env, info.si_signo, &info);
2238 }
2239 }
2240 break;
2241 default:
2242 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2243 trapnr);
2244 cpu_dump_state(env, stderr, fprintf, 0);
2245 abort();
2246 }
2247 process_pending_signals(env);
2248 }
2249 }
2250 #endif /* TARGET_M68K */
2251
2252 #ifdef TARGET_ALPHA
2253 void cpu_loop (CPUState *env)
2254 {
2255 int trapnr;
2256 target_siginfo_t info;
2257
2258 while (1) {
2259 trapnr = cpu_alpha_exec (env);
2260
2261 switch (trapnr) {
2262 case EXCP_RESET:
2263 fprintf(stderr, "Reset requested. Exit\n");
2264 exit(1);
2265 break;
2266 case EXCP_MCHK:
2267 fprintf(stderr, "Machine check exception. Exit\n");
2268 exit(1);
2269 break;
2270 case EXCP_ARITH:
2271 fprintf(stderr, "Arithmetic trap.\n");
2272 exit(1);
2273 break;
2274 case EXCP_HW_INTERRUPT:
2275 fprintf(stderr, "External interrupt. Exit\n");
2276 exit(1);
2277 break;
2278 case EXCP_DFAULT:
2279 fprintf(stderr, "MMU data fault\n");
2280 exit(1);
2281 break;
2282 case EXCP_DTB_MISS_PAL:
2283 fprintf(stderr, "MMU data TLB miss in PALcode\n");
2284 exit(1);
2285 break;
2286 case EXCP_ITB_MISS:
2287 fprintf(stderr, "MMU instruction TLB miss\n");
2288 exit(1);
2289 break;
2290 case EXCP_ITB_ACV:
2291 fprintf(stderr, "MMU instruction access violation\n");
2292 exit(1);
2293 break;
2294 case EXCP_DTB_MISS_NATIVE:
2295 fprintf(stderr, "MMU data TLB miss\n");
2296 exit(1);
2297 break;
2298 case EXCP_UNALIGN:
2299 fprintf(stderr, "Unaligned access\n");
2300 exit(1);
2301 break;
2302 case EXCP_OPCDEC:
2303 fprintf(stderr, "Invalid instruction\n");
2304 exit(1);
2305 break;
2306 case EXCP_FEN:
2307 fprintf(stderr, "Floating-point not allowed\n");
2308 exit(1);
2309 break;
2310 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1):
2311 call_pal(env, (trapnr >> 6) | 0x80);
2312 break;
2313 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1):
2314 fprintf(stderr, "Privileged call to PALcode\n");
2315 exit(1);
2316 break;
2317 case EXCP_DEBUG:
2318 {
2319 int sig;
2320
2321 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2322 if (sig)
2323 {
2324 info.si_signo = sig;
2325 info.si_errno = 0;
2326 info.si_code = TARGET_TRAP_BRKPT;
2327 queue_signal(env, info.si_signo, &info);
2328 }
2329 }
2330 break;
2331 default:
2332 printf ("Unhandled trap: 0x%x\n", trapnr);
2333 cpu_dump_state(env, stderr, fprintf, 0);
2334 exit (1);
2335 }
2336 process_pending_signals (env);
2337 }
2338 }
2339 #endif /* TARGET_ALPHA */
2340
2341 static void usage(void)
2342 {
2343 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n"
2344 "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
2345 "Linux CPU emulator (compiled for %s emulation)\n"
2346 "\n"
2347 "Standard options:\n"
2348 "-h print this help\n"
2349 "-g port wait gdb connection to port\n"
2350 "-L path set the elf interpreter prefix (default=%s)\n"
2351 "-s size set the stack size in bytes (default=%ld)\n"
2352 "-cpu model select CPU (-cpu ? for list)\n"
2353 "-drop-ld-preload drop LD_PRELOAD for target process\n"
2354 "-E var=value sets/modifies targets environment variable(s)\n"
2355 "-U var unsets targets environment variable(s)\n"
2356 "-0 argv0 forces target process argv[0] to be argv0\n"
2357 "\n"
2358 "Debug options:\n"
2359 "-d options activate log (logfile=%s)\n"
2360 "-p pagesize set the host page size to 'pagesize'\n"
2361 "-singlestep always run in singlestep mode\n"
2362 "-strace log system calls\n"
2363 "\n"
2364 "Environment variables:\n"
2365 "QEMU_STRACE Print system calls and arguments similar to the\n"
2366 " 'strace' program. Enable by setting to any value.\n"
2367 "You can use -E and -U options to set/unset environment variables\n"
2368 "for target process. It is possible to provide several variables\n"
2369 "by repeating the option. For example:\n"
2370 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
2371 "Note that if you provide several changes to single variable\n"
2372 "last change will stay in effect.\n"
2373 ,
2374 TARGET_ARCH,
2375 interp_prefix,
2376 x86_stack_size,
2377 DEBUG_LOGFILE);
2378 exit(1);
2379 }
2380
2381 THREAD CPUState *thread_env;
2382
2383 void task_settid(TaskState *ts)
2384 {
2385 if (ts->ts_tid == 0) {
2386 #ifdef USE_NPTL
2387 ts->ts_tid = (pid_t)syscall(SYS_gettid);
2388 #else
2389 /* when no threads are used, tid becomes pid */
2390 ts->ts_tid = getpid();
2391 #endif
2392 }
2393 }
2394
2395 void stop_all_tasks(void)
2396 {
2397 /*
2398 * We trust that when using NPTL, start_exclusive()
2399 * handles thread stopping correctly.
2400 */
2401 start_exclusive();
2402 }
2403
2404 /* Assumes contents are already zeroed. */
2405 void init_task_state(TaskState *ts)
2406 {
2407 int i;
2408
2409 ts->used = 1;
2410 ts->first_free = ts->sigqueue_table;
2411 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
2412 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
2413 }
2414 ts->sigqueue_table[i].next = NULL;
2415 }
2416
2417 int main(int argc, char **argv, char **envp)
2418 {
2419 const char *filename;
2420 const char *cpu_model;
2421 struct target_pt_regs regs1, *regs = &regs1;
2422 struct image_info info1, *info = &info1;
2423 struct linux_binprm bprm;
2424 TaskState ts1, *ts = &ts1;
2425 CPUState *env;
2426 int optind;
2427 const char *r;
2428 int gdbstub_port = 0;
2429 char **target_environ, **wrk;
2430 char **target_argv;
2431 int target_argc;
2432 envlist_t *envlist = NULL;
2433 const char *argv0 = NULL;
2434 int i;
2435 int ret;
2436
2437 if (argc <= 1)
2438 usage();
2439
2440 qemu_cache_utils_init(envp);
2441
2442 /* init debug */
2443 cpu_set_log_filename(DEBUG_LOGFILE);
2444
2445 if ((envlist = envlist_create()) == NULL) {
2446 (void) fprintf(stderr, "Unable to allocate envlist\n");
2447 exit(1);
2448 }
2449
2450 /* add current environment into the list */
2451 for (wrk = environ; *wrk != NULL; wrk++) {
2452 (void) envlist_setenv(envlist, *wrk);
2453 }
2454
2455 cpu_model = NULL;
2456 optind = 1;
2457 for(;;) {
2458 if (optind >= argc)
2459 break;
2460 r = argv[optind];
2461 if (r[0] != '-')
2462 break;
2463 optind++;
2464 r++;
2465 if (!strcmp(r, "-")) {
2466 break;
2467 } else if (!strcmp(r, "d")) {
2468 int mask;
2469 const CPULogItem *item;
2470
2471 if (optind >= argc)
2472 break;
2473
2474 r = argv[optind++];
2475 mask = cpu_str_to_log_mask(r);
2476 if (!mask) {
2477 printf("Log items (comma separated):\n");
2478 for(item = cpu_log_items; item->mask != 0; item++) {
2479 printf("%-10s %s\n", item->name, item->help);
2480 }
2481 exit(1);
2482 }
2483 cpu_set_log(mask);
2484 } else if (!strcmp(r, "E")) {
2485 r = argv[optind++];
2486 if (envlist_setenv(envlist, r) != 0)
2487 usage();
2488 } else if (!strcmp(r, "U")) {
2489 r = argv[optind++];
2490 if (envlist_unsetenv(envlist, r) != 0)
2491 usage();
2492 } else if (!strcmp(r, "0")) {
2493 r = argv[optind++];
2494 argv0 = r;
2495 } else if (!strcmp(r, "s")) {
2496 if (optind >= argc)
2497 break;
2498 r = argv[optind++];
2499 x86_stack_size = strtol(r, (char **)&r, 0);
2500 if (x86_stack_size <= 0)
2501 usage();
2502 if (*r == 'M')
2503 x86_stack_size *= 1024 * 1024;
2504 else if (*r == 'k' || *r == 'K')
2505 x86_stack_size *= 1024;
2506 } else if (!strcmp(r, "L")) {
2507 interp_prefix = argv[optind++];
2508 } else if (!strcmp(r, "p")) {
2509 if (optind >= argc)
2510 break;
2511 qemu_host_page_size = atoi(argv[optind++]);
2512 if (qemu_host_page_size == 0 ||
2513 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
2514 fprintf(stderr, "page size must be a power of two\n");
2515 exit(1);
2516 }
2517 } else if (!strcmp(r, "g")) {
2518 if (optind >= argc)
2519 break;
2520 gdbstub_port = atoi(argv[optind++]);
2521 } else if (!strcmp(r, "r")) {
2522 qemu_uname_release = argv[optind++];
2523 } else if (!strcmp(r, "cpu")) {
2524 cpu_model = argv[optind++];
2525 if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) {
2526 /* XXX: implement xxx_cpu_list for targets that still miss it */
2527 #if defined(cpu_list)
2528 cpu_list(stdout, &fprintf);
2529 #endif
2530 exit(1);
2531 }
2532 } else if (!strcmp(r, "drop-ld-preload")) {
2533 (void) envlist_unsetenv(envlist, "LD_PRELOAD");
2534 } else if (!strcmp(r, "singlestep")) {
2535 singlestep = 1;
2536 } else if (!strcmp(r, "strace")) {
2537 do_strace = 1;
2538 } else
2539 {
2540 usage();
2541 }
2542 }
2543 if (optind >= argc)
2544 usage();
2545 filename = argv[optind];
2546 exec_path = argv[optind];
2547
2548 /* Zero out regs */
2549 memset(regs, 0, sizeof(struct target_pt_regs));
2550
2551 /* Zero out image_info */
2552 memset(info, 0, sizeof(struct image_info));
2553
2554 memset(&bprm, 0, sizeof (bprm));
2555
2556 /* Scan interp_prefix dir for replacement files. */
2557 init_paths(interp_prefix);
2558
2559 if (cpu_model == NULL) {
2560 #if defined(TARGET_I386)
2561 #ifdef TARGET_X86_64
2562 cpu_model = "qemu64";
2563 #else
2564 cpu_model = "qemu32";
2565 #endif
2566 #elif defined(TARGET_ARM)
2567 cpu_model = "any";
2568 #elif defined(TARGET_M68K)
2569 cpu_model = "any";
2570 #elif defined(TARGET_SPARC)
2571 #ifdef TARGET_SPARC64
2572 cpu_model = "TI UltraSparc II";
2573 #else
2574 cpu_model = "Fujitsu MB86904";
2575 #endif
2576 #elif defined(TARGET_MIPS)
2577 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
2578 cpu_model = "20Kc";
2579 #else
2580 cpu_model = "24Kf";
2581 #endif
2582 #elif defined(TARGET_PPC)
2583 #ifdef TARGET_PPC64
2584 cpu_model = "970";
2585 #else
2586 cpu_model = "750";
2587 #endif
2588 #else
2589 cpu_model = "any";
2590 #endif
2591 }
2592 cpu_exec_init_all(0);
2593 /* NOTE: we need to init the CPU at this stage to get
2594 qemu_host_page_size */
2595 env = cpu_init(cpu_model);
2596 if (!env) {
2597 fprintf(stderr, "Unable to find CPU definition\n");
2598 exit(1);
2599 }
2600 thread_env = env;
2601
2602 if (getenv("QEMU_STRACE")) {
2603 do_strace = 1;
2604 }
2605
2606 target_environ = envlist_to_environ(envlist, NULL);
2607 envlist_free(envlist);
2608
2609 /*
2610 * Prepare copy of argv vector for target.
2611 */
2612 target_argc = argc - optind;
2613 target_argv = calloc(target_argc + 1, sizeof (char *));
2614 if (target_argv == NULL) {
2615 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
2616 exit(1);
2617 }
2618
2619 /*
2620 * If argv0 is specified (using '-0' switch) we replace
2621 * argv[0] pointer with the given one.
2622 */
2623 i = 0;
2624 if (argv0 != NULL) {
2625 target_argv[i++] = strdup(argv0);
2626 }
2627 for (; i < target_argc; i++) {
2628 target_argv[i] = strdup(argv[optind + i]);
2629 }
2630 target_argv[target_argc] = NULL;
2631
2632 memset(ts, 0, sizeof(TaskState));
2633 init_task_state(ts);
2634 /* build Task State */
2635 ts->info = info;
2636 ts->bprm = &bprm;
2637 env->opaque = ts;
2638 task_settid(ts);
2639
2640 ret = loader_exec(filename, target_argv, target_environ, regs,
2641 info, &bprm);
2642 if (ret != 0) {
2643 printf("Error %d while loading %s\n", ret, filename);
2644 _exit(1);
2645 }
2646
2647 for (i = 0; i < target_argc; i++) {
2648 free(target_argv[i]);
2649 }
2650 free(target_argv);
2651
2652 for (wrk = target_environ; *wrk; wrk++) {
2653 free(*wrk);
2654 }
2655
2656 free(target_environ);
2657
2658 if (qemu_log_enabled()) {
2659 log_page_dump();
2660
2661 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
2662 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
2663 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
2664 info->start_code);
2665 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
2666 info->start_data);
2667 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
2668 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
2669 info->start_stack);
2670 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
2671 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
2672 }
2673
2674 target_set_brk(info->brk);
2675 syscall_init();
2676 signal_init();
2677
2678 #if defined(TARGET_I386)
2679 cpu_x86_set_cpl(env, 3);
2680
2681 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
2682 env->hflags |= HF_PE_MASK;
2683 if (env->cpuid_features & CPUID_SSE) {
2684 env->cr[4] |= CR4_OSFXSR_MASK;
2685 env->hflags |= HF_OSFXSR_MASK;
2686 }
2687 #ifndef TARGET_ABI32
2688 /* enable 64 bit mode if possible */
2689 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
2690 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
2691 exit(1);
2692 }
2693 env->cr[4] |= CR4_PAE_MASK;
2694 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
2695 env->hflags |= HF_LMA_MASK;
2696 #endif
2697
2698 /* flags setup : we activate the IRQs by default as in user mode */
2699 env->eflags |= IF_MASK;
2700
2701 /* linux register setup */
2702 #ifndef TARGET_ABI32
2703 env->regs[R_EAX] = regs->rax;
2704 env->regs[R_EBX] = regs->rbx;
2705 env->regs[R_ECX] = regs->rcx;
2706 env->regs[R_EDX] = regs->rdx;
2707 env->regs[R_ESI] = regs->rsi;
2708 env->regs[R_EDI] = regs->rdi;
2709 env->regs[R_EBP] = regs->rbp;
2710 env->regs[R_ESP] = regs->rsp;
2711 env->eip = regs->rip;
2712 #else
2713 env->regs[R_EAX] = regs->eax;
2714 env->regs[R_EBX] = regs->ebx;
2715 env->regs[R_ECX] = regs->ecx;
2716 env->regs[R_EDX] = regs->edx;
2717 env->regs[R_ESI] = regs->esi;
2718 env->regs[R_EDI] = regs->edi;
2719 env->regs[R_EBP] = regs->ebp;
2720 env->regs[R_ESP] = regs->esp;
2721 env->eip = regs->eip;
2722 #endif
2723
2724 /* linux interrupt setup */
2725 #ifndef TARGET_ABI32
2726 env->idt.limit = 511;
2727 #else
2728 env->idt.limit = 255;
2729 #endif
2730 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
2731 PROT_READ|PROT_WRITE,
2732 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2733 idt_table = g2h(env->idt.base);
2734 set_idt(0, 0);
2735 set_idt(1, 0);
2736 set_idt(2, 0);
2737 set_idt(3, 3);
2738 set_idt(4, 3);
2739 set_idt(5, 0);
2740 set_idt(6, 0);
2741 set_idt(7, 0);
2742 set_idt(8, 0);
2743 set_idt(9, 0);
2744 set_idt(10, 0);
2745 set_idt(11, 0);
2746 set_idt(12, 0);
2747 set_idt(13, 0);
2748 set_idt(14, 0);
2749 set_idt(15, 0);
2750 set_idt(16, 0);
2751 set_idt(17, 0);
2752 set_idt(18, 0);
2753 set_idt(19, 0);
2754 set_idt(0x80, 3);
2755
2756 /* linux segment setup */
2757 {
2758 uint64_t *gdt_table;
2759 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
2760 PROT_READ|PROT_WRITE,
2761 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2762 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
2763 gdt_table = g2h(env->gdt.base);
2764 #ifdef TARGET_ABI32
2765 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2766 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2767 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2768 #else
2769 /* 64 bit code segment */
2770 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2771 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2772 DESC_L_MASK |
2773 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2774 #endif
2775 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
2776 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2777 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
2778 }
2779 cpu_x86_load_seg(env, R_CS, __USER_CS);
2780 cpu_x86_load_seg(env, R_SS, __USER_DS);
2781 #ifdef TARGET_ABI32
2782 cpu_x86_load_seg(env, R_DS, __USER_DS);
2783 cpu_x86_load_seg(env, R_ES, __USER_DS);
2784 cpu_x86_load_seg(env, R_FS, __USER_DS);
2785 cpu_x86_load_seg(env, R_GS, __USER_DS);
2786 /* This hack makes Wine work... */
2787 env->segs[R_FS].selector = 0;
2788 #else
2789 cpu_x86_load_seg(env, R_DS, 0);
2790 cpu_x86_load_seg(env, R_ES, 0);
2791 cpu_x86_load_seg(env, R_FS, 0);
2792 cpu_x86_load_seg(env, R_GS, 0);
2793 #endif
2794 #elif defined(TARGET_ARM)
2795 {
2796 int i;
2797 cpsr_write(env, regs->uregs[16], 0xffffffff);
2798 for(i = 0; i < 16; i++) {
2799 env->regs[i] = regs->uregs[i];
2800 }
2801 }
2802 #elif defined(TARGET_SPARC)
2803 {
2804 int i;
2805 env->pc = regs->pc;
2806 env->npc = regs->npc;
2807 env->y = regs->y;
2808 for(i = 0; i < 8; i++)
2809 env->gregs[i] = regs->u_regs[i];
2810 for(i = 0; i < 8; i++)
2811 env->regwptr[i] = regs->u_regs[i + 8];
2812 }
2813 #elif defined(TARGET_PPC)
2814 {
2815 int i;
2816
2817 #if defined(TARGET_PPC64)
2818 #if defined(TARGET_ABI32)
2819 env->msr &= ~((target_ulong)1 << MSR_SF);
2820 #else
2821 env->msr |= (target_ulong)1 << MSR_SF;
2822 #endif
2823 #endif
2824 env->nip = regs->nip;
2825 for(i = 0; i < 32; i++) {
2826 env->gpr[i] = regs->gpr[i];
2827 }
2828 }
2829 #elif defined(TARGET_M68K)
2830 {
2831 env->pc = regs->pc;
2832 env->dregs[0] = regs->d0;
2833 env->dregs[1] = regs->d1;
2834 env->dregs[2] = regs->d2;
2835 env->dregs[3] = regs->d3;
2836 env->dregs[4] = regs->d4;
2837 env->dregs[5] = regs->d5;
2838 env->dregs[6] = regs->d6;
2839 env->dregs[7] = regs->d7;
2840 env->aregs[0] = regs->a0;
2841 env->aregs[1] = regs->a1;
2842 env->aregs[2] = regs->a2;
2843 env->aregs[3] = regs->a3;
2844 env->aregs[4] = regs->a4;
2845 env->aregs[5] = regs->a5;
2846 env->aregs[6] = regs->a6;
2847 env->aregs[7] = regs->usp;
2848 env->sr = regs->sr;
2849 ts->sim_syscalls = 1;
2850 }
2851 #elif defined(TARGET_MICROBLAZE)
2852 {
2853 env->regs[0] = regs->r0;
2854 env->regs[1] = regs->r1;
2855 env->regs[2] = regs->r2;
2856 env->regs[3] = regs->r3;
2857 env->regs[4] = regs->r4;
2858 env->regs[5] = regs->r5;
2859 env->regs[6] = regs->r6;
2860 env->regs[7] = regs->r7;
2861 env->regs[8] = regs->r8;
2862 env->regs[9] = regs->r9;
2863 env->regs[10] = regs->r10;
2864 env->regs[11] = regs->r11;
2865 env->regs[12] = regs->r12;
2866 env->regs[13] = regs->r13;
2867 env->regs[14] = regs->r14;
2868 env->regs[15] = regs->r15;
2869 env->regs[16] = regs->r16;
2870 env->regs[17] = regs->r17;
2871 env->regs[18] = regs->r18;
2872 env->regs[19] = regs->r19;
2873 env->regs[20] = regs->r20;
2874 env->regs[21] = regs->r21;
2875 env->regs[22] = regs->r22;
2876 env->regs[23] = regs->r23;
2877 env->regs[24] = regs->r24;
2878 env->regs[25] = regs->r25;
2879 env->regs[26] = regs->r26;
2880 env->regs[27] = regs->r27;
2881 env->regs[28] = regs->r28;
2882 env->regs[29] = regs->r29;
2883 env->regs[30] = regs->r30;
2884 env->regs[31] = regs->r31;
2885 env->sregs[SR_PC] = regs->pc;
2886 }
2887 #elif defined(TARGET_MIPS)
2888 {
2889 int i;
2890
2891 for(i = 0; i < 32; i++) {
2892 env->active_tc.gpr[i] = regs->regs[i];
2893 }
2894 env->active_tc.PC = regs->cp0_epc;
2895 }
2896 #elif defined(TARGET_SH4)
2897 {
2898 int i;
2899
2900 for(i = 0; i < 16; i++) {
2901 env->gregs[i] = regs->regs[i];
2902 }
2903 env->pc = regs->pc;
2904 }
2905 #elif defined(TARGET_ALPHA)
2906 {
2907 int i;
2908
2909 for(i = 0; i < 28; i++) {
2910 env->ir[i] = ((abi_ulong *)regs)[i];
2911 }
2912 env->ipr[IPR_USP] = regs->usp;
2913 env->ir[30] = regs->usp;
2914 env->pc = regs->pc;
2915 env->unique = regs->unique;
2916 }
2917 #elif defined(TARGET_CRIS)
2918 {
2919 env->regs[0] = regs->r0;
2920 env->regs[1] = regs->r1;
2921 env->regs[2] = regs->r2;
2922 env->regs[3] = regs->r3;
2923 env->regs[4] = regs->r4;
2924 env->regs[5] = regs->r5;
2925 env->regs[6] = regs->r6;
2926 env->regs[7] = regs->r7;
2927 env->regs[8] = regs->r8;
2928 env->regs[9] = regs->r9;
2929 env->regs[10] = regs->r10;
2930 env->regs[11] = regs->r11;
2931 env->regs[12] = regs->r12;
2932 env->regs[13] = regs->r13;
2933 env->regs[14] = info->start_stack;
2934 env->regs[15] = regs->acr;
2935 env->pc = regs->erp;
2936 }
2937 #else
2938 #error unsupported target CPU
2939 #endif
2940
2941 #if defined(TARGET_ARM) || defined(TARGET_M68K)
2942 ts->stack_base = info->start_stack;
2943 ts->heap_base = info->brk;
2944 /* This will be filled in on the first SYS_HEAPINFO call. */
2945 ts->heap_limit = 0;
2946 #endif
2947
2948 if (gdbstub_port) {
2949 gdbserver_start (gdbstub_port);
2950 gdb_handlesig(env, 0);
2951 }
2952 cpu_loop(env);
2953 /* never exits */
2954 return 0;
2955 }
Adding pft support to QEMU's arm cpus