2 * QEMU Parallel PORT emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2007 Marko Kohtala
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu-char.h"
30 //#define DEBUG_PARALLEL
33 #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
35 #define pdebug(fmt, ...) ((void)0)
38 #define PARA_REG_DATA 0
39 #define PARA_REG_STS 1
40 #define PARA_REG_CTR 2
41 #define PARA_REG_EPP_ADDR 3
42 #define PARA_REG_EPP_DATA 4
45 * These are the definitions for the Printer Status Register
47 #define PARA_STS_BUSY 0x80 /* Busy complement */
48 #define PARA_STS_ACK 0x40 /* Acknowledge */
49 #define PARA_STS_PAPER 0x20 /* Out of paper */
50 #define PARA_STS_ONLINE 0x10 /* Online */
51 #define PARA_STS_ERROR 0x08 /* Error complement */
52 #define PARA_STS_TMOUT 0x01 /* EPP timeout */
55 * These are the definitions for the Printer Control Register
57 #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
58 #define PARA_CTR_INTEN 0x10 /* IRQ Enable */
59 #define PARA_CTR_SELECT 0x08 /* Select In complement */
60 #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
61 #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
62 #define PARA_CTR_STROBE 0x01 /* Strobe complement */
64 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
66 struct ParallelState
{
76 uint32_t last_read_offset
; /* For debugging */
77 /* Memory-mapped interface */
81 typedef struct ISAParallelState
{
88 static void parallel_update_irq(ParallelState
*s
)
91 qemu_irq_raise(s
->irq
);
93 qemu_irq_lower(s
->irq
);
97 parallel_ioport_write_sw(void *opaque
, uint32_t addr
, uint32_t val
)
99 ParallelState
*s
= opaque
;
101 pdebug("write addr=0x%02x val=0x%02x\n", addr
, val
);
107 parallel_update_irq(s
);
111 if ((val
& PARA_CTR_INIT
) == 0 ) {
112 s
->status
= PARA_STS_BUSY
;
113 s
->status
|= PARA_STS_ACK
;
114 s
->status
|= PARA_STS_ONLINE
;
115 s
->status
|= PARA_STS_ERROR
;
117 else if (val
& PARA_CTR_SELECT
) {
118 if (val
& PARA_CTR_STROBE
) {
119 s
->status
&= ~PARA_STS_BUSY
;
120 if ((s
->control
& PARA_CTR_STROBE
) == 0)
121 qemu_chr_write(s
->chr
, &s
->dataw
, 1);
123 if (s
->control
& PARA_CTR_INTEN
) {
128 parallel_update_irq(s
);
134 static void parallel_ioport_write_hw(void *opaque
, uint32_t addr
, uint32_t val
)
136 ParallelState
*s
= opaque
;
140 /* Sometimes programs do several writes for timing purposes on old
141 HW. Take care not to waste time on writes that do nothing. */
143 s
->last_read_offset
= ~0U;
150 pdebug("wd%02x\n", val
);
151 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_WRITE_DATA
, &parm
);
155 pdebug("ws%02x\n", val
);
156 if (val
& PARA_STS_TMOUT
)
161 if (s
->control
== val
)
163 pdebug("wc%02x\n", val
);
165 if ((val
& PARA_CTR_DIR
) != (s
->control
& PARA_CTR_DIR
)) {
166 if (val
& PARA_CTR_DIR
) {
171 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_DATA_DIR
, &dir
);
172 parm
&= ~PARA_CTR_DIR
;
175 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_WRITE_CONTROL
, &parm
);
178 case PARA_REG_EPP_ADDR
:
179 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != PARA_CTR_INIT
)
180 /* Controls not correct for EPP address cycle, so do nothing */
181 pdebug("wa%02x s\n", val
);
183 struct ParallelIOArg ioarg
= { .buffer
= &parm
, .count
= 1 };
184 if (qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_WRITE_ADDR
, &ioarg
)) {
186 pdebug("wa%02x t\n", val
);
189 pdebug("wa%02x\n", val
);
192 case PARA_REG_EPP_DATA
:
193 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != PARA_CTR_INIT
)
194 /* Controls not correct for EPP data cycle, so do nothing */
195 pdebug("we%02x s\n", val
);
197 struct ParallelIOArg ioarg
= { .buffer
= &parm
, .count
= 1 };
198 if (qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_WRITE
, &ioarg
)) {
200 pdebug("we%02x t\n", val
);
203 pdebug("we%02x\n", val
);
210 parallel_ioport_eppdata_write_hw2(void *opaque
, uint32_t addr
, uint32_t val
)
212 ParallelState
*s
= opaque
;
213 uint16_t eppdata
= cpu_to_le16(val
);
215 struct ParallelIOArg ioarg
= {
216 .buffer
= &eppdata
, .count
= sizeof(eppdata
)
218 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != PARA_CTR_INIT
) {
219 /* Controls not correct for EPP data cycle, so do nothing */
220 pdebug("we%04x s\n", val
);
223 err
= qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_WRITE
, &ioarg
);
226 pdebug("we%04x t\n", val
);
229 pdebug("we%04x\n", val
);
233 parallel_ioport_eppdata_write_hw4(void *opaque
, uint32_t addr
, uint32_t val
)
235 ParallelState
*s
= opaque
;
236 uint32_t eppdata
= cpu_to_le32(val
);
238 struct ParallelIOArg ioarg
= {
239 .buffer
= &eppdata
, .count
= sizeof(eppdata
)
241 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != PARA_CTR_INIT
) {
242 /* Controls not correct for EPP data cycle, so do nothing */
243 pdebug("we%08x s\n", val
);
246 err
= qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_WRITE
, &ioarg
);
249 pdebug("we%08x t\n", val
);
252 pdebug("we%08x\n", val
);
255 static uint32_t parallel_ioport_read_sw(void *opaque
, uint32_t addr
)
257 ParallelState
*s
= opaque
;
263 if (s
->control
& PARA_CTR_DIR
)
271 if ((s
->status
& PARA_STS_BUSY
) == 0 && (s
->control
& PARA_CTR_STROBE
) == 0) {
272 /* XXX Fixme: wait 5 microseconds */
273 if (s
->status
& PARA_STS_ACK
)
274 s
->status
&= ~PARA_STS_ACK
;
276 /* XXX Fixme: wait 5 microseconds */
277 s
->status
|= PARA_STS_ACK
;
278 s
->status
|= PARA_STS_BUSY
;
281 parallel_update_irq(s
);
287 pdebug("read addr=0x%02x val=0x%02x\n", addr
, ret
);
291 static uint32_t parallel_ioport_read_hw(void *opaque
, uint32_t addr
)
293 ParallelState
*s
= opaque
;
298 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_READ_DATA
, &ret
);
299 if (s
->last_read_offset
!= addr
|| s
->datar
!= ret
)
300 pdebug("rd%02x\n", ret
);
304 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_READ_STATUS
, &ret
);
305 ret
&= ~PARA_STS_TMOUT
;
307 ret
|= PARA_STS_TMOUT
;
308 if (s
->last_read_offset
!= addr
|| s
->status
!= ret
)
309 pdebug("rs%02x\n", ret
);
313 /* s->control has some bits fixed to 1. It is zero only when
314 it has not been yet written to. */
315 if (s
->control
== 0) {
316 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_READ_CONTROL
, &ret
);
317 if (s
->last_read_offset
!= addr
)
318 pdebug("rc%02x\n", ret
);
323 if (s
->last_read_offset
!= addr
)
324 pdebug("rc%02x\n", ret
);
327 case PARA_REG_EPP_ADDR
:
328 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != (PARA_CTR_DIR
|PARA_CTR_INIT
))
329 /* Controls not correct for EPP addr cycle, so do nothing */
330 pdebug("ra%02x s\n", ret
);
332 struct ParallelIOArg ioarg
= { .buffer
= &ret
, .count
= 1 };
333 if (qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_READ_ADDR
, &ioarg
)) {
335 pdebug("ra%02x t\n", ret
);
338 pdebug("ra%02x\n", ret
);
341 case PARA_REG_EPP_DATA
:
342 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != (PARA_CTR_DIR
|PARA_CTR_INIT
))
343 /* Controls not correct for EPP data cycle, so do nothing */
344 pdebug("re%02x s\n", ret
);
346 struct ParallelIOArg ioarg
= { .buffer
= &ret
, .count
= 1 };
347 if (qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_READ
, &ioarg
)) {
349 pdebug("re%02x t\n", ret
);
352 pdebug("re%02x\n", ret
);
356 s
->last_read_offset
= addr
;
361 parallel_ioport_eppdata_read_hw2(void *opaque
, uint32_t addr
)
363 ParallelState
*s
= opaque
;
365 uint16_t eppdata
= ~0;
367 struct ParallelIOArg ioarg
= {
368 .buffer
= &eppdata
, .count
= sizeof(eppdata
)
370 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != (PARA_CTR_DIR
|PARA_CTR_INIT
)) {
371 /* Controls not correct for EPP data cycle, so do nothing */
372 pdebug("re%04x s\n", eppdata
);
375 err
= qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_READ
, &ioarg
);
376 ret
= le16_to_cpu(eppdata
);
380 pdebug("re%04x t\n", ret
);
383 pdebug("re%04x\n", ret
);
388 parallel_ioport_eppdata_read_hw4(void *opaque
, uint32_t addr
)
390 ParallelState
*s
= opaque
;
392 uint32_t eppdata
= ~0U;
394 struct ParallelIOArg ioarg
= {
395 .buffer
= &eppdata
, .count
= sizeof(eppdata
)
397 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != (PARA_CTR_DIR
|PARA_CTR_INIT
)) {
398 /* Controls not correct for EPP data cycle, so do nothing */
399 pdebug("re%08x s\n", eppdata
);
402 err
= qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_READ
, &ioarg
);
403 ret
= le32_to_cpu(eppdata
);
407 pdebug("re%08x t\n", ret
);
410 pdebug("re%08x\n", ret
);
414 static void parallel_ioport_ecp_write(void *opaque
, uint32_t addr
, uint32_t val
)
417 pdebug("wecp%d=%02x\n", addr
, val
);
420 static uint32_t parallel_ioport_ecp_read(void *opaque
, uint32_t addr
)
424 pdebug("recp%d:%02x\n", addr
, ret
);
428 static void parallel_reset(void *opaque
)
430 ParallelState
*s
= opaque
;
434 s
->status
= PARA_STS_BUSY
;
435 s
->status
|= PARA_STS_ACK
;
436 s
->status
|= PARA_STS_ONLINE
;
437 s
->status
|= PARA_STS_ERROR
;
438 s
->status
|= PARA_STS_TMOUT
;
439 s
->control
= PARA_CTR_SELECT
;
440 s
->control
|= PARA_CTR_INIT
;
445 s
->last_read_offset
= ~0U;
448 static int parallel_isa_initfn(ISADevice
*dev
)
450 ISAParallelState
*isa
= DO_UPCAST(ISAParallelState
, dev
, dev
);
451 ParallelState
*s
= &isa
->state
;
452 int base
= isa
->iobase
;
456 fprintf(stderr
, "Can't create parallel device, empty char device\n");
460 isa_init_irq(dev
, &s
->irq
, isa
->isairq
);
462 qemu_register_reset(parallel_reset
, s
);
464 if (qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_READ_STATUS
, &dummy
) == 0) {
470 register_ioport_write(base
, 8, 1, parallel_ioport_write_hw
, s
);
471 register_ioport_read(base
, 8, 1, parallel_ioport_read_hw
, s
);
472 register_ioport_write(base
+4, 1, 2, parallel_ioport_eppdata_write_hw2
, s
);
473 register_ioport_read(base
+4, 1, 2, parallel_ioport_eppdata_read_hw2
, s
);
474 register_ioport_write(base
+4, 1, 4, parallel_ioport_eppdata_write_hw4
, s
);
475 register_ioport_read(base
+4, 1, 4, parallel_ioport_eppdata_read_hw4
, s
);
476 register_ioport_write(base
+0x400, 8, 1, parallel_ioport_ecp_write
, s
);
477 register_ioport_read(base
+0x400, 8, 1, parallel_ioport_ecp_read
, s
);
480 register_ioport_write(base
, 8, 1, parallel_ioport_write_sw
, s
);
481 register_ioport_read(base
, 8, 1, parallel_ioport_read_sw
, s
);
486 static const int isa_parallel_io
[MAX_PARALLEL_PORTS
] = { 0x378, 0x278, 0x3bc };
488 ParallelState
*parallel_init(int index
, CharDriverState
*chr
)
492 dev
= isa_create("isa-parallel");
493 qdev_prop_set_uint32(&dev
->qdev
, "iobase", isa_parallel_io
[index
]);
494 qdev_prop_set_uint32(&dev
->qdev
, "irq", 7);
495 qdev_prop_set_chr(&dev
->qdev
, "chardev", chr
);
496 if (qdev_init(&dev
->qdev
) != 0)
498 return &DO_UPCAST(ISAParallelState
, dev
, dev
)->state
;
501 /* Memory mapped interface */
502 static uint32_t parallel_mm_readb (void *opaque
, target_phys_addr_t addr
)
504 ParallelState
*s
= opaque
;
506 return parallel_ioport_read_sw(s
, addr
>> s
->it_shift
) & 0xFF;
509 static void parallel_mm_writeb (void *opaque
,
510 target_phys_addr_t addr
, uint32_t value
)
512 ParallelState
*s
= opaque
;
514 parallel_ioport_write_sw(s
, addr
>> s
->it_shift
, value
& 0xFF);
517 static uint32_t parallel_mm_readw (void *opaque
, target_phys_addr_t addr
)
519 ParallelState
*s
= opaque
;
521 return parallel_ioport_read_sw(s
, addr
>> s
->it_shift
) & 0xFFFF;
524 static void parallel_mm_writew (void *opaque
,
525 target_phys_addr_t addr
, uint32_t value
)
527 ParallelState
*s
= opaque
;
529 parallel_ioport_write_sw(s
, addr
>> s
->it_shift
, value
& 0xFFFF);
532 static uint32_t parallel_mm_readl (void *opaque
, target_phys_addr_t addr
)
534 ParallelState
*s
= opaque
;
536 return parallel_ioport_read_sw(s
, addr
>> s
->it_shift
);
539 static void parallel_mm_writel (void *opaque
,
540 target_phys_addr_t addr
, uint32_t value
)
542 ParallelState
*s
= opaque
;
544 parallel_ioport_write_sw(s
, addr
>> s
->it_shift
, value
);
547 static CPUReadMemoryFunc
* const parallel_mm_read_sw
[] = {
553 static CPUWriteMemoryFunc
* const parallel_mm_write_sw
[] = {
559 /* If fd is zero, it means that the parallel device uses the console */
560 ParallelState
*parallel_mm_init(target_phys_addr_t base
, int it_shift
, qemu_irq irq
, CharDriverState
*chr
)
565 s
= qemu_mallocz(sizeof(ParallelState
));
568 s
->it_shift
= it_shift
;
570 qemu_register_reset(parallel_reset
, s
);
572 io_sw
= cpu_register_io_memory(parallel_mm_read_sw
, parallel_mm_write_sw
, s
);
573 cpu_register_physical_memory(base
, 8 << it_shift
, io_sw
);
577 static ISADeviceInfo parallel_isa_info
= {
578 .qdev
.name
= "isa-parallel",
579 .qdev
.size
= sizeof(ISAParallelState
),
580 .init
= parallel_isa_initfn
,
581 .qdev
.props
= (Property
[]) {
582 DEFINE_PROP_HEX32("iobase", ISAParallelState
, iobase
, 0x378),
583 DEFINE_PROP_UINT32("irq", ISAParallelState
, isairq
, 7),
584 DEFINE_PROP_CHR("chardev", ISAParallelState
, state
.chr
),
585 DEFINE_PROP_END_OF_LIST(),
589 static void parallel_register_devices(void)
591 isa_qdev_register(¶llel_isa_info
);
594 device_init(parallel_register_devices
)