libs/pbd/fpu.cc

   1 #define _XOPEN_SOURCE 600
   2 #include <cstring> // for memset
   3 #include <cstdlib>
   4 #include <stdint.h>
   5
   6 #include "pbd/fpu.h"
   7 #include "pbd/error.h"
   8
   9 #include "i18n.h"
  10
  11 using namespace PBD;
  12 using namespace std;
  13
  14 FPU::FPU ()
  15 {
  16         unsigned long cpuflags = 0;
  17
  18         _flags = Flags (0);
  19
  20 #ifndef ARCH_X86
  21         return;
  22 #endif
  23
  24
  25 #ifndef USE_X86_64_ASM
  26         asm volatile (
  27                 "mov $1, %%eax\n"
  28                 "pushl %%ebx\n"
  29                 "cpuid\n"
  30                 "movl %%edx, %0\n"
  31                 "popl %%ebx\n"
  32                 : "=r" (cpuflags)
  33                 :
  34                 : "%eax", "%ecx", "%edx"
  35                 );
  36
  37 #else
  38
  39         /* asm notes: although we explicitly save&restore rbx, we must tell
  40            gcc that ebx,rbx is clobbered so that it doesn't try to use it as an intermediate
  41            register when storing rbx. gcc 4.3 didn't make this "mistake", but gcc 4.4
  42            does, at least on x86_64.
  43         */
  44
  45         asm volatile (
  46                 "pushq %%rbx\n"
  47                 "movq $1, %%rax\n"
  48                 "cpuid\n"
  49                 "movq %%rdx, %0\n"
  50                 "popq %%rbx\n"
  51                 : "=r" (cpuflags)
  52                 :
  53                 : "%rax", "%rbx", "%rcx", "%rdx"
  54                 );
  55
  56 #endif /* USE_X86_64_ASM */
  57
  58         if (cpuflags & (1<<25)) {
  59                 _flags = Flags (_flags | (HasSSE|HasFlushToZero));
  60         }
  61
  62         if (cpuflags & (1<<26)) {
  63                 _flags = Flags (_flags | HasSSE2);
  64         }
  65
  66         if (cpuflags & (1 << 24)) {
  67
  68                 char* fxbuf = 0;
  69
  70 #ifdef NO_POSIX_MEMALIGN
  71                 if ((fxbuf = (char *) malloc(512)) == 0)
  72 #else
  73                 if (posix_memalign ((void**)&fxbuf, 16, 512))
  74 #endif
  75                 {
  76                         error << _("cannot allocate 16 byte aligned buffer for h/w feature detection") << endmsg;
  77                 } else {
  78
  79                         memset (fxbuf, 0, 512);
  80
  81                         asm volatile (
  82                                 "fxsave (%0)"
  83                                 :
  84                                 : "r" (fxbuf)
  85                                 : "memory"
  86                                 );
  87
  88                         uint32_t mxcsr_mask = *((uint32_t*) &fxbuf[28]);
  89
  90                         /* if the mask is zero, set its default value (from intel specs) */
  91
  92                         if (mxcsr_mask == 0) {
  93                                 mxcsr_mask = 0xffbf;
  94                         }
  95
  96                         if (mxcsr_mask & (1<<6)) {
  97                                 _flags = Flags (_flags | HasDenormalsAreZero);
  98                         }
  99
 100                         free (fxbuf);
 101                 }
 102         }
 103 }
 104
 105 FPU::~FPU ()
 106 {
 107 }