libs/pbd/fpu.cc

   1 #include "libpbd-config.h"
   2
   3 #define _XOPEN_SOURCE 600
   4 #include <cstring> // for memset
   5 #include <cstdlib>
   6 #include <stdint.h>
   7
   8 #include "pbd/fpu.h"
   9 #include "pbd/error.h"
  10
  11 #include "i18n.h"
  12
  13 using namespace PBD;
  14 using namespace std;
  15
  16 FPU::FPU ()
  17 {
  18         unsigned long cpuflags = 0;
  19
  20         _flags = Flags (0);
  21
  22 #ifndef ARCH_X86
  23         return;
  24 #endif
  25
  26
  27 #ifndef USE_X86_64_ASM
  28         asm volatile (
  29                 "mov $1, %%eax\n"
  30                 "pushl %%ebx\n"
  31                 "cpuid\n"
  32                 "movl %%edx, %0\n"
  33                 "popl %%ebx\n"
  34                 : "=r" (cpuflags)
  35                 :
  36                 : "%eax", "%ecx", "%edx"
  37                 );
  38
  39 #else
  40
  41         /* asm notes: although we explicitly save&restore rbx, we must tell
  42            gcc that ebx,rbx is clobbered so that it doesn't try to use it as an intermediate
  43            register when storing rbx. gcc 4.3 didn't make this "mistake", but gcc 4.4
  44            does, at least on x86_64.
  45         */
  46
  47         asm volatile (
  48                 "pushq %%rbx\n"
  49                 "movq $1, %%rax\n"
  50                 "cpuid\n"
  51                 "movq %%rdx, %0\n"
  52                 "popq %%rbx\n"
  53                 : "=r" (cpuflags)
  54                 :
  55                 : "%rax", "%rbx", "%rcx", "%rdx"
  56                 );
  57
  58 #endif /* USE_X86_64_ASM */
  59
  60         if (cpuflags & (1<<25)) {
  61                 _flags = Flags (_flags | (HasSSE|HasFlushToZero));
  62         }
  63
  64         if (cpuflags & (1<<26)) {
  65                 _flags = Flags (_flags | HasSSE2);
  66         }
  67
  68         if (cpuflags & (1 << 24)) {
  69
  70                 char* fxbuf = 0;
  71
  72 #ifdef NO_POSIX_MEMALIGN
  73                 if ((fxbuf = (char *) malloc(512)) == 0)
  74 #else
  75                 if (posix_memalign ((void**)&fxbuf, 16, 512))
  76 #endif
  77                 {
  78                         error << _("cannot allocate 16 byte aligned buffer for h/w feature detection") << endmsg;
  79                 } else {
  80
  81                         memset (fxbuf, 0, 512);
  82
  83                         asm volatile (
  84                                 "fxsave (%0)"
  85                                 :
  86                                 : "r" (fxbuf)
  87                                 : "memory"
  88                                 );
  89
  90                         uint32_t mxcsr_mask = *((uint32_t*) &fxbuf[28]);
  91
  92                         /* if the mask is zero, set its default value (from intel specs) */
  93
  94                         if (mxcsr_mask == 0) {
  95                                 mxcsr_mask = 0xffbf;
  96                         }
  97
  98                         if (mxcsr_mask & (1<<6)) {
  99                                 _flags = Flags (_flags | HasDenormalsAreZero);
 100                         }
 101
 102                         free (fxbuf);
 103                 }
 104         }
 105 }
 106
 107 FPU::~FPU ()
 108 {
 109 }