esp-idf-bootloader: hw_esp32.c initial revision
[apeos.git] / src / hw_esp32.c
blob5020bd56c28cd8b3073ef71508d9eddea5cf1708
1 /* -*- Mode: C ; c-basic-offset: 2 -*- */
2 /*
3 * Copyright 2018 apeos contributors
5 * apeos Espressif esp-32 hardware interface functions
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <apeos/apeos.h>
22 #include <apeos/hw.h>
23 #include <rom/ets_sys.h> /* ets_printf */
24 #include <rom/spi_flash.h> /* g_rom_flashchip */
25 #include <soc/rtc_cntl_reg.h> /* RTC_CNTL_WDTCONFIG0_REG */
26 #include <soc/timer_group_reg.h> /* TIMG_WDTCONFIG0_REG */
27 #include <soc/cpu.h> /* esp_cpu_stall() */
28 #include <soc/efuse_reg.h> /* EFUSE_BLK0_RDATA3_REG */
30 static void esp32_disable_watchdog(void)
32 REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
33 REG_CLR_BIT(TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN);
36 void hw_init(void)
38 ets_printf("apeos booting\n");
39 esp32_disable_watchdog();
42 void hw_uninit(void)
44 esp_cpu_stall(0);
47 static
48 bool
49 esp32_package_get_info(
50 uint32_t efuse_blk0_rdata3_reg,
51 bool * embedded_flash_ptr,
52 const char ** package_description_ptr_ptr)
54 const char * package_description_ptr;
55 bool embedded_flash;
57 switch ((efuse_blk0_rdata3_reg & EFUSE_RD_CHIP_VER_PKG_M)
58 >> EFUSE_RD_CHIP_VER_PKG_S)
60 case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5:
61 package_description_ptr = "D2WDQ5";
62 embedded_flash = true;
63 break;
64 case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2:
65 package_description_ptr = "PICOD2";
66 embedded_flash = true;
67 break;
68 case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:
69 package_description_ptr = "PICOD4";
70 embedded_flash = true;
71 break;
72 default:
73 package_description_ptr = NULL;
76 if (package_description_ptr == NULL) /* unknown chip package */
78 *package_description_ptr_ptr = "unknown";
79 return false;
82 *package_description_ptr_ptr = package_description_ptr;
83 *embedded_flash_ptr = embedded_flash;
84 return true;
87 /* Print chip information */
88 void hw_info(void)
90 uint32_t reg;
91 bool known_package;
92 bool embedded_flash;
93 const char * package_description_ptr;
94 bool bluetooth;
95 uint32_t spiflash_chip_size;
97 reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
99 known_package = esp32_package_get_info(
100 reg,
101 &embedded_flash,
102 &package_description_ptr);
104 /* bluetooth is enabled if not found disabled in efuse */
105 bluetooth = (reg & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0;
107 /* size of SPI flash chip, in bytes */
108 spiflash_chip_size = g_rom_flashchip.chip_size;
110 ets_printf(
111 "ESP32 SoC");
113 if (known_package)
115 ets_printf(
116 ", %s package",
117 package_description_ptr);
120 ets_printf(
121 ", silicon revision %d", ((reg & EFUSE_RD_CHIP_VER_REV1_M) != 0) ? 1 : 0);
123 ets_printf(
124 ", %d CPU cores",
125 ((reg & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) ? 2 : 1);
127 ets_printf(
128 ", bluetooth %s",
129 bluetooth ? "enabled" : "disabled");
131 ets_printf(
132 ", %u byte %sflash\n",
133 (unsigned int)spiflash_chip_size,
134 known_package ? (embedded_flash ? "embedded " : "external ") : "");