components/bootloader_support/src/bootloader_clock.c

   1 // Copyright 2017 Espressif Systems (Shanghai) PTE LTD
   2 // Copyright 2018 apeos contributors
   3 //
   4 // Licensed under the Apache License, Version 2.0 (the "License");
   5 // you may not use this file except in compliance with the License.
   6 // You may obtain a copy of the License at
   7 //
   8 //     http://www.apache.org/licenses/LICENSE-2.0
   9 //
  10 // Unless required by applicable law or agreed to in writing, software
  11 // distributed under the License is distributed on an "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13 // See the License for the specific language governing permissions and
  14 // limitations under the License.
  15 #include "rom/uart.h"
  16 #include "rom/rtc.h"
  17 #include "soc/soc.h"
  18 #include "soc/rtc.h"
  19 #include "soc/dport_reg.h"
  20 #include "soc/efuse_reg.h"
  21 #include "soc/rtc_cntl_reg.h"
  22
  23 void bootloader_clock_configure()
  24 {
  25     // ROM bootloader may have put a lot of text into UART0 FIFO.
  26     // Wait for it to be printed.
  27     // This is not needed on power on reset, when ROM bootloader is running at
  28     // 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
  29     // and will be done with the bootloader much earlier than UART FIFO is empty.
  30     uart_tx_wait_idle(0);
  31
  32     /* Set CPU to 80MHz. Keep other clocks unmodified. */
  33     rtc_cpu_freq_t cpu_freq = RTC_CPU_FREQ_80M;
  34
  35 #if !defined(ESP_IDF_APEOS_BUILD)
  36     /* On ESP32 rev 0, switching to 80MHz if clock was previously set to
  37      * 240 MHz may cause the chip to lock up (see section 3.5 of the errata
  38      * document). For rev. 0, switch to 240 instead if it was chosen in
  39      * menuconfig.
  40      */
  41     uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
  42     if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 &&
  43             CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240) {
  44         cpu_freq = RTC_CPU_FREQ_240M;
  45     }
  46 #endif
  47
  48     rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
  49     clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
  50     clk_cfg.cpu_freq = cpu_freq;
  51     clk_cfg.slow_freq = rtc_clk_slow_freq_get();
  52     clk_cfg.fast_freq = rtc_clk_fast_freq_get();
  53     rtc_clk_init(clk_cfg);
  54     /* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable
  55      * it here. Usually it needs some time to start up, so we amortize at least
  56      * part of the start up time by enabling 32k XTAL early.
  57      * App startup code will wait until the oscillator has started up.
  58      */
  59 #ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
  60     if (!rtc_clk_32k_enabled()) {
  61         rtc_clk_32k_bootstrap();
  62     }
  63 #endif
  64 }