components/bootloader_support/src/bootloader_random.c

   1 // Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
   2 //
   3 // Licensed under the Apache License, Version 2.0 (the "License");
   4 // you may not use this file except in compliance with the License.
   5 // You may obtain a copy of the License at
   6 //
   7 //     http://www.apache.org/licenses/LICENSE-2.0
   8 //
   9 // Unless required by applicable law or agreed to in writing, software
  10 // distributed under the License is distributed on an "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12 // See the License for the specific language governing permissions and
  13 // limitations under the License.
  14 #include "bootloader_random.h"
  15 #include "soc/cpu.h"
  16 #include "soc/wdev_reg.h"
  17 #include "soc/rtc_cntl_reg.h"
  18 #include "soc/sens_reg.h"
  19 #include "soc/syscon_reg.h"
  20 #include "soc/dport_reg.h"
  21 #include "soc/i2s_reg.h"
  22 #include "esp_log.h"
  23
  24 #ifndef BOOTLOADER_BUILD
  25 #include "esp_system.h"
  26 #endif
  27
  28 void bootloader_fill_random(void *buffer, size_t length)
  29 {
  30     uint8_t *buffer_bytes = (uint8_t *)buffer;
  31     uint32_t random;
  32 #ifdef BOOTLOADER_BUILD
  33     uint32_t start, now;
  34 #endif
  35
  36     for (int i = 0; i < length; i++) {
  37         if (i == 0 || i % 4 == 0) { /* redundant check is for a compiler warning */
  38 #ifdef BOOTLOADER_BUILD
  39             /* in bootloader with ADC feeding HWRNG, we accumulate 1
  40                bit of entropy per 40 APB cycles (==80 CPU cycles.)
  41
  42                To avoid reading the entire RNG hardware state out
  43                as-is, we repeatedly read the RNG register and XOR all
  44                values.
  45             */
  46             random = REG_READ(WDEV_RND_REG);
  47             RSR(CCOUNT, start);
  48             do {
  49                 random ^= REG_READ(WDEV_RND_REG);
  50                 RSR(CCOUNT, now);
  51             } while(now - start < 80*32*2); /* extra factor of 2 is precautionary */
  52 #else
  53             random = esp_random();
  54 #endif
  55         }
  56
  57         buffer_bytes[i] = random >> ((i % 4) * 8);
  58     }
  59 }
  60
  61 void bootloader_random_enable(void)
  62 {
  63     /* Ensure the hardware RNG is enabled following a soft reset.  This should always be the case already (this clock is
  64        never disabled while the CPU is running), this is a "belts and braces" type check.
  65      */
  66     DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN);
  67
  68     /* Enable SAR ADC in test mode to feed ADC readings of the 1.1V
  69        reference via I2S into the RNG entropy input.
  70
  71        Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M)
  72        in early bootloader startup must have been made.
  73     */
  74     SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S);
  75     SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
  76     SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
  77
  78     DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
  79     CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
  80     CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
  81     // Test pattern configuration byte 0xAD:
  82     //--[7:4] channel_sel: 10-->en_test
  83     //--[3:2] bit_width  : 3-->12bit
  84     //--[1:0] atten      : 1-->3dB attenuation
  85     WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);
  86     WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
  87     WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
  88     WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD);
  89
  90     SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
  91     SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
  92     SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
  93     SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX);
  94     SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_S);
  95
  96     SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_RSTB_WAIT, 8, SYSCON_SARADC_RSTB_WAIT_S); /* was 1 */
  97     SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 10, SYSCON_SARADC_START_WAIT_S);
  98     SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, SYSCON_SARADC_WORK_MODE_S);
  99     SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL);
 100     CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL);
 101
 102     SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S);
 103
 104     SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG,SYSCON_SARADC_DATA_TO_I2S);
 105
 106     CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN);
 107     SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN);
 108     SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
 109     SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN);
 110     SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START);
 111 }
 112
 113 void bootloader_random_disable(void)
 114 {
 115     /* Disable i2s clock */
 116     DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
 117
 118
 119     /* Reset some i2s configuration (possibly redundant as we reset entire
 120        I2S peripheral further down). */
 121     CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN);
 122     CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN);
 123     CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN);
 124     CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
 125     CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START);
 126
 127     /* Restore SYSCON mode registers */
 128     CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
 129     CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
 130
 131     /* Restore SAR ADC mode */
 132     CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
 133     CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX
 134                         | SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
 135     SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
 136     SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S);
 137
 138     /* Reset i2s peripheral */
 139     DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
 140     DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
 141
 142     /* Disable pull supply voltage to SAR ADC */
 143     CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
 144     SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 0, RTC_CNTL_DTEST_RTC_S);
 145 }