2 ## Copyright (c) 2015 The WebM project authors. All Rights Reserved.
4 ## Use of this source code is governed by a BSD-style license
5 ## that can be found in the LICENSE file in the root of the source
6 ## tree. An additional intellectual property rights grant can be found
7 ## in the file PATENTS. All contributing project authors may
8 ## be found in the AUTHORS file in the root of the source tree.
11 DSP_SRCS-yes
+= vpx_dsp.mk
12 DSP_SRCS-yes
+= vpx_dsp_common.h
14 DSP_SRCS-
$(HAVE_MSA
) += mips
/macros_msa.h
17 DSP_SRCS-yes
+= prob.h
18 DSP_SRCS-yes
+= prob.c
20 ifeq ($(CONFIG_ENCODERS
),yes
)
21 DSP_SRCS-yes
+= bitwriter.h
22 DSP_SRCS-yes
+= bitwriter.c
23 DSP_SRCS-yes
+= bitwriter_buffer.c
24 DSP_SRCS-yes
+= bitwriter_buffer.h
25 DSP_SRCS-
$(CONFIG_INTERNAL_STATS
) += ssim.c
26 DSP_SRCS-
$(CONFIG_INTERNAL_STATS
) += ssim.h
27 DSP_SRCS-
$(CONFIG_INTERNAL_STATS
) += psnrhvs.c
28 DSP_SRCS-
$(CONFIG_INTERNAL_STATS
) += fastssim.c
31 ifeq ($(CONFIG_DECODERS
),yes
)
32 DSP_SRCS-yes
+= bitreader.h
33 DSP_SRCS-yes
+= bitreader.c
34 DSP_SRCS-yes
+= bitreader_buffer.c
35 DSP_SRCS-yes
+= bitreader_buffer.h
39 DSP_SRCS-yes
+= intrapred.c
41 ifeq ($(CONFIG_USE_X86INC
),yes
)
42 DSP_SRCS-
$(HAVE_MMX
) += x86
/loopfilter_mmx.asm
43 DSP_SRCS-
$(HAVE_SSE
) += x86
/intrapred_sse2.asm
44 DSP_SRCS-
$(HAVE_SSE2
) += x86
/intrapred_sse2.asm
45 DSP_SRCS-
$(HAVE_SSSE3
) += x86
/intrapred_ssse3.asm
46 DSP_SRCS-
$(HAVE_SSSE3
) += x86
/vpx_subpixel_8t_ssse3.asm
47 endif # CONFIG_USE_X86INC
49 ifeq ($(CONFIG_VP9_HIGHBITDEPTH
),yes
)
50 ifeq ($(CONFIG_USE_X86INC
),yes
)
51 DSP_SRCS-
$(HAVE_SSE
) += x86
/highbd_intrapred_sse2.asm
52 DSP_SRCS-
$(HAVE_SSE2
) += x86
/highbd_intrapred_sse2.asm
53 endif # CONFIG_USE_X86INC
54 endif # CONFIG_VP9_HIGHBITDEPTH
56 DSP_SRCS-
$(HAVE_NEON_ASM
) += arm
/intrapred_neon_asm
$(ASM
)
57 DSP_SRCS-
$(HAVE_NEON
) += arm
/intrapred_neon.c
58 DSP_SRCS-
$(HAVE_MSA
) += mips
/intrapred_msa.c
59 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/intrapred4_dspr2.c
60 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/intrapred8_dspr2.c
61 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/intrapred16_dspr2.c
63 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/common_dspr2.h
64 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/common_dspr2.c
66 # interpolation filters
67 DSP_SRCS-yes
+= vpx_convolve.c
68 DSP_SRCS-yes
+= vpx_convolve.h
69 DSP_SRCS-yes
+= vpx_filter.h
71 DSP_SRCS-
$(ARCH_X86
)$(ARCH_X86_64
) += x86
/convolve.h
72 DSP_SRCS-
$(ARCH_X86
)$(ARCH_X86_64
) += x86
/vpx_asm_stubs.c
73 DSP_SRCS-
$(HAVE_SSE2
) += x86
/vpx_subpixel_8t_sse2.asm
74 DSP_SRCS-
$(HAVE_SSE2
) += x86
/vpx_subpixel_bilinear_sse2.asm
75 DSP_SRCS-
$(HAVE_SSSE3
) += x86
/vpx_subpixel_8t_ssse3.asm
76 DSP_SRCS-
$(HAVE_SSSE3
) += x86
/vpx_subpixel_bilinear_ssse3.asm
77 DSP_SRCS-
$(HAVE_AVX2
) += x86
/vpx_subpixel_8t_intrin_avx2.c
78 DSP_SRCS-
$(HAVE_SSSE3
) += x86
/vpx_subpixel_8t_intrin_ssse3.c
79 ifeq ($(CONFIG_VP9_HIGHBITDEPTH
),yes
)
80 DSP_SRCS-
$(HAVE_SSE2
) += x86
/vpx_high_subpixel_8t_sse2.asm
81 DSP_SRCS-
$(HAVE_SSE2
) += x86
/vpx_high_subpixel_bilinear_sse2.asm
83 ifeq ($(CONFIG_USE_X86INC
),yes
)
84 DSP_SRCS-
$(HAVE_SSE2
) += x86
/vpx_convolve_copy_sse2.asm
87 ifeq ($(HAVE_NEON_ASM
),yes
)
88 DSP_SRCS-yes
+= arm
/vpx_convolve_copy_neon_asm
$(ASM
)
89 DSP_SRCS-yes
+= arm
/vpx_convolve8_avg_neon_asm
$(ASM
)
90 DSP_SRCS-yes
+= arm
/vpx_convolve8_neon_asm
$(ASM
)
91 DSP_SRCS-yes
+= arm
/vpx_convolve_avg_neon_asm
$(ASM
)
92 DSP_SRCS-yes
+= arm
/vpx_convolve_neon.c
94 ifeq ($(HAVE_NEON
),yes
)
95 DSP_SRCS-yes
+= arm
/vpx_convolve_copy_neon.c
96 DSP_SRCS-yes
+= arm
/vpx_convolve8_avg_neon.c
97 DSP_SRCS-yes
+= arm
/vpx_convolve8_neon.c
98 DSP_SRCS-yes
+= arm
/vpx_convolve_avg_neon.c
99 DSP_SRCS-yes
+= arm
/vpx_convolve_neon.c
101 endif # HAVE_NEON_ASM
104 DSP_SRCS-
$(HAVE_MSA
) += mips
/vpx_convolve8_avg_horiz_msa.c
105 DSP_SRCS-
$(HAVE_MSA
) += mips
/vpx_convolve8_avg_msa.c
106 DSP_SRCS-
$(HAVE_MSA
) += mips
/vpx_convolve8_avg_vert_msa.c
107 DSP_SRCS-
$(HAVE_MSA
) += mips
/vpx_convolve8_horiz_msa.c
108 DSP_SRCS-
$(HAVE_MSA
) += mips
/vpx_convolve8_msa.c
109 DSP_SRCS-
$(HAVE_MSA
) += mips
/vpx_convolve8_vert_msa.c
110 DSP_SRCS-
$(HAVE_MSA
) += mips
/vpx_convolve_avg_msa.c
111 DSP_SRCS-
$(HAVE_MSA
) += mips
/vpx_convolve_copy_msa.c
112 DSP_SRCS-
$(HAVE_MSA
) += mips
/vpx_convolve_msa.h
115 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/convolve_common_dspr2.h
116 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/convolve2_avg_dspr2.c
117 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/convolve2_avg_horiz_dspr2.c
118 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/convolve2_dspr2.c
119 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/convolve2_horiz_dspr2.c
120 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/convolve2_vert_dspr2.c
121 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/convolve8_avg_dspr2.c
122 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/convolve8_avg_horiz_dspr2.c
123 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/convolve8_dspr2.c
124 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/convolve8_horiz_dspr2.c
125 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/convolve8_vert_dspr2.c
128 DSP_SRCS-yes
+= loopfilter.c
130 DSP_SRCS-
$(ARCH_X86
)$(ARCH_X86_64
) += x86
/loopfilter_sse2.c
131 DSP_SRCS-
$(HAVE_AVX2
) += x86
/loopfilter_avx2.c
133 DSP_SRCS-
$(HAVE_NEON
) += arm
/loopfilter_neon.c
134 ifeq ($(HAVE_NEON_ASM
),yes
)
135 DSP_SRCS-yes
+= arm
/loopfilter_mb_neon
$(ASM
)
136 DSP_SRCS-yes
+= arm
/loopfilter_16_neon
$(ASM
)
137 DSP_SRCS-yes
+= arm
/loopfilter_8_neon
$(ASM
)
138 DSP_SRCS-yes
+= arm
/loopfilter_4_neon
$(ASM
)
140 ifeq ($(HAVE_NEON
),yes
)
141 DSP_SRCS-yes
+= arm
/loopfilter_16_neon.c
142 DSP_SRCS-yes
+= arm
/loopfilter_8_neon.c
143 DSP_SRCS-yes
+= arm
/loopfilter_4_neon.c
145 endif # HAVE_NEON_ASM
147 DSP_SRCS-
$(HAVE_MSA
) += mips
/loopfilter_msa.h
148 DSP_SRCS-
$(HAVE_MSA
) += mips
/loopfilter_16_msa.c
149 DSP_SRCS-
$(HAVE_MSA
) += mips
/loopfilter_8_msa.c
150 DSP_SRCS-
$(HAVE_MSA
) += mips
/loopfilter_4_msa.c
151 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/loopfilter_filters_dspr2.h
152 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/loopfilter_filters_dspr2.c
153 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/loopfilter_macros_dspr2.h
154 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/loopfilter_masks_dspr2.h
155 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/loopfilter_mb_dspr2.c
156 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/loopfilter_mb_horiz_dspr2.c
157 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/loopfilter_mb_vert_dspr2.c
159 ifeq ($(CONFIG_VP9_HIGHBITDEPTH
),yes
)
160 DSP_SRCS-
$(HAVE_SSE2
) += x86
/highbd_loopfilter_sse2.c
161 endif # CONFIG_VP9_HIGHBITDEPTH
163 DSP_SRCS-yes
+= txfm_common.h
164 DSP_SRCS-
$(HAVE_SSE2
) += x86
/txfm_common_sse2.h
165 DSP_SRCS-
$(HAVE_MSA
) += mips
/txfm_macros_msa.h
167 ifneq ($(filter yes
,$(CONFIG_VP9_ENCODER
) $(CONFIG_VP10_ENCODER
)),)
168 DSP_SRCS-yes
+= fwd_txfm.c
169 DSP_SRCS-yes
+= fwd_txfm.h
170 DSP_SRCS-
$(HAVE_SSE2
) += x86
/fwd_txfm_sse2.h
171 DSP_SRCS-
$(HAVE_SSE2
) += x86
/fwd_txfm_sse2.c
172 DSP_SRCS-
$(HAVE_SSE2
) += x86
/fwd_txfm_impl_sse2.h
173 DSP_SRCS-
$(HAVE_SSE2
) += x86
/fwd_dct32x32_impl_sse2.h
174 ifeq ($(ARCH_X86_64
),yes
)
175 ifeq ($(CONFIG_USE_X86INC
),yes
)
176 DSP_SRCS-
$(HAVE_SSSE3
) += x86
/fwd_txfm_ssse3_x86_64.asm
179 DSP_SRCS-
$(HAVE_AVX2
) += x86
/fwd_txfm_avx2.c
180 DSP_SRCS-
$(HAVE_AVX2
) += x86
/fwd_dct32x32_impl_avx2.h
181 DSP_SRCS-
$(HAVE_NEON
) += arm
/fwd_txfm_neon.c
182 DSP_SRCS-
$(HAVE_MSA
) += mips
/fwd_txfm_msa.h
183 DSP_SRCS-
$(HAVE_MSA
) += mips
/fwd_txfm_msa.c
184 DSP_SRCS-
$(HAVE_MSA
) += mips
/fwd_dct32x32_msa.c
185 endif # CONFIG_VP9_ENCODER || CONFIG_VP10_ENCODER
188 ifneq ($(filter yes
,$(CONFIG_VP9
) $(CONFIG_VP10
)),)
189 DSP_SRCS-yes
+= inv_txfm.h
190 DSP_SRCS-yes
+= inv_txfm.c
191 DSP_SRCS-
$(HAVE_SSE2
) += x86
/inv_txfm_sse2.h
192 DSP_SRCS-
$(HAVE_SSE2
) += x86
/inv_txfm_sse2.c
193 ifeq ($(CONFIG_USE_X86INC
),yes
)
194 DSP_SRCS-
$(HAVE_SSE2
) += x86
/inv_wht_sse2.asm
195 ifeq ($(ARCH_X86_64
),yes
)
196 DSP_SRCS-
$(HAVE_SSSE3
) += x86
/inv_txfm_ssse3_x86_64.asm
198 endif # CONFIG_USE_X86INC
200 ifeq ($(HAVE_NEON_ASM
),yes
)
201 DSP_SRCS-yes
+= arm
/save_reg_neon
$(ASM
)
202 DSP_SRCS-yes
+= arm
/idct4x4_1_add_neon
$(ASM
)
203 DSP_SRCS-yes
+= arm
/idct4x4_add_neon
$(ASM
)
204 DSP_SRCS-yes
+= arm
/idct8x8_1_add_neon
$(ASM
)
205 DSP_SRCS-yes
+= arm
/idct8x8_add_neon
$(ASM
)
206 DSP_SRCS-yes
+= arm
/idct16x16_1_add_neon
$(ASM
)
207 DSP_SRCS-yes
+= arm
/idct16x16_add_neon
$(ASM
)
208 DSP_SRCS-yes
+= arm
/idct32x32_1_add_neon
$(ASM
)
209 DSP_SRCS-yes
+= arm
/idct32x32_add_neon
$(ASM
)
211 ifeq ($(HAVE_NEON
),yes
)
212 DSP_SRCS-yes
+= arm
/idct4x4_1_add_neon.c
213 DSP_SRCS-yes
+= arm
/idct4x4_add_neon.c
214 DSP_SRCS-yes
+= arm
/idct8x8_1_add_neon.c
215 DSP_SRCS-yes
+= arm
/idct8x8_add_neon.c
216 DSP_SRCS-yes
+= arm
/idct16x16_1_add_neon.c
217 DSP_SRCS-yes
+= arm
/idct16x16_add_neon.c
218 DSP_SRCS-yes
+= arm
/idct32x32_1_add_neon.c
219 DSP_SRCS-yes
+= arm
/idct32x32_add_neon.c
221 endif # HAVE_NEON_ASM
222 DSP_SRCS-
$(HAVE_NEON
) += arm
/idct16x16_neon.c
224 DSP_SRCS-
$(HAVE_MSA
) += mips
/inv_txfm_msa.h
225 DSP_SRCS-
$(HAVE_MSA
) += mips
/idct4x4_msa.c
226 DSP_SRCS-
$(HAVE_MSA
) += mips
/idct8x8_msa.c
227 DSP_SRCS-
$(HAVE_MSA
) += mips
/idct16x16_msa.c
228 DSP_SRCS-
$(HAVE_MSA
) += mips
/idct32x32_msa.c
230 ifneq ($(CONFIG_VP9_HIGHBITDEPTH
),yes
)
231 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/inv_txfm_dspr2.h
232 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/itrans4_dspr2.c
233 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/itrans8_dspr2.c
234 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/itrans16_dspr2.c
235 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/itrans32_dspr2.c
236 DSP_SRCS-
$(HAVE_DSPR2
) += mips
/itrans32_cols_dspr2.c
237 endif # CONFIG_VP9_HIGHBITDEPTH
238 endif # CONFIG_VP9 || CONFIG_VP10
241 ifneq ($(filter yes
, $(CONFIG_VP9_ENCODER
) $(CONFIG_VP10_ENCODER
)),)
242 DSP_SRCS-yes
+= quantize.c
243 DSP_SRCS-yes
+= quantize.h
245 DSP_SRCS-
$(HAVE_SSE2
) += x86
/quantize_sse2.c
246 ifeq ($(CONFIG_VP9_HIGHBITDEPTH
),yes
)
247 DSP_SRCS-
$(HAVE_SSE2
) += x86
/highbd_quantize_intrin_sse2.c
249 ifeq ($(ARCH_X86_64
),yes
)
250 ifeq ($(CONFIG_USE_X86INC
),yes
)
251 DSP_SRCS-
$(HAVE_SSSE3
) += x86
/quantize_ssse3_x86_64.asm
252 DSP_SRCS-
$(HAVE_AVX
) += x86
/quantize_avx_x86_64.asm
257 DSP_SRCS-yes
+= avg.c
258 DSP_SRCS-
$(HAVE_SSE2
) += x86
/avg_intrin_sse2.c
259 DSP_SRCS-
$(HAVE_NEON
) += arm
/avg_neon.c
260 DSP_SRCS-
$(HAVE_MSA
) += mips
/avg_msa.c
261 ifeq ($(ARCH_X86_64
),yes
)
262 ifeq ($(CONFIG_USE_X86INC
),yes
)
263 DSP_SRCS-
$(HAVE_SSSE3
) += x86
/avg_ssse3_x86_64.asm
267 endif # CONFIG_VP9_ENCODER || CONFIG_VP10_ENCODER
269 ifeq ($(CONFIG_ENCODERS
),yes
)
270 DSP_SRCS-yes
+= sad.c
271 DSP_SRCS-yes
+= subtract.c
273 DSP_SRCS-
$(HAVE_MEDIA
) += arm
/sad_media
$(ASM
)
274 DSP_SRCS-
$(HAVE_NEON
) += arm
/sad4d_neon.c
275 DSP_SRCS-
$(HAVE_NEON
) += arm
/sad_neon.c
276 DSP_SRCS-
$(HAVE_NEON
) += arm
/subtract_neon.c
278 DSP_SRCS-
$(HAVE_MSA
) += mips
/sad_msa.c
279 DSP_SRCS-
$(HAVE_MSA
) += mips
/subtract_msa.c
281 DSP_SRCS-
$(HAVE_MMX
) += x86
/sad_mmx.asm
282 DSP_SRCS-
$(HAVE_SSE3
) += x86
/sad_sse3.asm
283 DSP_SRCS-
$(HAVE_SSSE3
) += x86
/sad_ssse3.asm
284 DSP_SRCS-
$(HAVE_SSE4_1
) += x86
/sad_sse4.asm
285 DSP_SRCS-
$(HAVE_AVX2
) += x86
/sad4d_avx2.c
286 DSP_SRCS-
$(HAVE_AVX2
) += x86
/sad_avx2.c
288 ifeq ($(CONFIG_USE_X86INC
),yes
)
289 DSP_SRCS-
$(HAVE_SSE
) += x86
/sad4d_sse2.asm
290 DSP_SRCS-
$(HAVE_SSE
) += x86
/sad_sse2.asm
291 DSP_SRCS-
$(HAVE_SSE2
) += x86
/sad4d_sse2.asm
292 DSP_SRCS-
$(HAVE_SSE2
) += x86
/sad_sse2.asm
293 DSP_SRCS-
$(HAVE_SSE2
) += x86
/subtract_sse2.asm
295 ifeq ($(CONFIG_VP9_HIGHBITDEPTH
),yes
)
296 DSP_SRCS-
$(HAVE_SSE2
) += x86
/highbd_sad4d_sse2.asm
297 DSP_SRCS-
$(HAVE_SSE2
) += x86
/highbd_sad_sse2.asm
298 endif # CONFIG_VP9_HIGHBITDEPTH
299 endif # CONFIG_USE_X86INC
301 endif # CONFIG_ENCODERS
303 ifneq ($(filter yes
,$(CONFIG_ENCODERS
) $(CONFIG_POSTPROC
) $(CONFIG_VP9_POSTPROC
)),)
304 DSP_SRCS-yes
+= variance.c
305 DSP_SRCS-yes
+= variance.h
307 DSP_SRCS-
$(HAVE_MEDIA
) += arm
/bilinear_filter_media
$(ASM
)
308 DSP_SRCS-
$(HAVE_MEDIA
) += arm
/subpel_variance_media.c
309 DSP_SRCS-
$(HAVE_MEDIA
) += arm
/variance_halfpixvar16x16_h_media
$(ASM
)
310 DSP_SRCS-
$(HAVE_MEDIA
) += arm
/variance_halfpixvar16x16_hv_media
$(ASM
)
311 DSP_SRCS-
$(HAVE_MEDIA
) += arm
/variance_halfpixvar16x16_v_media
$(ASM
)
312 DSP_SRCS-
$(HAVE_MEDIA
) += arm
/variance_media
$(ASM
)
313 DSP_SRCS-
$(HAVE_NEON
) += arm
/subpel_variance_neon.c
314 DSP_SRCS-
$(HAVE_NEON
) += arm
/variance_neon.c
316 DSP_SRCS-
$(HAVE_MSA
) += mips
/variance_msa.c
317 DSP_SRCS-
$(HAVE_MSA
) += mips
/sub_pixel_variance_msa.c
319 DSP_SRCS-
$(HAVE_MMX
) += x86
/variance_mmx.c
320 DSP_SRCS-
$(HAVE_MMX
) += x86
/variance_impl_mmx.asm
321 DSP_SRCS-
$(HAVE_SSE
) += x86
/variance_sse2.c
322 DSP_SRCS-
$(HAVE_SSE2
) += x86
/variance_sse2.c
# Contains SSE2 and SSSE3
323 DSP_SRCS-
$(HAVE_SSE2
) += x86
/halfpix_variance_sse2.c
324 DSP_SRCS-
$(HAVE_SSE2
) += x86
/halfpix_variance_impl_sse2.asm
325 DSP_SRCS-
$(HAVE_AVX2
) += x86
/variance_avx2.c
326 DSP_SRCS-
$(HAVE_AVX2
) += x86
/variance_impl_avx2.c
328 ifeq ($(ARCH_X86_64
),yes
)
329 DSP_SRCS-
$(HAVE_SSE2
) += x86
/ssim_opt_x86_64.asm
332 ifeq ($(CONFIG_USE_X86INC
),yes
)
333 DSP_SRCS-
$(HAVE_SSE
) += x86
/subpel_variance_sse2.asm
334 DSP_SRCS-
$(HAVE_SSE2
) += x86
/subpel_variance_sse2.asm
# Contains SSE2 and SSSE3
335 endif # CONFIG_USE_X86INC
337 ifeq ($(CONFIG_VP9_HIGHBITDEPTH
),yes
)
338 DSP_SRCS-
$(HAVE_SSE2
) += x86
/highbd_variance_sse2.c
339 DSP_SRCS-
$(HAVE_SSE2
) += x86
/highbd_variance_impl_sse2.asm
340 ifeq ($(CONFIG_USE_X86INC
),yes
)
341 DSP_SRCS-
$(HAVE_SSE2
) += x86
/highbd_subpel_variance_impl_sse2.asm
342 endif # CONFIG_USE_X86INC
343 endif # CONFIG_VP9_HIGHBITDEPTH
344 endif # CONFIG_ENCODERS || CONFIG_POSTPROC || CONFIG_VP9_POSTPROC
346 DSP_SRCS-no
+= $(DSP_SRCS_REMOVE-yes
)
348 DSP_SRCS-yes
+= vpx_dsp_rtcd.c
349 DSP_SRCS-yes
+= vpx_dsp_rtcd_defs.pl
351 $(eval
$(call rtcd_h_template
,vpx_dsp_rtcd
,vpx_dsp
/vpx_dsp_rtcd_defs.pl
))
