Adding some more judges, here and there.

[andmenj-acm.git] / NEERC / yield / yield_gk.dpr

var\r
    a, b: longint;\r
begin\r
    assign(input, 'yield.in');  reset(input);\r
    assign(output, 'yield.out'); rewrite(output);\r
\r
    read(a, b);\r
    writeln(a + b);\r
\r
    close(input);\r
    close(output);\r
end.