firmware/target/arm/tms320dm320/spi-dm320.c

   1 /*
   2  * SPI interface driver for the DM320 SoC
   3  *
   4  * Copyright (C) 2007 shirour <mrobefan@gmail.com>
   5  * Copyright (C) 2007 Catalin Patulea <cat@vv.carleton.ca>
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the License, or (at your
  10  *  option) any later version.
  11  *
  12  *  THIS  SOFTWARE  IS PROVIDED   ``AS IS'' AND   ANY EXPRESS OR IMPLIED
  13  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  14  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  15  *  NO EVENT  SHALL   THE AUTHOR  BE  LIABLE FOR ANY   DIRECT, INDIRECT,
  16  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS OR SERVICES; LOSS OF
  18  *  USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  20  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  *  You should have received a copy of the  GNU General Public License along
  24  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  25  *  675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27 #include "kernel.h"
  28 #include "system.h"
  29 #include "spi.h"
  30
  31 #define GIO_TS_ENABLE  (1<<2)
  32 #define GIO_RTC_ENABLE (1<<12)
  33
  34 struct spinlock spi_lock;
  35
  36 struct SPI_info {
  37     volatile unsigned short *setreg;
  38     volatile unsigned short *clrreg;
  39     int bit;
  40 };
  41 #define reg(a) ((volatile unsigned short *)(PHY_IO_BASE+a))
  42 struct SPI_info spi_targets[] =
  43 {
  44     [SPI_target_TSC2100]   = { reg(0x0594), reg(0x058E), GIO_TS_ENABLE },
  45     [SPI_target_RX5X348AB] = { reg(0x058C), reg(0x0592), GIO_RTC_ENABLE },
  46 };
  47
  48 static void spi_disable_all_targets(void)
  49 {
  50     int i;
  51     for(i=0;i<SPI_MAX_TARGETS;i++)
  52     {
  53         *spi_targets[i].clrreg = spi_targets[i].bit;
  54     }
  55 }
  56
  57 int spi_block_transfer(enum SPI_target target,
  58                        const uint8_t *tx_bytes, unsigned int tx_size,
  59                              uint8_t *rx_bytes, unsigned int rx_size)
  60 {
  61     spinlock_lock(&spi_lock);
  62     /* Activate the slave select pin */
  63     *spi_targets[target].setreg = spi_targets[target].bit;
  64
  65     while (tx_size--)
  66     {
  67         /* Send one byte */
  68         IO_SERIAL0_TX_DATA = *tx_bytes++;
  69
  70         /* Wait until transfer finished */
  71         while (IO_SERIAL0_RX_DATA & 0x100);
  72     }
  73
  74     while (rx_size--)
  75     {
  76         /* Make the clock tick */
  77         IO_SERIAL0_TX_DATA = 0;
  78
  79         /* Wait until transfer finished */
  80         unsigned short data;
  81         while ((data = IO_SERIAL0_RX_DATA) & 0x100);
  82
  83         *rx_bytes++ = data & 0xff;
  84     }
  85
  86     *spi_targets[target].clrreg = spi_targets[target].bit;
  87
  88     spinlock_unlock(&spi_lock);
  89     return 0;
  90 }
  91
  92 void spi_init(void)
  93 {
  94     spinlock_init(&spi_lock);
  95     /* Set SCLK idle level = 1 */
  96     IO_SERIAL0_MODE &= ~(1<<10);
  97     /* Enable TX */
  98     IO_SERIAL0_TX_ENABLE = 0x0001;
  99
 100     /* Set GIO 18 to output for touch screen slave enable */
 101     IO_GIO_DIR1 &= ~GIO_TS_ENABLE;
 102     /* Set GIO 12 to output for rtc slave enable */
 103     IO_GIO_DIR0 &= ~GIO_RTC_ENABLE;
 104
 105     spi_disable_all_targets(); /* make sure only one is ever enabled at a time */
 106 }