firmware/target/sh/system-target.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by Jens Arnold
  11  * Based on the work of Alan Korr and others
  12  *
  13  * All files in this archive are subject to the GNU General Public License.
  14  * See the file COPYING in the source tree root for full license agreement.
  15  *
  16  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  17  * KIND, either express or implied.
  18  *
  19  ****************************************************************************/
  20 #ifndef SYSTEM_TARGET_H
  21 #define SYSTEM_TARGET_H
  22
  23 #define or_b(mask, address) \
  24   asm                                       \
  25     ("or.b %0,@(r0,gbr)"                    \
  26      :                                      \
  27      : /* %0 */ I_CONSTRAINT((char)(mask)), \
  28        /* %1 */ "z"(address-GBR))
  29
  30 #define and_b(mask, address) \
  31   asm                                       \
  32     ("and.b %0,@(r0,gbr)"                   \
  33      :                                      \
  34      : /* %0 */ I_CONSTRAINT((char)(mask)), \
  35        /* %1 */ "z"(address-GBR))
  36
  37 #define xor_b(mask, address) \
  38   asm                                        \
  39     ("xor.b %0,@(r0,gbr)"                    \
  40      :                                       \
  41      : /* %0 */ I_CONSTRAINT((char)(mask)),  \
  42        /* %1 */ "z"(address-GBR))
  43
  44
  45 /****************************************************************************
  46  * Interrupt level setting
  47  * The level is left shifted 4 bits
  48  ****************************************************************************/
  49 #define HIGHEST_IRQ_LEVEL (15<<4)
  50
  51 static inline int set_irq_level(int level)
  52 {
  53     int i;
  54     /* Read the old level and set the new one */
  55     asm volatile ("stc sr, %0" : "=r" (i));
  56     asm volatile ("ldc %0, sr" : : "r" (level));
  57     return i;
  58 }
  59
  60 static inline uint16_t swap16(uint16_t value)
  61   /*
  62     result[15..8] = value[ 7..0];
  63     result[ 7..0] = value[15..8];
  64   */
  65 {
  66     uint16_t result;
  67     asm volatile ("swap.b\t%1,%0" : "=r"(result) : "r"(value));
  68     return result;
  69 }
  70
  71 static inline uint32_t SWAW32(uint32_t value)
  72   /*
  73     result[31..16] = value[15.. 0];
  74     result[15.. 0] = value[31..16];
  75   */
  76 {
  77     uint32_t result;
  78     asm volatile ("swap.w\t%1,%0" : "=r"(result) : "r"(value));
  79     return result;
  80 }
  81
  82 static inline uint32_t swap32(uint32_t value)
  83   /*
  84     result[31..24] = value[ 7.. 0];
  85     result[23..16] = value[15.. 8];
  86     result[15.. 8] = value[23..16];
  87     result[ 7.. 0] = value[31..24];
  88   */
  89 {
  90     asm volatile ("swap.b\t%0,%0\n"
  91                   "swap.w\t%0,%0\n"
  92                   "swap.b\t%0,%0\n" : "+r"(value));
  93     return value;
  94 }
  95
  96 static inline uint32_t swap_odd_even32(uint32_t value)
  97 {
  98     /*
  99       result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
 100       result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
 101     */
 102     asm volatile ("swap.b\t%0,%0\n"
 103                   "swap.w\t%0,%0\n"
 104                   "swap.b\t%0,%0\n"
 105                   "swap.w\t%0,%0\n" : "+r"(value));
 106     return value;
 107 }
 108
 109 #define invalidate_icache()
 110
 111 #endif /* SYSTEM_TARGET_H */