firmware/export/pp5002.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2004 by Thom Johansen
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 #ifndef __PP5002_H__
  20 #define __PP5002_H__
  21
  22 /* Much info gleaned and/or copied from the iPodLinux project. */
  23 #define DRAM_START       0x28000000
  24
  25 /* LCD bridge */
  26 #define LCD1_BASE        0xc0001000
  27
  28 #define LCD1_CONTROL     (*(volatile unsigned long *)(0xc0001000))
  29 #define LCD1_CMD         (*(volatile unsigned long *)(0xc0001008))
  30 #define LCD1_DATA        (*(volatile unsigned long *)(0xc0001010))
  31
  32 #define LCD1_BUSY_MASK   0x8000
  33
  34 /* I2S controller */
  35 #define IISCONFIG        (*(volatile unsigned long *)(0xc0002500))
  36 #define IISFIFO_CFG      (*(volatile unsigned long *)(0xc000251c))
  37 #define IISFIFO_WR       (*(volatile unsigned long *)(0xc0002540))
  38 #define IISFIFO_RD       (*(volatile unsigned long *)(0xc0002580))
  39
  40 /* IISCONFIG bits: */
  41 #define IIS_TXFIFOEN      (1 << 2)
  42 #define IIS_TX_FREE_MASK  (0xf << 23)
  43 #define IIS_TX_FREE_COUNT ((IISFIFO_CFG & IIS_TX_FREE_MASK) >> 23)
  44
  45 /* IISFIFO_CFG bits: */
  46 #define IIS_IRQTX_REG    IISFIFO_CFG
  47 #define IIS_IRQTX        (1 << 9)
  48
  49 #define IDE_BASE         0xc0003000
  50
  51 #define IDE_CFG_STATUS   (*(volatile unsigned long *)(0xc0003024))
  52
  53 #define USB_BASE         0xc0005000
  54
  55 #define I2C_BASE         0xc0008000
  56
  57 /* Processor ID */
  58 #define PROCESSOR_ID     (*(volatile unsigned long *)(0xc4000000))
  59
  60 #define PROC_ID_CPU      0x55
  61 #define PROC_ID_COP      0xaa
  62
  63 #define GPIOA_ENABLE     (*(volatile unsigned char *)(0xcf000000))
  64 #define GPIOB_ENABLE     (*(volatile unsigned char *)(0xcf000004))
  65 #define GPIOC_ENABLE     (*(volatile unsigned char *)(0xcf000008))
  66 #define GPIOD_ENABLE     (*(volatile unsigned char *)(0xcf00000c))
  67 #define GPIOA_OUTPUT_EN  (*(volatile unsigned char *)(0xcf000010))
  68 #define GPIOB_OUTPUT_EN  (*(volatile unsigned char *)(0xcf000014))
  69 #define GPIOC_OUTPUT_EN  (*(volatile unsigned char *)(0xcf000018))
  70 #define GPIOD_OUTPUT_EN  (*(volatile unsigned char *)(0xcf00001c))
  71 #define GPIOA_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000020))
  72 #define GPIOB_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000024))
  73 #define GPIOC_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000028))
  74 #define GPIOD_OUTPUT_VAL (*(volatile unsigned char *)(0xcf00002c))
  75 #define GPIOA_INPUT_VAL  (*(volatile unsigned char *)(0xcf000030))
  76 #define GPIOB_INPUT_VAL  (*(volatile unsigned char *)(0xcf000034))
  77 #define GPIOC_INPUT_VAL  (*(volatile unsigned char *)(0xcf000038))
  78 #define GPIOD_INPUT_VAL  (*(volatile unsigned char *)(0xcf00003c))
  79 #define GPIOA_INT_STAT   (*(volatile unsigned char *)(0xcf000040))
  80 #define GPIOB_INT_STAT   (*(volatile unsigned char *)(0xcf000044))
  81 #define GPIOC_INT_STAT   (*(volatile unsigned char *)(0xcf000048))
  82 #define GPIOD_INT_STAT   (*(volatile unsigned char *)(0xcf00004c))
  83 #define GPIOA_INT_EN     (*(volatile unsigned char *)(0xcf000050))
  84 #define GPIOB_INT_EN     (*(volatile unsigned char *)(0xcf000054))
  85 #define GPIOC_INT_EN     (*(volatile unsigned char *)(0xcf000058))
  86 #define GPIOD_INT_EN     (*(volatile unsigned char *)(0xcf00005c))
  87 #define GPIOA_INT_LEV    (*(volatile unsigned char *)(0xcf000060))
  88 #define GPIOB_INT_LEV    (*(volatile unsigned char *)(0xcf000064))
  89 #define GPIOC_INT_LEV    (*(volatile unsigned char *)(0xcf000068))
  90 #define GPIOD_INT_LEV    (*(volatile unsigned char *)(0xcf00006c))
  91 #define GPIOA_INT_CLR    (*(volatile unsigned char *)(0xcf000070))
  92 #define GPIOB_INT_CLR    (*(volatile unsigned char *)(0xcf000074))
  93 #define GPIOC_INT_CLR    (*(volatile unsigned char *)(0xcf000078))
  94 #define GPIOD_INT_CLR    (*(volatile unsigned char *)(0xcf00007c))
  95
  96 #define CPU_INT_STAT     (*(volatile unsigned long *)(0xcf001000))
  97 #define COP_INT_STAT     (*(volatile unsigned long *)(0xcf001004))
  98 #define CPU_FIQ_STAT     (*(volatile unsigned long *)(0xcf001008))
  99 #define COP_FIQ_STAT     (*(volatile unsigned long *)(0xcf00100c))
 100
 101 #define INT_STAT         (*(volatile unsigned long *)(0xcf001010))
 102 #define INT_FORCED_STAT  (*(volatile unsigned long *)(0xcf001014))
 103 #define INT_FORCED_SET   (*(volatile unsigned long *)(0xcf001018))
 104 #define INT_FORCED_CLR   (*(volatile unsigned long *)(0xcf00101c))
 105
 106 #define CPU_INT_EN_STAT  (*(volatile unsigned long *)(0xcf001020))
 107 #define CPU_INT_EN       (*(volatile unsigned long *)(0xcf001024))
 108 #define CPU_INT_CLR      (*(volatile unsigned long *)(0xcf001028))
 109 #define CPU_INT_PRIORITY (*(volatile unsigned long *)(0xcf00102c))
 110
 111 #define COP_INT_EN_STAT  (*(volatile unsigned long *)(0xcf001030))
 112 #define COP_INT_EN       (*(volatile unsigned long *)(0xcf001034))
 113 #define COP_INT_CLR      (*(volatile unsigned long *)(0xcf001038))
 114 #define COP_INT_PRIORITY (*(volatile unsigned long *)(0xcf00103c))
 115
 116 #define IDE_IRQ          1
 117 #define SER0_IRQ         4
 118 #define I2S_IRQ          5
 119 #define SER1_IRQ         7
 120 #define TIMER1_IRQ      11
 121 #define TIMER2_IRQ      12
 122 #define GPIO_IRQ        14
 123 #define DMA_OUT_IRQ     30
 124 #define DMA_IN_IRQ      31
 125
 126 #define IDE_MASK         (1 << IDE_IRQ)
 127 #define SER0_MASK        (1 << SER0_IRQ)
 128 #define I2S_MASK         (1 << I2S_IRQ)
 129 #define SER1_MASK        (1 << SER1_IRQ)
 130 #define TIMER1_MASK      (1 << TIMER1_IRQ)
 131 #define TIMER2_MASK      (1 << TIMER2_IRQ)
 132 #define GPIO_MASK        (1 << GPIO_IRQ)
 133 #define DMA_OUT_MASK     (1 << DMA_OUT_IRQ)
 134 #define DMA_IN_MASK      (1 << DMA_IN_IRQ)
 135
 136 /* Yes, there is I2S_MASK but this cleans up the pcm code */
 137 #define IIS_MASK         DMA_OUT_MASK
 138
 139 #define TIMER1_CFG       (*(volatile unsigned long *)(0xcf001100))
 140 #define TIMER1_VAL       (*(volatile unsigned long *)(0xcf001104))
 141 #define TIMER2_CFG       (*(volatile unsigned long *)(0xcf001108))
 142 #define TIMER2_VAL       (*(volatile unsigned long *)(0xcf00110c))
 143
 144 #define USEC_TIMER       (*(volatile unsigned long *)(0xcf001110))
 145
 146 #define TIMING1_CTL      (*(volatile unsigned long *)(0xcf004000))
 147 #define TIMING2_CTL      (*(volatile unsigned long *)(0xcf004008))
 148
 149 #define PP_VER1          (*(volatile unsigned long *)(0xcf004030))
 150 #define PP_VER2          (*(volatile unsigned long *)(0xcf004034))
 151 #define PP_VER3          (*(volatile unsigned long *)(0xcf004038))
 152 #define PP_VER4          (*(volatile unsigned long *)(0xcf00403c))
 153
 154 /* Processors Control */
 155 #define PROC_STAT        (*(volatile unsigned long *)(0xcf004050))
 156 #define CPU_CTL          (*(volatile unsigned char *)(0xcf004054))
 157 #define COP_CTL          (*(volatile unsigned char *)(0xcf004058))
 158
 159 #define CPU_SLEEPING     0x8000
 160 #define COP_SLEEPING     0x4000
 161 #define PROC_SLEEPING(core) (0x8000 >> (core))
 162
 163 #define PROC_CTL(core)   ((&CPU_CTL)[(core)*4])
 164
 165 #define PROC_SLEEP       0xca
 166 #define PROC_WAKE        0xce
 167
 168 /* Cache Control */
 169 #define CACHE_CTL        (*(volatile unsigned long *)(0xcf004024))
 170 #define CACHE_RUN        0x1
 171 #define CACHE_INIT       0x2
 172
 173 #define CACHE_MASK       (*(volatile unsigned long *)(0xf000f020))
 174 #define CACHE_OPERATION  (*(volatile unsigned long *)(0xf000f024))
 175 #define CACHE_FLUSH_BASE (*(volatile unsigned long *)(0xf000c000))
 176 #define CACHE_INVALIDATE_BASE (*(volatile unsigned long *)(0xf0004000))
 177 #define CACHE_SIZE       0x2000  /* PP5002 has 8KB cache */
 178
 179 #define CACHE_OP_UNKNOWN1 (1<<11) /* 0x800 */
 180
 181 #define DEV_EN           (*(volatile unsigned long *)(0xcf005000))
 182 #define DEV_RS           (*(volatile unsigned long *)(0xcf005030))
 183
 184 #define DEV_I2C          (1<<8)
 185 #define DEV_USB          0x400000
 186
 187 #define CLOCK_ENABLE     (*(volatile unsigned long *)(0xcf005008))
 188 #define CLOCK_SOURCE     (*(volatile unsigned long *)(0xcf00500c))
 189 #define PLL_CONTROL      (*(volatile unsigned long *)(0xcf005010))
 190 #define PLL_DIV          (*(volatile unsigned long *)(0xcf005018))
 191 #define PLL_MULT         (*(volatile unsigned long *)(0xcf00501c))
 192 #define PLL_UNLOCK       (*(volatile unsigned long *)(0xcf005038))
 193
 194 #define MMAP0_LOGICAL    (*(volatile unsigned long *)(0xf000f000))
 195 #define MMAP0_PHYSICAL   (*(volatile unsigned long *)(0xf000f004))
 196 #define MMAP1_LOGICAL    (*(volatile unsigned long *)(0xf000f008))
 197 #define MMAP1_PHYSICAL   (*(volatile unsigned long *)(0xf000f00c))
 198 #define MMAP2_LOGICAL    (*(volatile unsigned long *)(0xf000f010))
 199 #define MMAP2_PHYSICAL   (*(volatile unsigned long *)(0xf000f014))
 200 #define MMAP3_LOGICAL    (*(volatile unsigned long *)(0xf000f018))
 201 #define MMAP3_PHYSICAL   (*(volatile unsigned long *)(0xf000f01c))
 202
 203 #endif