When setting a cache path also enable the cache implicitly.
[Rockbox.git] / firmware / export / mcf5250.h
blobb5679e684536935d6bc406e77ec28bac5a80439f
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2005 by Christian Gmeiner
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
18 ****************************************************************************/
19 #ifndef __MCF5250_H__
20 #define __MCF5250_H__
22 #include "mcf5249.h"
24 /* here we remove stuff, which is not included in mfc5250 */
25 #undef DACR1
26 #undef DMR1
27 #undef INTERRUPTSTAT3
28 #undef INTERRUPTCLEAR3
29 #undef INTERRUPTEN3
30 #undef IPERRORADR
32 /* here we define some new stuff */
34 #define CSAR4 (*(volatile unsigned long *)(MBAR + 0x0b0)) /* Chip Select Address Register Bank 4 */
35 #define CSMR4 (*(volatile unsigned long *)(MBAR + 0x0b4)) /* Chip Select Mask Register Bank 4 */
36 #define CSCR4 (*(volatile unsigned long *)(MBAR + 0x0b8)) /* Chip Select Control Register Bank 4 */
38 #endif