firmware/timer.c

   1 /***************************************************************************
   2 *             __________               __   ___.
   3 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7 *                     \/            \/     \/    \/            \/
   8 * $Id$
   9 *
  10 * Copyright (C) 2005 Jens Arnold
  11 *
  12 * All files in this archive are subject to the GNU General Public License.
  13 * See the file COPYING in the source tree root for full license agreement.
  14 *
  15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16 * KIND, either express or implied.
  17 *
  18 ****************************************************************************/
  19
  20 #include <stdbool.h>
  21 #include "config.h"
  22 #include "cpu.h"
  23 #include "system.h"
  24 #include "timer.h"
  25
  26 static int timer_prio = -1;
  27 static void (*pfn_timer)(void) = NULL;      /* timer callback */
  28 static void (*pfn_unregister)(void) = NULL; /* unregister callback */
  29 #ifdef CPU_COLDFIRE
  30 static int base_prescale;
  31 #elif defined CPU_PP
  32 static long cycles_new = 0;
  33 #endif
  34
  35 /* interrupt handler */
  36 #if CONFIG_CPU == SH7034
  37 void IMIA4(void) __attribute__((interrupt_handler));
  38 void IMIA4(void)
  39 {
  40     if (pfn_timer != NULL)
  41         pfn_timer();
  42     and_b(~0x01, &TSR4); /* clear the interrupt */
  43 }
  44 #elif defined CPU_COLDFIRE
  45 void TIMER1(void) __attribute__ ((interrupt_handler));
  46 void TIMER1(void)
  47 {
  48     if (pfn_timer != NULL)
  49         pfn_timer();
  50     TER1 = 0xff; /* clear all events */
  51 }
  52 #elif CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002
  53 void TIMER2(void)
  54 {
  55     TIMER2_VAL; /* ACK interrupt */
  56     if (cycles_new > 0)
  57     {
  58         TIMER2_CFG = 0xc0000000 | (cycles_new - 1);
  59         cycles_new = 0;
  60     }
  61     if (pfn_timer != NULL)
  62     {
  63         cycles_new = -1;
  64         /* "lock" the variable, in case timer_set_period()
  65          * is called within pfn_timer() */
  66         pfn_timer();
  67         cycles_new = 0;
  68     }
  69 }
  70 #endif /* CONFIG_CPU */
  71
  72 static bool timer_set(long cycles, bool start)
  73 {
  74 #if (CONFIG_CPU == SH7034) || defined(CPU_COLDFIRE)
  75     int phi = 0; /* bits for the prescaler */
  76     int prescale = 1;
  77
  78     while (cycles > 0x10000)
  79     {   /* work out the smallest prescaler that makes it fit */
  80 #if CONFIG_CPU == SH7034
  81         phi++;
  82 #endif
  83         prescale *= 2;
  84         cycles >>= 1;
  85     }
  86 #endif
  87
  88 #if CONFIG_CPU == PNX0101  /* TODO: Implement for iFP */
  89     (void)start;
  90 #endif
  91
  92 #if CONFIG_CPU == SH7034
  93     if (prescale > 8)
  94         return false;
  95
  96     if (start)
  97     {
  98         if (pfn_unregister != NULL)
  99         {
 100             pfn_unregister();
 101             pfn_unregister = NULL;
 102         }
 103
 104         and_b(~0x10, &TSTR); /* Stop the timer 4 */
 105         and_b(~0x10, &TSNC); /* No synchronization */
 106         and_b(~0x10, &TMDR); /* Operate normally */
 107
 108         TIER4 = 0xF9;        /* Enable GRA match interrupt */
 109     }
 110
 111     TCR4 = 0x20 | phi;   /* clear at GRA match, set prescaler */
 112     GRA4 = (unsigned short)(cycles - 1);
 113     if (start || (TCNT4 >= GRA4))
 114         TCNT4 = 0;
 115     and_b(~0x01, &TSR4); /* clear an eventual interrupt */
 116
 117 #elif defined CPU_COLDFIRE
 118     if (prescale > 4096/CPUFREQ_MAX_MULT)
 119         return false;
 120
 121     if (prescale > 256/CPUFREQ_MAX_MULT)
 122     {
 123         phi = 0x05;      /* prescale sysclk/16, timer enabled */
 124         prescale >>= 4;
 125     }
 126     else
 127         phi = 0x03;      /* prescale sysclk, timer enabled */
 128
 129     base_prescale = prescale;
 130     prescale *= (cpu_frequency / CPU_FREQ);
 131
 132     if (start)
 133     {
 134         if (pfn_unregister != NULL)
 135         {
 136             pfn_unregister();
 137             pfn_unregister = NULL;
 138         }
 139         phi &= ~1;       /* timer disabled at start */
 140
 141         /* If it is already enabled, writing a 0 to the RST bit will clear
 142            the register, so we clear RST explicitly before writing the real
 143            data. */
 144         TMR1 = 0;
 145     }
 146
 147     /* We are using timer 1 */
 148     TMR1 = 0x0018 | (unsigned short)phi | ((unsigned short)(prescale - 1) << 8);
 149     TRR1 = (unsigned short)(cycles - 1);
 150     if (start || (TCN1 >= TRR1))
 151         TCN1 = 0; /* reset the timer */
 152     TER1 = 0xff;  /* clear all events */
 153 #elif CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002
 154     if (cycles > 0x20000000 || cycles < 2)
 155         return false;
 156
 157     if (start)
 158     {
 159         if (pfn_unregister != NULL)
 160         {
 161             pfn_unregister();
 162             pfn_unregister = NULL;
 163         }
 164     }
 165     if (start || (cycles_new == -1))  /* within isr, cycles_new is "locked" */
 166         TIMER2_CFG = 0xc0000000 | (cycles - 1);    /* enable timer */
 167     else
 168         cycles_new = cycles;
 169
 170 #elif CONFIG_CPU == S3C2440  /* TODO: Implement for the Gigabeat */
 171     (void)start;
 172     (void)cycles;
 173 #endif /* CONFIG_CPU */
 174     return true;
 175 }
 176
 177 #ifdef CPU_COLDFIRE
 178 void timers_adjust_prescale(int multiplier, bool enable_irq)
 179 {
 180     /* tick timer */
 181     TMR0 = (TMR0 & 0x00ef)
 182          | ((unsigned short)(multiplier - 1) << 8)
 183          | (enable_irq ? 0x10 : 0);
 184
 185     if (pfn_timer)
 186     {
 187         /* user timer */
 188         int prescale = base_prescale * multiplier;
 189         TMR1 = (TMR1 & 0x00ef)
 190              | ((unsigned short)(prescale - 1) << 8)
 191              | (enable_irq ? 0x10 : 0);
 192     }
 193 }
 194 #endif
 195
 196 /* Register a user timer, called every <cycles> TIMER_FREQ cycles */
 197 bool timer_register(int reg_prio, void (*unregister_callback)(void),
 198                     long cycles, int int_prio, void (*timer_callback)(void))
 199 {
 200     if (reg_prio <= timer_prio || cycles == 0)
 201         return false;
 202
 203 #if (CONFIG_CPU==PP5002) || (CONFIG_CPU==PP5020) || (CONFIG_CPU==PNX0101) \
 204     || (CONFIG_CPU==S3C2440)
 205     /* TODO: Implement for iPod and iFP (if possible) */
 206     (void)int_prio;
 207 #endif
 208
 209 #if CONFIG_CPU == SH7034
 210     if (int_prio < 1 || int_prio > 15)
 211         return false;
 212 #elif defined CPU_COLDFIRE
 213     (void)int_prio;
 214 #endif
 215
 216     if (!timer_set(cycles, true))
 217         return false;
 218
 219     pfn_timer = timer_callback;
 220     pfn_unregister = unregister_callback;
 221     timer_prio = reg_prio;
 222
 223 #if CONFIG_CPU == SH7034
 224     IPRD = (IPRD & 0xFF0F) | int_prio << 4;  /* interrupt priority */
 225     or_b(0x10, &TSTR); /* start timer 4 */
 226 #elif defined CPU_COLDFIRE
 227     ICR2 = 0x90;       /* interrupt on level 4.0 */
 228     and_l(~(1<<10), &IMR);
 229     TMR1 |= 1;         /* start timer */
 230 #elif CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002
 231     /* unmask interrupt source */
 232     CPU_INT_EN = TIMER2_MASK;
 233 #endif
 234     return true;
 235 }
 236
 237 bool timer_set_period(long cycles)
 238 {
 239     return timer_set(cycles, false);
 240 }
 241
 242 void timer_unregister(void)
 243 {
 244 #if CONFIG_CPU == SH7034
 245     and_b(~0x10, &TSTR);    /* stop the timer 4 */
 246     IPRD = (IPRD & 0xFF0F); /* disable interrupt */
 247 #elif defined CPU_COLDFIRE
 248     TMR1 = 0;               /* disable timer 1 */
 249     or_l((1<<10), &IMR);    /* disable interrupt */
 250 #elif CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002
 251     TIMER2_CFG = 0;         /* stop timer 2 */
 252     CPU_INT_CLR = TIMER2_MASK;
 253 #endif
 254     pfn_timer = NULL;
 255     pfn_unregister = NULL;
 256     timer_prio = -1;
 257 }
 258