firmware/timer.c

   1 /***************************************************************************
   2 *             __________               __   ___.
   3 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7 *                     \/            \/     \/    \/            \/
   8 * $Id$
   9 *
  10 * Copyright (C) 2005 Jens Arnold
  11 *
  12 * All files in this archive are subject to the GNU General Public License.
  13 * See the file COPYING in the source tree root for full license agreement.
  14 *
  15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16 * KIND, either express or implied.
  17 *
  18 ****************************************************************************/
  19
  20 #include <stdbool.h>
  21 #include "config.h"
  22 #include "cpu.h"
  23 #include "system.h"
  24 #include "timer.h"
  25 #include "logf.h"
  26
  27 static int timer_prio = -1;
  28 void (*pfn_timer)(void) = NULL;      /* timer callback */
  29 void (*pfn_unregister)(void) = NULL; /* unregister callback */
  30 #ifdef CPU_COLDFIRE
  31 static int base_prescale;
  32 #elif defined CPU_PP || CONFIG_CPU == PNX0101
  33 static long cycles_new = 0;
  34 #endif
  35
  36 /* interrupt handler */
  37 #if CONFIG_CPU == SH7034
  38 void IMIA4(void) __attribute__((interrupt_handler));
  39 void IMIA4(void)
  40 {
  41     if (pfn_timer != NULL)
  42         pfn_timer();
  43     and_b(~0x01, &TSR4); /* clear the interrupt */
  44 }
  45 #elif defined CPU_COLDFIRE
  46 void TIMER1(void) __attribute__ ((interrupt_handler));
  47 void TIMER1(void)
  48 {
  49     if (pfn_timer != NULL)
  50         pfn_timer();
  51     TER1 = 0xff; /* clear all events */
  52 }
  53 #elif defined(CPU_PP)
  54 void TIMER2(void)
  55 {
  56     TIMER2_VAL; /* ACK interrupt */
  57     if (cycles_new > 0)
  58     {
  59         TIMER2_CFG = 0xc0000000 | (cycles_new - 1);
  60         cycles_new = 0;
  61     }
  62     if (pfn_timer != NULL)
  63     {
  64         cycles_new = -1;
  65         /* "lock" the variable, in case timer_set_period()
  66          * is called within pfn_timer() */
  67         pfn_timer();
  68         cycles_new = 0;
  69     }
  70 }
  71 #elif CONFIG_CPU == PNX0101
  72 void TIMER1_ISR(void)
  73 {
  74     if (cycles_new > 0)
  75     {
  76         TIMER1.load = cycles_new - 1;
  77         cycles_new = 0;
  78     }
  79     if (pfn_timer != NULL)
  80     {
  81         cycles_new = -1;
  82         /* "lock" the variable, in case timer_set_period()
  83          * is called within pfn_timer() */
  84         pfn_timer();
  85         cycles_new = 0;
  86     }
  87     TIMER1.clr = 1; /* clear the interrupt */
  88 }
  89 #endif /* CONFIG_CPU */
  90
  91 static bool timer_set(long cycles, bool start)
  92 {
  93 #if (CONFIG_CPU == SH7034) || defined(CPU_COLDFIRE)
  94     int phi = 0; /* bits for the prescaler */
  95     int prescale = 1;
  96
  97     while (cycles > 0x10000)
  98     {   /* work out the smallest prescaler that makes it fit */
  99 #if CONFIG_CPU == SH7034
 100         phi++;
 101 #endif
 102         prescale *= 2;
 103         cycles >>= 1;
 104     }
 105 #endif
 106
 107 #if CONFIG_CPU == PNX0101
 108     if (start)
 109     {
 110         if (pfn_unregister != NULL)
 111         {
 112             pfn_unregister();
 113             pfn_unregister = NULL;
 114         }
 115         TIMER1.ctrl &= ~0x80; /* disable the counter */
 116         TIMER1.ctrl |= 0x40;  /* reload after counting down to zero */
 117         TIMER1.ctrl &= ~0xc;  /* no prescaler */
 118         TIMER1.clr = 1;       /* clear an interrupt event */
 119     }
 120     if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */
 121     {                                /* enable timer */
 122         TIMER1.load = cycles - 1;
 123         TIMER1.ctrl |= 0x80;        /* enable the counter */
 124     }
 125     else
 126         cycles_new = cycles;
 127
 128     return true;
 129 #elif CONFIG_CPU == SH7034
 130     if (prescale > 8)
 131         return false;
 132
 133     if (start)
 134     {
 135         if (pfn_unregister != NULL)
 136         {
 137             pfn_unregister();
 138             pfn_unregister = NULL;
 139         }
 140
 141         and_b(~0x10, &TSTR); /* Stop the timer 4 */
 142         and_b(~0x10, &TSNC); /* No synchronization */
 143         and_b(~0x10, &TMDR); /* Operate normally */
 144
 145         TIER4 = 0xF9;        /* Enable GRA match interrupt */
 146     }
 147
 148     TCR4 = 0x20 | phi;   /* clear at GRA match, set prescaler */
 149     GRA4 = (unsigned short)(cycles - 1);
 150     if (start || (TCNT4 >= GRA4))
 151         TCNT4 = 0;
 152     and_b(~0x01, &TSR4); /* clear an eventual interrupt */
 153
 154     return true;
 155 #elif defined CPU_COLDFIRE
 156     if (prescale > 4096/CPUFREQ_MAX_MULT)
 157         return false;
 158
 159     if (prescale > 256/CPUFREQ_MAX_MULT)
 160     {
 161         phi = 0x05;      /* prescale sysclk/16, timer enabled */
 162         prescale >>= 4;
 163     }
 164     else
 165         phi = 0x03;      /* prescale sysclk, timer enabled */
 166
 167     base_prescale = prescale;
 168     prescale *= (cpu_frequency / CPU_FREQ);
 169
 170     if (start)
 171     {
 172         if (pfn_unregister != NULL)
 173         {
 174             pfn_unregister();
 175             pfn_unregister = NULL;
 176         }
 177         phi &= ~1;       /* timer disabled at start */
 178
 179         /* If it is already enabled, writing a 0 to the RST bit will clear
 180            the register, so we clear RST explicitly before writing the real
 181            data. */
 182         TMR1 = 0;
 183     }
 184
 185     /* We are using timer 1 */
 186     TMR1 = 0x0018 | (unsigned short)phi | ((unsigned short)(prescale - 1) << 8);
 187     TRR1 = (unsigned short)(cycles - 1);
 188     if (start || (TCN1 >= TRR1))
 189         TCN1 = 0; /* reset the timer */
 190     TER1 = 0xff;  /* clear all events */
 191
 192     return true;
 193 #elif defined(CPU_PP)
 194     if (cycles > 0x20000000 || cycles < 2)
 195         return false;
 196
 197     if (start)
 198     {
 199         if (pfn_unregister != NULL)
 200         {
 201             pfn_unregister();
 202             pfn_unregister = NULL;
 203         }
 204     }
 205     if (start || (cycles_new == -1))  /* within isr, cycles_new is "locked" */
 206         TIMER2_CFG = 0xc0000000 | (cycles - 1);    /* enable timer */
 207     else
 208         cycles_new = cycles;
 209
 210     return true;
 211 #elif CONFIG_CPU == S3C2440
 212     return __TIMER_SET(cycles, start);
 213 #endif /* CONFIG_CPU */
 214 }
 215
 216 #ifdef CPU_COLDFIRE
 217 void timers_adjust_prescale(int multiplier, bool enable_irq)
 218 {
 219     /* tick timer */
 220     TMR0 = (TMR0 & 0x00ef)
 221          | ((unsigned short)(multiplier - 1) << 8)
 222          | (enable_irq ? 0x10 : 0);
 223
 224     if (pfn_timer)
 225     {
 226         /* user timer */
 227         int prescale = base_prescale * multiplier;
 228         TMR1 = (TMR1 & 0x00ef)
 229              | ((unsigned short)(prescale - 1) << 8)
 230              | (enable_irq ? 0x10 : 0);
 231     }
 232 }
 233 #endif
 234
 235 /* Register a user timer, called every <cycles> TIMER_FREQ cycles */
 236 bool timer_register(int reg_prio, void (*unregister_callback)(void),
 237                     long cycles, int int_prio, void (*timer_callback)(void))
 238 {
 239     if (reg_prio <= timer_prio || cycles == 0)
 240         return false;
 241
 242 #if CONFIG_CPU == SH7034
 243     if (int_prio < 1 || int_prio > 15)
 244         return false;
 245 #endif
 246
 247     if (!timer_set(cycles, true))
 248         return false;
 249
 250     pfn_timer = timer_callback;
 251     pfn_unregister = unregister_callback;
 252     timer_prio = reg_prio;
 253
 254 #if CONFIG_CPU == SH7034
 255     IPRD = (IPRD & 0xFF0F) | int_prio << 4;  /* interrupt priority */
 256     or_b(0x10, &TSTR); /* start timer 4 */
 257     return true;
 258 #elif defined CPU_COLDFIRE
 259     ICR2 = 0x90;       /* interrupt on level 4.0 */
 260     and_l(~(1<<10), &IMR);
 261     TMR1 |= 1;         /* start timer */
 262     return true;
 263 #elif defined(CPU_PP)
 264     /* unmask interrupt source */
 265     CPU_INT_EN = TIMER2_MASK;
 266     return true;
 267 #elif CONFIG_CPU == PNX0101
 268     irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR);
 269     irq_enable_int(IRQ_TIMER1);
 270     return true;
 271 #elif CONFIG_CPU == S3C2440
 272     return __TIMER_REGISTER(reg_prio, unregister_callback, cycles,
 273                             int_prio, timer_callback);
 274 #endif
 275     /* Cover for targets that don't use all these */
 276     (void)reg_prio;
 277     (void)unregister_callback;
 278     (void)cycles;
 279     /* TODO: Implement for PortalPlayer and iFP (if possible) */
 280     (void)int_prio;
 281     (void)timer_callback;
 282 }
 283
 284 bool timer_set_period(long cycles)
 285 {
 286     return timer_set(cycles, false);
 287 }
 288
 289 void timer_unregister(void)
 290 {
 291 #if CONFIG_CPU == SH7034
 292     and_b(~0x10, &TSTR);    /* stop the timer 4 */
 293     IPRD = (IPRD & 0xFF0F); /* disable interrupt */
 294 #elif defined CPU_COLDFIRE
 295     TMR1 = 0;               /* disable timer 1 */
 296     or_l((1<<10), &IMR);    /* disable interrupt */
 297 #elif defined(CPU_PP)
 298     TIMER2_CFG = 0;         /* stop timer 2 */
 299     CPU_INT_CLR = TIMER2_MASK;
 300 #elif CONFIG_CPU == PNX0101
 301     TIMER1.ctrl &= ~0x80;  /* disable timer 1 */
 302     irq_disable_int(5);
 303 #elif CONFIG_CPU == S3C2440
 304     __TIMER_UNREGISTER();
 305 #endif
 306     pfn_timer = NULL;
 307     pfn_unregister = NULL;
 308     timer_prio = -1;
 309 }
 310