firmware/export/imx31l.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 by James Espinoza
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19
  20 /* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/
  21
  22 #define REG8_PTR_T  volatile unsigned char *
  23 #define REG16_PTR_T volatile unsigned short *
  24 #define REG32_PTR_T volatile unsigned long *
  25
  26 /* Place in the section with the framebuffer */
  27 #define TTB_BASE_ADDR           (0x80100000 + 0x00100000 - TTB_SIZE)
  28
  29 /*Frame Buffer and TTB defines from gigabeat f/x build*/
  30 #define FRAME ((short *)0x80100000) /* Framebuffer */
  31 #define LCD_BUFFER_SIZE ((320*240*2))
  32 #define TTB_SIZE (0x4000)
  33 #define TTB_BASE ((unsigned int *)TTB_BASE_ADDR)
  34
  35 /*
  36  * AIPS 1
  37  */
  38 #define IRAM_BASE_ADDR          0x1fffc000
  39 #define L2CC_BASE_ADDR          0x30000000
  40 #define AIPS1_BASE_ADDR         0x43F00000
  41 #define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
  42 #define MAX_BASE_ADDR           0x43F04000
  43 #define EVTMON_BASE_ADDR        0x43F08000
  44 #define CLKCTL_BASE_ADDR        0x43F0C000
  45 #define ETB_SLOT4_BASE_ADDR     0x43F10000
  46 #define ETB_SLOT5_BASE_ADDR     0x43F14000
  47 #define ECT_CTIO_BASE_ADDR      0x43F18000
  48 #define I2C_BASE_ADDR           0x43F80000
  49 #define I2C3_BASE_ADDR          0x43F84000
  50 #define OTG_BASE_ADDR           0x43F88000
  51 #define ATA_BASE_ADDR           0x43F8C000
  52 #define UART1_BASE_ADDR         0x43F90000
  53 #define UART2_BASE_ADDR         0x43F94000
  54 #define I2C2_BASE_ADDR          0x43F98000
  55 #define OWIRE_BASE_ADDR         0x43F9C000
  56 #define SSI1_BASE_ADDR          0x43FA0000
  57 #define CSPI1_BASE_ADDR         0x43FA4000
  58 #define KPP_BASE_ADDR           0x43FA8000
  59 #define IOMUXC_BASE_ADDR        0x43FAC000
  60 #define UART4_BASE_ADDR         0x43FB0000
  61 #define UART5_BASE_ADDR         0x43FB4000
  62 #define ECT_IP1_BASE_ADDR       0x43FB8000
  63 #define ECT_IP2_BASE_ADDR       0x43FBC000
  64
  65 /*
  66  * SPBA
  67  */
  68 #define SPBA_BASE_ADDR          0x50000000
  69 #define MMC_SDHC1_BASE_ADDR     0x50004000
  70 #define MMC_SDHC2_BASE_ADDR     0x50008000
  71 #define UART3_BASE_ADDR         0x5000C000
  72 #define CSPI2_BASE_ADDR         0x50010000
  73 #define SSI2_BASE_ADDR          0x50014000
  74 #define SIM_BASE_ADDR           0x50018000
  75 #define IIM_BASE_ADDR           0x5001C000
  76 #define ATA_DMA_BASE_ADDR       0x50020000
  77 #define SPBA_CTRL_BASE_ADDR     0x5003C000
  78
  79 /*
  80  * AIPS 2
  81  */
  82 #define AIPS2_BASE_ADDR         0x53F00000
  83 #define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
  84 #define CCM_BASE_ADDR           0x53F80000
  85 #define FIRI_BASE_ADDR          0x53F8C000
  86 #define GPT1_BASE_ADDR          0x53F90000
  87 #define EPIT1_BASE_ADDR         0x53F94000
  88 #define EPIT2_BASE_ADDR         0x53F98000
  89 #define GPIO3_BASE_ADDR         0x53FA4000
  90 #define SCC_BASE                0x53FAC000
  91 #define SCM_BASE                0x53FAE000
  92 #define SMN_BASE                0x53FAF000
  93 #define RNGA_BASE_ADDR          0x53FB0000
  94 #define IPU_CTRL_BASE_ADDR      0x53FC0000
  95 #define AUDMUX_BASE             0x53FC4000
  96 #define MPEG4_ENC_BASE          0x53FC8000
  97 #define GPIO1_BASE_ADDR         0x53FCC000
  98 #define GPIO2_BASE_ADDR         0x53FD0000
  99 #define SDMA_BASE_ADDR          0x53FD4000
 100 #define RTC_BASE_ADDR           0x53FD8000
 101 #define WDOG_BASE_ADDR          0x53FDC000
 102 #define PWM_BASE_ADDR           0x53FE0000
 103 #define RTIC_BASE_ADDR          0x53FEC000
 104
 105 #define WDOG1_BASE_ADDR         WDOG_BASE_ADDR
 106 #define CRM_MCU_BASE_ADDR       CCM_BASE_ADDR
 107
 108 /* IPU */
 109 #define IPU_CONF                (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
 110 #define IPU_CHA_BUF0_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
 111 #define IPU_CHA_BUF1_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08))
 112 #define IPU_CHA_DB_MODE_SEL     (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C))
 113 #define IPU_CHA_CUR_BUF         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10))
 114 #define IPU_FS_PROC_FLOW        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14))
 115 #define IPU_FS_DISP_FLOW        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18))
 116 #define IPU_TASKS_STAT          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C))
 117 #define IPU_IMA_ADDR            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20))
 118 #define IPU_IMA_DATA            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24))
 119 #define IPU_INT_CTRL_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28))
 120 #define IPU_INT_CTRL_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C))
 121 #define IPU_INT_CTRL_3          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30))
 122 #define IPU_INT_CTRL_4          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34))
 123 #define IPU_INT_CTRL_5          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38))
 124 #define IPU_INT_STAT_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C))
 125 #define IPU_INT_STAT_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40))
 126 #define IPU_INT_STAT_3          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44))
 127 #define IPU_INT_STAT_4          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48))
 128 #define IPU_INT_STAT_5          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C))
 129 #define IPU_BRK_CTRL_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50))
 130 #define IPU_BRK_CTRL_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
 131 #define IPU_BRK_STAT            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
 132 #define IPU_DIAGB_CTRL          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
 133
 134
 135 /* ATA */
 136 #define ATA_TIME_OFF            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))
 137 #define ATA_TIME_ON             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x01))
 138 #define ATA_TIME_1              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x02))
 139 #define ATA_TIME_2W             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x03))
 140     /* PIO */
 141 #define ATA_TIME_2R             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x04))
 142 #define ATA_TIME_AX             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x05))
 143 #define ATA_TIME_4              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x07))
 144 #define ATA_TIME_9              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x08))
 145     /* MDMA */
 146 #define ATA_TIME_M              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x09))
 147 #define ATA_TIME_JN             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0A))
 148 #define ATA_TIME_D              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0B))
 149 #define ATA_TIME_K              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0C))
 150     /* UDMA */
 151 #define ATA_TIME_ACK            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0D))
 152 #define ATA_TIME_ENV            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0E))
 153 #define ATA_TIME_PIO_RDX        (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0F))
 154 #define ATA_TIME_ZAH            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x10))
 155 #define ATA_TIME_MLIX           (*(REG8_PTR_T)(ATA_BASE_ADDR+0x11))
 156 #define ATA_TIME_DVH            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x12))
 157 #define ATA_TIME_DZFS           (*(REG8_PTR_T)(ATA_BASE_ADDR+0x13))
 158 #define ATA_TIME_DVS            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x14))
 159 #define ATA_TIME_CVS            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x15))
 160 #define ATA_TIME_SS             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x16))
 161 #define ATA_TIME_CYC            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x17))
 162     /* */
 163 #define ATA_FIFO_DATA_32        (*(REG32_PTR_T)(ATA_BASE_ADDR+0x18))
 164 #define ATA_FIFO_DATA_16        (*(REG16_PTR_T)(ATA_BASE_ADDR+0x1c))
 165 #define ATA_FIFO_FILL           (*(REG8_PTR_T)(ATA_BASE_ADDR+0x20))
 166     /* Actually ATA_CONTROL but conflicts arise */
 167 #define ATA_INTF_CONTROL        (*(REG8_PTR_T)(ATA_BASE_ADDR+0x24))
 168 #define ATA_INTERRUPT_PENDING   (*(REG8_PTR_T)(ATA_BASE_ADDR+0x28))
 169 #define ATA_INTERRUPT_ENABLE    (*(REG8_PTR_T)(ATA_BASE_ADDR+0x2c))
 170 #define ATA_INTERRUPT_CLEAR     (*(REG8_PTR_T)(ATA_BASE_ADDR+0x30))
 171 #define ATA_FIFO_ALARM          (*(REG8_PTR_T)(ATA_BASE_ADDR+0x34))
 172 #define ATA_DRIVE_DATA          (*(REG16_PTR_T)(ATA_BASE_ADDR+0xA0))
 173 #define ATA_DRIVE_FEATURES      (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA4))
 174 #define ATA_DRIVE_SECTOR_COUNT  (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA8))
 175 #define ATA_DRIVE_SECTOR_NUM    (*(REG8_PTR_T)(ATA_BASE_ADDR+0xAC))
 176 #define ATA_DRIVE_CYL_LOW       (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB0))
 177 #define ATA_DRIVE_CYL_HIGH      (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB4))
 178 #define ATA_DRIVE_CYL_HEAD      (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB8))
 179 #define ATA_DRIVE_STATUS        (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* rd */
 180 #define ATA_DRIVE_COMMAND       (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* wr */
 181 #define ATA_ALT_DRIVE_STATUS    (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* rd */
 182 #define ATA_DRIVE_CONTROL       (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* wr */
 183
 184 /* ATA_INTF_CONTROL flags */
 185 #define ATA_FIFO_RST            (1 << 7)
 186 #define ATA_ATA_RST             (1 << 6)
 187 #define ATA_FIFO_TX_EN          (1 << 5)
 188 #define ATA_FIFO_RCV_EN         (1 << 4)
 189 #define ATA_DMA_PENDING         (1 << 3)
 190 #define ATA_DMA_ULTRA_SELECTED  (1 << 2)
 191 #define ATA_DMA_WRITE           (1 << 1)
 192 #define ATA_IORDY_EN            (1 << 0)
 193
 194 /* ATA_INTERRUPT_PENDING, ATA_INTERRUPT_ENABLE, ATA_INTERRUPT_CLEAR flags */
 195 #define ATA_INTRQ1              (1 << 7)
 196 #define ATA_FIFO_UNDERFLOW      (1 << 6)
 197 #define ATA_FIFO_OVERFLOW       (1 << 5)
 198 #define ATA_CONTROLLER_IDLE     (1 << 4)
 199 #define ATA_INTRQ2              (1 << 3)
 200
 201 /* Timers */
 202 #define EPITCR1                 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))
 203 #define EPITSR1                 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04))
 204 #define EPITLR1                 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08))
 205 #define EPITCMPR1               (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C))
 206 #define EPITCNT1                (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10))
 207 #define EPITCR2                 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00))
 208 #define EPITSR2                 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04))
 209 #define EPITLR2                 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08))
 210 #define EPITCMPR2               (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C))
 211 #define EPITCNT2                (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10))
 212
 213 /* GPIO */
 214 #define GPIO1_DR                (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00))
 215 #define GPIO1_GDIR              (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04))
 216 #define GPIO1_PSR               (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08))
 217 #define GPIO1_ICR1              (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C))
 218 #define GPIO1_ICR2              (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10))
 219 #define GPIO1_IMR               (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14))
 220 #define GPIO1_ISR               (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18))
 221
 222 #define GPIO2_DR                (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00))
 223 #define GPIO2_GDIR              (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04))
 224 #define GPIO2_PSR               (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08))
 225 #define GPIO2_ICR1              (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C))
 226 #define GPIO2_ICR2              (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10))
 227 #define GPIO2_IMR               (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14))
 228 #define GPIO2_ISR               (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18))
 229
 230 #define GPIO3_DR                (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00))
 231 #define GPIO3_GDIR              (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04))
 232 #define GPIO3_PSR               (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08))
 233 #define GPIO3_ICR1              (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C))
 234 #define GPIO3_ICR2              (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10))
 235 #define GPIO3_IMR               (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14))
 236 #define GPIO3_ISR               (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18))
 237
 238 /* SPI */
 239 #define CSPI_RXDATA1            (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00))
 240 #define CSPI_TXDATA1            (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04))
 241 #define CSPI_CONREG1            (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08))
 242 #define CSPI_INTREG1            (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C))
 243 #define CSPI_DMAREG1            (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10))
 244 #define CSPI_STATREG1           (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14))
 245 #define CSPI_PERIODREG1         (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18))
 246 #define CSPI_TESTREG1           (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0))
 247
 248 #define CSPI_RXDATA2            (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00))
 249 #define CSPI_TXDATA2            (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04))
 250 #define CSPI_CONREG2            (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08))
 251 #define CSPI_INTREG2            (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C))
 252 #define CSPI_DMAREG2            (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10))
 253 #define CSPI_STATREG2           (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14))
 254 #define CSPI_PERIODREG2         (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18))
 255 #define CSPI_TESTREG2           (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0))
 256
 257 /* RTC */
 258 #define RTC_HOURMIN             (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
 259 #define RTC_SECONDS             (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
 260 #define RTC_ALRM_HM             (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
 261 #define RTC_ALRM_SEC            (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
 262 #define RTC_CTL                 (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
 263 #define RTC_ISR                 (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
 264 #define RTC_IENR                (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
 265 #define RTC_STPWCH              (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
 266 #define RTC_DAYR                (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
 267 #define RTC_DAYALARM            (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
 268
 269 /* Keypad */
 270 #define KPP_KPCR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x0))
 271 #define KPP_KPSR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x2))
 272 #define KPP_KDDR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4))
 273 #define KPP_KPDR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6))
 274
 275 /* ROMPATCH and AVIC */
 276 #define ROMPATCH_BASE_ADDR      0x60000000
 277
 278 /* Since AVIC vector registers are NOT used, we reserve some for various
 279  * purposes. Copied from Linux source code. */
 280 #define CHIP_REV_1_0            0x10
 281 #define CHIP_REV_2_0            0x20
 282 #define SYSTEM_REV_ID_REG       (AVIC_BASE_ADDR + AVIC_VEC_1)
 283 #define SYSTEM_REV_ID_MAG       0xF00C
 284
 285 /*
 286  * NAND, SDRAM, WEIM, M3IF, EMI controllers
 287  */
 288 #define EXT_MEM_CTRL_BASE       0xB8000000
 289 #define NFC_BASE                EXT_MEM_CTRL_BASE
 290 #define ESDCTL_BASE             0xB8001000
 291 #define WEIM_BASE_ADDR          0xB8002000
 292 #define WEIM_CTRL_CS0           (WEIM_BASE_ADDR+0x00)
 293 #define WEIM_CTRL_CS1           (WEIM_BASE_ADDR+0x10)
 294 #define WEIM_CTRL_CS2           (WEIM_BASE_ADDR+0x20)
 295 #define WEIM_CTRL_CS3           (WEIM_BASE_ADDR+0x30)
 296 #define WEIM_CTRL_CS4           (WEIM_BASE_ADDR+0x40)
 297 #define M3IF_BASE               0xB8003000
 298 #define PCMCIA_CTL_BASE         0xB8004000
 299
 300 /*
 301  * Memory regions and CS
 302  */
 303 #define IPU_MEM_BASE_ADDR       0x70000000
 304 #define CSD0_BASE_ADDR          0x80000000
 305 #define CSD1_BASE_ADDR          0x90000000
 306 #define CS0_BASE_ADDR           0xA0000000
 307 #define CS1_BASE_ADDR           0xA8000000
 308 #define CS2_BASE_ADDR           0xB0000000
 309 #define CS3_BASE_ADDR           0xB2000000
 310 #define CS4_BASE_ADDR           0xB4000000
 311 #define CS4_BASE_PSRAM          0xB5000000
 312 #define CS5_BASE_ADDR           0xB6000000
 313 #define PCMCIA_MEM_BASE_ADDR    0xC0000000
 314
 315 #define INTERNAL_ROM_VA         0xF0000000
 316
 317 /*
 318  * SDRAM
 319  */
 320 #define RAM_BANK0_BASE          SDRAM_BASE_ADDR
 321
 322 /*
 323  * IRQ Controller Register Definitions.
 324  */
 325 #define AVIC_BASE_ADDR         0x68000000
 326 #define INTCNTL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
 327 #define NIMASK                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
 328 #define INTENNUM               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
 329 #define INTDISNUM              (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
 330 #define INTENABLEH             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
 331 #define INTENABLEL             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
 332 #define INTTYPEH               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
 333 #define INTTYPEL               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
 334 #define NIPRIORITY(n)          (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
 335 #define NIPRIORITY7            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
 336 #define NIPRIORITY6            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
 337 #define NIPRIORITY5            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
 338 #define NIPRIORITY4            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
 339 #define NIPRIORITY3            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
 340 #define NIPRIORITY2            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
 341 #define NIPRIORITY1            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
 342 #define NIPRIORITY0            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
 343 #define NIVECSR                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
 344 #define FIVECSR                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
 345 #define INTSRCH                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
 346 #define INTSRCL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
 347 #define INTFRCH                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
 348 #define INTFRCL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
 349 #define NIPNDH                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
 350 #define NIPNDL                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
 351 #define FIPNDH                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
 352 #define FIPNDL                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
 353 #define VECTOR_BASE_ADDR       (AVIC_BASE_ADDR+0x100)
 354 #define VECTOR(n)              (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
 355
 356 /* The vectors go all the way up to 63. 4 bytes for each */
 357 #define INTCNTL_ABFLAG         (1 << 25)
 358 #define INTCNTL_ABFEN          (1 << 24)
 359 #define INTCNTL_NIDIS          (1 << 22)
 360 #define INTCNTL_FIDIS          (1 << 21)
 361 #define INTCNTL_NIAD           (1 << 20)
 362 #define INTCNTL_FIAD           (1 << 19)
 363 #define INTCNTL_NM             (1 << 18)
 364
 365 /* L210 */
 366 #define L2CC_BASE_ADDR                  0x30000000
 367 #define L2_CACHE_LINE_SIZE              32
 368 #define L2_CACHE_CTL_REG                0x100
 369 #define L2_CACHE_AUX_CTL_REG            0x104
 370 #define L2_CACHE_SYNC_REG               0x730
 371 #define L2_CACHE_INV_LINE_REG           0x770
 372 #define L2_CACHE_INV_WAY_REG            0x77C
 373 #define L2_CACHE_CLEAN_LINE_REG         0x7B0
 374 #define L2_CACHE_CLEAN_INV_LINE_REG     0x7F0
 375
 376 #define L2CC_CACHE_SYNC                 (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
 377
 378 /* CCM */
 379 #define CLKCTL_CCMR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
 380 #define CLKCTL_PDR0                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
 381 #define CLKCTL_PDR1                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
 382 #define CLKCTL_PDR2                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
 383 #define CLKCTL_RCSR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
 384 #define CLKCTL_MPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
 385 #define CLKCTL_UPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
 386 #define CLKCTL_SPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
 387 #define CLKCTL_COSR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
 388 #define CLKCTL_CGR0                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
 389 #define CLKCTL_CGR1                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
 390 #define CLKCTL_CGR2                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
 391 #define CLKCTL_WIMR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
 392 #define CLKCTL_PMCR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
 393 #define PLL_REF_CLK                     26000000
 394
 395 /* WEIM - CS0 */
 396 #define CSCRU                           0x00
 397 #define CSCRL                           0x04
 398 #define CSCRA                           0x08
 399
 400 /* ESDCTL */
 401 #define ESDCTL_ESDCTL0                  0x00
 402 #define ESDCTL_ESDCFG0                  0x04
 403 #define ESDCTL_ESDCTL1                  0x08
 404 #define ESDCTL_ESDCFG1                  0x0C
 405 #define ESDCTL_ESDMISC                  0x10
 406
 407 /* More UART 1 Register defines */
 408 #define URXD1                           (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
 409 #define UTXD1                           (*(REG32_PTR_T)(UART1_BASE_ADDR+0x40))
 410 #define UCR1_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x80))
 411 #define UCR2_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x84))
 412 #define UCR3_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x88))
 413 #define UCR4_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x8C))
 414 #define UFCR1                           (*(REG32_PTR_T)(UART1_BASE_ADDR+0x90))
 415 #define USR1_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x94))
 416 #define USR2_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98))
 417 #define UTS1                            (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4))
 418
 419 /*
 420  * UART Control Register 0 Bit Fields.
 421  */
 422 #define EUartUCR1_ADEN      (1 << 15)   // Auto detect interrupt
 423 #define EUartUCR1_ADBR      (1 << 14)   // Auto detect baud rate
 424 #define EUartUCR1_TRDYEN    (1 << 13)   // Transmitter ready interrupt enable
 425 #define EUartUCR1_IDEN      (1 << 12)   // Idle condition interrupt
 426 #define EUartUCR1_RRDYEN    (1 << 9)    // Recv ready interrupt enable
 427 #define EUartUCR1_RDMAEN    (1 << 8)    // Recv ready DMA enable
 428 #define EUartUCR1_IREN      (1 << 7)    // Infrared interface enable
 429 #define EUartUCR1_TXMPTYEN  (1 << 6)    // Transimitter empt  interrupt enable
 430 #define EUartUCR1_RTSDEN    (1 << 5)    // RTS delta interrupt enable
 431 #define EUartUCR1_SNDBRK    (1 << 4)    // Send break
 432 #define EUartUCR1_TDMAEN    (1 << 3)    // Transmitter ready DMA enable
 433 #define EUartUCR1_DOZE      (1 << 1)    // Doze
 434 #define EUartUCR1_UARTEN    (1 << 0)    // UART enabled
 435 #define EUartUCR2_ESCI      (1 << 15)   // Escape seq interrupt enable
 436 #define EUartUCR2_IRTS      (1 << 14)   // Ignore RTS pin
 437 #define EUartUCR2_CTSC      (1 << 13)   // CTS pin control
 438 #define EUartUCR2_CTS       (1 << 12)   // Clear to send
 439 #define EUartUCR2_ESCEN     (1 << 11)   // Escape enable
 440 #define EUartUCR2_PREN      (1 << 8)    // Parity enable
 441 #define EUartUCR2_PROE      (1 << 7)    // Parity odd/even
 442 #define EUartUCR2_STPB      (1 << 6)    // Stop
 443 #define EUartUCR2_WS        (1 << 5)    // Word size
 444 #define EUartUCR2_RTSEN     (1 << 4)    // Request to send interrupt enable
 445 #define EUartUCR2_ATEN      (1 << 3)    // Aging timer enable
 446 #define EUartUCR2_TXEN      (1 << 2)    // Transmitter enabled
 447 #define EUartUCR2_RXEN      (1 << 1)    // Receiver enabled
 448 #define EUartUCR2_SRST_     (1 << 0)    // SW reset
 449 #define EUartUCR3_PARERREN  (1 << 12)   // Parity enable
 450 #define EUartUCR3_FRAERREN  (1 << 11)   // Frame error interrupt enable
 451 #define EUartUCR3_ADNIMP    (1 << 7)    // Autobaud detection not improved
 452 #define EUartUCR3_RXDSEN    (1 << 6)    // Receive status interrupt  enable
 453 #define EUartUCR3_AIRINTEN  (1 << 5)    // Async IR wake interrupt enable
 454 #define EUartUCR3_AWAKEN    (1 << 4)    // Async wake interrupt enable
 455 #define EUartUCR3_RXDMUXSEL (1 << 2)    // RXD muxed input selected
 456 #define EUartUCR3_INVT      (1 << 1)    // Inverted Infrared transmission
 457 #define EUartUCR3_ACIEN     (1 << 0)    // Autobaud counter interrupt  enable
 458 #define EUartUCR4_CTSTL_32  (32 << 10)  // CTS trigger level (32 chars)
 459 #define EUartUCR4_INVR      (1 << 9)    // Inverted infrared reception
 460 #define EUartUCR4_ENIRI     (1 << 8)    // Serial infrared interrupt enable
 461 #define EUartUCR4_WKEN      (1 << 7)    // Wake interrupt enable
 462 #define EUartUCR4_IRSC      (1 << 5)    // IR special case
 463 #define EUartUCR4_LPBYP     (1 << 4)    // Low power bypass
 464 #define EUartUCR4_TCEN      (1 << 3)    // Transmit complete interrupt  enable
 465 #define EUartUCR4_BKEN      (1 << 2)    // Break condition interrupt enable
 466 #define EUartUCR4_OREN      (1 << 1)    // Receiver overrun interrupt enable
 467 #define EUartUCR4_DREN      (1 << 0)    // Recv data ready interrupt enable
 468 #define EUartUFCR_RXTL_SHF  0           // Receiver trigger level shift
 469 #define EUartUFCR_RFDIV_1   (5 << 7)    // Reference freq divider (div> 1)
 470 #define EUartUFCR_RFDIV_2   (4 << 7)    // Reference freq divider (div> 2)
 471 #define EUartUFCR_RFDIV_3   (3 << 7)            // Reference freq  divider (div 3)
 472 #define EUartUFCR_RFDIV_4   (2 << 7)            // Reference freq divider (div 4)
 473 #define EUartUFCR_RFDIV_5   (1 << 7)            // Reference freq divider (div 5)
 474 #define EUartUFCR_RFDIV_6   (0 << 7)            // Reference freq divider (div 6)
 475 #define EUartUFCR_RFDIV_7   (6 << 7)            // Reference freq divider (div 7)
 476 #define EUartUFCR_TXTL_SHF  10          // Transmitter trigger level shift
 477 #define EUartUSR1_PARITYERR (1 << 15)   // Parity error interrupt flag
 478 #define EUartUSR1_RTSS      (1 << 14)   // RTS pin status
 479 #define EUartUSR1_TRDY      (1 << 13)   // Transmitter ready interrupt/dma flag
 480 #define EUartUSR1_RTSD      (1 << 12)   // RTS delta
 481 #define EUartUSR1_ESCF      (1 << 11)   // Escape seq interrupt flag
 482 #define EUartUSR1_FRAMERR   (1 << 10)   // Frame error interrupt flag
 483 #define EUartUSR1_RRDY      (1 << 9)    // Receiver ready  interrupt/dma flag
 484 #define EUartUSR1_AGTIM     (1 << 8)    // Aging timeout interrupt status
 485 #define EUartUSR1_RXDS      (1 << 6)    // Receiver idle interrupt flag
 486 #define EUartUSR1_AIRINT    (1 << 5)    // Async IR wake interrupt flag
 487 #define EUartUSR1_AWAKE     (1 << 4)    // Aysnc wake interrupt flag
 488 #define EUartUSR2_ADET      (1 << 15)   // Auto baud rate detect  complete
 489 #define EUartUSR2_TXFE      (1 << 14)   // Transmit buffer FIFO empty
 490 #define EUartUSR2_IDLE      (1 << 12)   // Idle condition
 491 #define EUartUSR2_ACST      (1 << 11)   // Autobaud counter stopped
 492 #define EUartUSR2_IRINT     (1 << 8)    // Serial infrared interrupt flag
 493 #define EUartUSR2_WAKE      (1 << 7)    // Wake
 494 #define EUartUSR2_RTSF      (1 << 4)    // RTS edge interrupt flag
 495 #define EUartUSR2_TXDC      (1 << 3)    // Transmitter complete
 496 #define EUartUSR2_BRCD      (1 << 2)    // Break condition
 497 #define EUartUSR2_ORE       (1 << 1)    // Overrun error
 498 #define EUartUSR2_RDR       (1 << 0)    // Recv data ready
 499 #define EUartUTS_FRCPERR    (1 << 13)   // Force parity error
 500 #define EUartUTS_LOOP       (1 << 12)   // Loop tx and rx
 501 #define EUartUTS_TXEMPTY    (1 << 6)    // TxFIFO empty
 502 #define EUartUTS_RXEMPTY    (1 << 5)    // RxFIFO empty
 503 #define EUartUTS_TXFULL     (1 << 4)    // TxFIFO full
 504 #define EUartUTS_RXFULL     (1 << 3)    // RxFIFO full
 505 #define EUartUTS_SOFTRST    (1 << 0)    // Software reset
 506
 507 #define DelayTimerPresVal   3
 508
 509 #define L2CC_ENABLED
 510
 511 /* Assuming 26MHz input clock */
 512 /*                         PD          MFD           MFI          MFN */
 513 #define MPCTL_PARAM_208  ((1 << 26) + (0   << 16) + (8  << 10) + (0 << 0))
 514 #define MPCTL_PARAM_399  ((0 << 26) + (51  << 16) + (7  << 10) + (35 << 0))
 515 #define MPCTL_PARAM_532  ((0 << 26) + (51  << 16) + (10 << 10) + (12 << 0))
 516
 517 /* UPCTL                   PD             MFD              MFI          MFN */
 518 #define UPCTL_PARAM_288  (((1-1) << 26) + ((13-1) << 16) + (5  << 10) + (7  << 0))
 519 #define UPCTL_PARAM_240  (((2-1) << 26) + ((13-1) << 16) + (9  << 10) + (3  << 0))
 520
 521 /* PDR0 */
 522 #define PDR0_208_104_52     0xFF870D48  /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
 523 #define PDR0_399_66_66      0xFF872B28  /* ARM=399MHz, HCLK=IPG=66.5MHz */
 524 #define PDR0_399_133_66     0xFF871650  /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
 525 #define PDR0_532_133_66     0xFF871E58  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
 526 #define PDR0_665_83_66      0xFF873D78  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
 527 #define PDR0_665_133_66     0xFF872660  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
 528
 529 #define PBC_BASE            CS4_BASE_ADDR    /* Peripheral Bus Controller */
 530
 531 #define PBC_BSTAT2                  0x2
 532 #define PBC_BCTRL1                  0x4
 533 #define PBC_BCTRL1_CLR              0x6
 534 #define PBC_BCTRL2                  0x8
 535 #define PBC_BCTRL2_CLR              0xA
 536 #define PBC_BCTRL3                  0xC
 537 #define PBC_BCTRL3_CLR              0xE
 538 #define PBC_BCTRL4                  0x10
 539 #define PBC_BCTRL4_CLR              0x12
 540 #define PBC_BSTAT1                  0x14
 541 #define MX31EVB_CS_LAN_BASE         (CS4_BASE_ADDR + 0x00020000 +  0x300)
 542 #define MX31EVB_CS_UART_BASE        (CS4_BASE_ADDR + 0x00010000)
 543
 544 #define REDBOOT_IMAGE_SIZE              0x40000
 545
 546 #define SDRAM_WORKAROUND_FULL_PAGE
 547
 548 #define ARMHIPG_208_52_52         /* ARM: 208MHz, HCLK=IPG=52MHz*/
 549 #define ARMHIPG_52_52_52          /* ARM: 52MHz, HCLK=IPG=52MHz*/
 550 #define ARMHIPG_399_66_66
 551 #define ARMHIPG_399_133_66
 552
 553 /* MX31 EVB SDRAM is from 0x80000000, 64M */
 554 #define SDRAM_BASE_ADDR                 CSD0_BASE_ADDR
 555 #define SDRAM_SIZE                      0x04000000
 556
 557 #define UART_WIDTH_32         /* internal UART is 32bit access only */
 558 #define EXT_UART_x16
 559
 560 #define UART_WIDTH_32         /* internal UART is 32bit access only */
 561
 562 #define FLASH_BURST_MODE_ENABLE 1
 563 #define SDRAM_COMPARE_CONST1    0x55555555
 564 #define SDRAM_COMPARE_CONST2    0xAAAAAAAA
 565 #define UART_FIFO_CTRL          0x881
 566 #define TIMEOUT                 1000
 567 #define writel(v,a)             (*(REG32_PTR_T)(a) = (v))
 568 #define readl(a)                (*(REG32_PTR_T)(a))
 569 #define writew(v,a)             (*(REG16_PTR_T)(a) = (v))
 570 #define readw(a)                (*(REG16_PTR_T)(a))