1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2005 by Andy Young
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
18 ****************************************************************************/
25 #include "i2c-coldfire.h"
29 const struct sound_settings_info audiohw_settings
[] = {
30 [SOUND_VOLUME
] = {"dB", 0, 1, -84, 0, -25},
31 [SOUND_BASS
] = {"dB", 0, 2, 0, 24, 0},
32 [SOUND_TREBLE
] = {"dB", 0, 2, 0, 6, 0},
33 [SOUND_BALANCE
] = {"%", 0, 1,-100, 100, 0},
34 [SOUND_CHANNELS
] = {"", 0, 1, 0, 5, 0},
35 [SOUND_STEREO_WIDTH
] = {"%", 0, 5, 0, 250, 100},
36 [SOUND_LEFT_GAIN
] = {"dB", 1, 1,-128, 96, 0},
37 [SOUND_RIGHT_GAIN
] = {"dB", 1, 1,-128, 96, 0},
38 [SOUND_MIC_GAIN
] = {"dB", 1, 1,-128, 108, 16},
41 /* convert tenth of dB volume (-840..0) to master volume register value */
42 int tenthdb2master(int db
)
44 if (db
< -720) /* 1.5 dB steps */
45 return (2940 - db
) / 15;
46 else if (db
< -660) /* 0.75 dB steps */
47 return (1110 - db
) * 2 / 15;
48 else if (db
< -520) /* 0.5 dB steps */
49 return (520 - db
) / 5;
50 else /* 0.25 dB steps */
54 /* convert tenth of dB volume (-780..0) to mixer volume register value */
55 int tenthdb2mixer(int db
)
57 if (db
< -660) /* 1.5 dB steps */
58 return (2640 - db
) / 15;
59 else if (db
< -600) /* 0.75 dB steps */
60 return (990 - db
) * 2 / 15;
61 else if (db
< -460) /* 0.5 dB steps */
62 return (460 - db
) / 5;
63 else /* 0.25 dB steps */
67 /* ------------------------------------------------- */
68 /* Local functions and variables */
69 /* ------------------------------------------------- */
71 static int uda1380_write_reg(unsigned char reg
, unsigned short value
);
72 unsigned short uda1380_regs
[0x30];
76 /* Definition of a playback configuration to start with */
78 #define NUM_DEFAULT_REGS 13
79 unsigned short uda1380_defaults
[2*NUM_DEFAULT_REGS
] =
81 REG_0
, EN_DAC
| EN_INT
| EN_DEC
| ADC_CLK
| DAC_CLK
|
82 SYSCLK_256FS
| WSPLL_25_50
,
83 REG_I2S
, I2S_IFMT_IIS
,
84 REG_PWR
, PON_PLL
| PON_BIAS
,
85 /* PON_HP & PON_DAC is enabled later */
86 REG_AMIX
, AMIX_RIGHT(0x3f) | AMIX_LEFT(0x3f),
88 REG_MASTER_VOL
, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20),
90 REG_MIX_VOL
, MIX_VOL_CH_1(0) | MIX_VOL_CH_2(0xff),
93 /* Bass and treble = 0 dB */
94 REG_MUTE
, MUTE_MASTER
| MUTE_CH2
,
95 /* Mute everything to start with */
96 REG_MIX_CTL
, MIX_CTL_MIX
,
105 /* Returns 0 if register was written or -1 if write failed */
106 static int uda1380_write_reg(unsigned char reg
, unsigned short value
)
108 unsigned char data
[3];
111 data
[1] = value
>> 8;
112 data
[2] = value
& 0xff;
114 if (i2c_write(I2C_IFACE_0
, UDA1380_ADDR
, data
, 3) != 3)
116 DEBUGF("uda1380 error reg=0x%x", reg
);
120 uda1380_regs
[reg
] = value
;
126 * Sets left and right master volume (0(max) to 252(muted))
128 void audiohw_set_master_vol(int vol_l
, int vol_r
)
130 uda1380_write_reg(REG_MASTER_VOL
,
131 MASTER_VOL_LEFT(vol_l
) | MASTER_VOL_RIGHT(vol_r
));
135 * Sets mixer volume for both channels (0(max) to 228(muted))
137 void audiohw_set_mixer_vol(int channel1
, int channel2
)
139 uda1380_write_reg(REG_MIX_VOL
,
140 MIX_VOL_CH_1(channel1
) | MIX_VOL_CH_2(channel2
));
144 * Sets the bass value (0-12)
146 void audiohw_set_bass(int value
)
148 uda1380_write_reg(REG_EQ
, (uda1380_regs
[REG_EQ
] & ~BASS_MASK
)
149 | BASSL(value
) | BASSR(value
));
153 * Sets the treble value (0-3)
155 void audiohw_set_treble(int value
)
157 uda1380_write_reg(REG_EQ
, (uda1380_regs
[REG_EQ
] & ~TREBLE_MASK
)
158 | TREBLEL(value
) | TREBLER(value
));
161 void audiohw_mute(bool mute
)
163 unsigned int value
= uda1380_regs
[REG_MUTE
];
166 value
= value
| MUTE_MASTER
;
168 value
= value
& ~MUTE_MASTER
;
170 uda1380_write_reg(REG_MUTE
, value
);
173 /* Returns 0 if successful or -1 if some register failed */
174 static int audiohw_set_regs(void)
177 memset(uda1380_regs
, 0, sizeof(uda1380_regs
));
179 /* Initialize all registers */
180 for (i
=0; i
<NUM_DEFAULT_REGS
; i
++)
182 unsigned char reg
= uda1380_defaults
[i
*2+0];
183 unsigned short value
= uda1380_defaults
[i
*2+1];
185 if (uda1380_write_reg(reg
, value
) == -1)
192 /* Silently enable / disable audio output */
193 void audiohw_enable_output(bool enable
)
196 uda1380_write_reg(REG_PWR
, uda1380_regs
[REG_PWR
] | PON_DAC
| PON_HP
);
198 uda1380_write_reg(REG_MUTE
, MUTE_MASTER
);
199 uda1380_write_reg(REG_PWR
, uda1380_regs
[REG_PWR
] & ~PON_DAC
);
203 static void reset(void)
205 #ifdef IRIVER_H300_SERIES
206 int mask
= disable_irq_save();
207 pcf50606_write(0x3b, 0x00); /* GPOOD2 high Z */
208 pcf50606_write(0x3b, 0x07); /* GPOOD2 low */
212 or_l(1<<29, &GPIO_OUT
);
213 or_l(1<<29, &GPIO_ENABLE
);
214 or_l(1<<29, &GPIO_FUNCTION
);
216 and_l(~(1<<29), &GPIO_OUT
);
221 * Sets frequency settings for DAC and ADC relative to MCLK
223 * Selection for frequency ranges:
225 * 11025: 0 = 6.25 to 12.5 MCLK/2 SCLK, LRCK: Audio Clk / 16
226 * 22050: 1 = 12.5 to 25 MCLK/2 SCLK, LRCK: Audio Clk / 8
227 * 44100: 2 = 25 to 50 MCLK SCLK, LRCK: Audio Clk / 4 (default)
228 * 88200: 3 = 50 to 100 MCLK SCLK, LRCK: Audio Clk / 2 <= TODO: Needs WSPLL
230 void audiohw_set_frequency(unsigned fsel
)
232 static const unsigned short values_reg
[4][2] =
235 { 0, WSPLL_625_125
| SYSCLK_512FS
}, /* 11025 */
236 { 0, WSPLL_125_25
| SYSCLK_256FS
}, /* 22050 */
237 { MIX_CTL_SEL_NS
, WSPLL_25_50
| SYSCLK_256FS
}, /* 44100 */
238 { MIX_CTL_SEL_NS
, WSPLL_50_100
| SYSCLK_256FS
}, /* 88200 */
241 const unsigned short *ent
;
243 if (fsel
>= ARRAYLEN(values_reg
))
246 ent
= values_reg
[fsel
];
248 /* Set WSPLL input frequency range or SYSCLK divider */
249 uda1380_regs
[REG_0
] &= ~0xf;
250 uda1380_write_reg(REG_0
, uda1380_regs
[REG_0
] | ent
[1]);
252 /* Choose 3rd order or 5th order noise shaper */
253 uda1380_regs
[REG_MIX_CTL
] &= ~MIX_CTL_SEL_NS
;
254 uda1380_write_reg(REG_MIX_CTL
, uda1380_regs
[REG_MIX_CTL
] | ent
[0]);
257 /* Initialize UDA1380 codec with default register values (uda1380_defaults) */
258 void audiohw_init(void)
265 if (audiohw_set_regs() == -1)
267 /* this shoud never (!) happen. */
268 logf("uda1380: audiohw_init failed");
272 void audiohw_postinit(void)
274 /* Sleep a while so the power can stabilize (especially a long
275 delay is needed for the line out connector). */
277 /* Power on FSDAC and HP amp. */
278 audiohw_enable_output(true);
280 /* UDA1380: Unmute the master channel
281 (DAC should be at zero point now). */
285 /* Nice shutdown of UDA1380 codec */
286 void audiohw_close(void)
288 /* First enable mute and sleep a while */
289 uda1380_write_reg(REG_MUTE
, MUTE_MASTER
);
292 /* Then power off the rest of the chip */
293 uda1380_write_reg(REG_PWR
, 0);
294 uda1380_write_reg(REG_0
, 0); /* Disable codec */
298 * Calling this function enables the UDA1380 to send
299 * sound samples over the I2S bus, which is connected
300 * to the processor's IIS1 interface.
302 * source_mic: true=record from microphone, false=record from line-in (or radio)
304 void audiohw_enable_recording(bool source_mic
)
306 uda1380_regs
[REG_0
] &= ~(ADC_CLK
| DAC_CLK
);
307 uda1380_write_reg(REG_0
, uda1380_regs
[REG_0
] | EN_ADC
);
311 /* VGA_GAIN: 0=0 dB, F=30dB */
312 /* Output of left ADC is fed into right bitstream */
313 uda1380_regs
[REG_PWR
] &= ~(PON_PGAR
| PON_ADCR
);
314 uda1380_write_reg(REG_PWR
, uda1380_regs
[REG_PWR
] | PON_LNA
| PON_ADCL
);
315 uda1380_regs
[REG_ADC
] &= ~SKIP_DCFIL
;
316 uda1380_write_reg(REG_ADC
, (uda1380_regs
[REG_ADC
] & VGA_GAIN_MASK
)
317 | SEL_LNA
| SEL_MIC
| EN_DCFIL
);
318 uda1380_write_reg(REG_PGA
, 0);
322 /* PGA_GAIN: 0=0 dB, F=24dB */
323 uda1380_regs
[REG_PWR
] &= ~PON_LNA
;
324 uda1380_write_reg(REG_PWR
, uda1380_regs
[REG_PWR
] | PON_PGAL
| PON_ADCL
325 | PON_PGAR
| PON_ADCR
);
326 uda1380_write_reg(REG_ADC
, EN_DCFIL
);
327 uda1380_write_reg(REG_PGA
, uda1380_regs
[REG_PGA
] & PGA_GAIN_MASK
);
332 uda1380_write_reg(REG_I2S
, uda1380_regs
[REG_I2S
] | I2S_MODE_MASTER
);
333 uda1380_write_reg(REG_MIX_CTL
, MIX_MODE(1));
337 * Stop sending samples on the I2S bus
339 void audiohw_disable_recording(void)
341 uda1380_write_reg(REG_PGA
, MUTE_ADC
);
344 uda1380_write_reg(REG_I2S
, I2S_IFMT_IIS
);
346 uda1380_regs
[REG_PWR
] &= ~(PON_LNA
| PON_ADCL
| PON_ADCR
|
347 PON_PGAL
| PON_PGAR
);
348 uda1380_write_reg(REG_PWR
, uda1380_regs
[REG_PWR
]);
350 uda1380_regs
[REG_0
] &= ~EN_ADC
;
351 uda1380_write_reg(REG_0
, uda1380_regs
[REG_0
] | ADC_CLK
| DAC_CLK
);
353 uda1380_write_reg(REG_ADC
, SKIP_DCFIL
);
357 * Set recording gain and volume
359 * type: params: ranges:
360 * AUDIO_GAIN_MIC: left -128 .. 108 -> -64 .. 54 dB gain
361 * AUDIO_GAIN_LINEIN left & right -128 .. 96 -> -64 .. 48 dB gain
363 * Note: - For all types the value 0 gives 0 dB gain.
364 * - order of setting both values determines if the small glitch will
365 be a peak or a dip. The small glitch is caused by the time between
366 setting the two gains
368 void audiohw_set_recvol(int left
, int right
, int type
)
370 int left_ag
, right_ag
;
375 left_ag
= MIN(MAX(0, left
/ 4), 15);
378 if(left
< recgain_mic
)
380 uda1380_write_reg(REG_DEC_VOL
, DEC_VOLL(left
)
382 uda1380_write_reg(REG_ADC
, (uda1380_regs
[REG_ADC
]
384 | VGA_GAIN(left_ag
));
388 uda1380_write_reg(REG_ADC
, (uda1380_regs
[REG_ADC
]
390 | VGA_GAIN(left_ag
));
391 uda1380_write_reg(REG_DEC_VOL
, DEC_VOLL(left
)
395 logf("Mic: %dA/%dD", left_ag
, left
);
398 case AUDIO_GAIN_LINEIN
:
399 left_ag
= MIN(MAX(0, left
/ 6), 8);
401 right_ag
= MIN(MAX(0, right
/ 6), 8);
402 right
-= right_ag
* 6;
404 if(left
< recgain_line
)
406 /* for this order we can combine both registers,
407 making the glitch even smaller */
408 unsigned char data
[5];
409 unsigned short value_dec
;
410 unsigned short value_pga
;
411 value_dec
= DEC_VOLL(left
) | DEC_VOLR(right
);
412 value_pga
= (uda1380_regs
[REG_PGA
] & ~PGA_GAIN_MASK
)
413 | PGA_GAINL(left_ag
) | PGA_GAINR(right_ag
);
415 data
[0] = REG_DEC_VOL
;
416 data
[1] = value_dec
>> 8;
417 data
[2] = value_dec
& 0xff;
418 data
[3] = value_pga
>> 8;
419 data
[4] = value_pga
& 0xff;
421 if (i2c_write(I2C_IFACE_0
, UDA1380_ADDR
, data
, 5) != 5)
423 DEBUGF("uda1380 error reg=combi rec gain");
427 uda1380_regs
[REG_DEC_VOL
] = value_dec
;
428 uda1380_regs
[REG_PGA
] = value_pga
;
433 uda1380_write_reg(REG_PGA
, (uda1380_regs
[REG_PGA
]
436 | PGA_GAINR(right_ag
));
437 uda1380_write_reg(REG_DEC_VOL
, DEC_VOLL(left
)
442 logf("Line L: %dA/%dD", left_ag
, left
);
443 logf("Line R: %dA/%dD", right_ag
, right
);
450 * Enable or disable recording monitor (so one can listen to the recording)
453 void audiohw_set_monitor(bool enable
)
455 if (enable
) /* enable channel 2 */
456 uda1380_write_reg(REG_MUTE
, uda1380_regs
[REG_MUTE
] & ~MUTE_CH2
);
457 else /* mute channel 2 */
458 uda1380_write_reg(REG_MUTE
, uda1380_regs
[REG_MUTE
] | MUTE_CH2
);