firmware/target/arm/system-pp502x.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Alan Korr
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "system.h"
  22 #include "thread.h"
  23 #include "i2s.h"
  24 #include "i2c-pp.h"
  25 #include "as3514.h"
  26 #include "ata-sd-target.h"
  27 #include "button-target.h"
  28 #ifdef HAVE_USBSTACK
  29 #include "usb_drv.h"
  30 #endif
  31
  32 #ifndef BOOTLOADER
  33 extern void TIMER1(void);
  34 extern void TIMER2(void);
  35 extern void ipod_mini_button_int(void); /* iPod Mini 1st gen only */
  36 extern void ipod_4g_button_int(void);   /* iPod 4th gen and higher only */
  37 #ifdef MROBE_100
  38 extern void button_int(void);
  39 #endif
  40
  41 void irq(void)
  42 {
  43     if(CURRENT_CORE == CPU)
  44     {
  45         if (CPU_INT_STAT & TIMER1_MASK) {
  46             TIMER1();
  47         } else if (CPU_INT_STAT & TIMER2_MASK)
  48             TIMER2();
  49 #if defined(IPOD_MINI) /* Mini 1st gen only, mini 2nd gen uses iPod 4G code */
  50         else if (CPU_HI_INT_STAT & GPIO0_MASK)
  51             ipod_mini_button_int();
  52 #elif CONFIG_KEYPAD == IPOD_4G_PAD /* except Mini 1st gen, handled above */
  53         else if (CPU_HI_INT_STAT & I2C_MASK)
  54             ipod_4g_button_int();
  55 #elif defined(SANSA_E200)
  56 #ifdef HAVE_HOTSWAP
  57         else if (CPU_HI_INT_STAT & GPIO0_MASK) {
  58             if (GPIOA_INT_STAT & 0x80)
  59                 microsd_int();
  60         }
  61 #endif
  62         else if (CPU_HI_INT_STAT & GPIO1_MASK) {
  63             if (GPIOF_INT_STAT & 0xff)
  64                 button_int();
  65             if (GPIOH_INT_STAT & 0xc0)
  66                 clickwheel_int();
  67         }
  68 #elif defined(SANSA_C200) && defined(HAVE_HOTSWAP)
  69         else if (CPU_HI_INT_STAT & GPIO2_MASK) {
  70             if (GPIOL_INT_STAT & 0x08)
  71                 microsd_int();
  72         }
  73 #elif defined(MROBE_100)
  74         else if (CPU_HI_INT_STAT & GPIO0_MASK) {
  75             if (GPIOD_INT_STAT & 0x2)
  76                 button_int();
  77         }
  78 #endif
  79 #ifdef HAVE_USBSTACK
  80         else if (CPU_INT_STAT & USB_MASK) {
  81             usb_drv_int();
  82         }
  83 #endif
  84     } else {
  85         if (COP_INT_STAT & TIMER2_MASK)
  86             TIMER2();
  87     }
  88 }
  89 #endif /* BOOTLOADER */
  90
  91 /* TODO: The following function has been lifted straight from IPL, and
  92    hence has a lot of numeric addresses used straight. I'd like to use
  93    #defines for these, but don't know what most of them are for or even what
  94    they should be named. Because of this I also have no way of knowing how
  95    to extend the funtions to do alternate cache configurations. */
  96
  97 #ifndef BOOTLOADER
  98 void flush_icache(void) ICODE_ATTR;
  99 void flush_icache(void)
 100 {
 101     if (CACHE_CTL & CACHE_CTL_ENABLE)
 102     {
 103         CACHE_OPERATION |= CACHE_OP_FLUSH;
 104         while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
 105     }
 106 }
 107
 108 void invalidate_icache(void) ICODE_ATTR;
 109 void invalidate_icache(void)
 110 {
 111     if (CACHE_CTL & CACHE_CTL_ENABLE)
 112     {
 113         CACHE_OPERATION |= CACHE_OP_FLUSH | CACHE_OP_INVALIDATE;
 114         while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
 115         nop; nop; nop; nop;
 116     }
 117 }
 118
 119 static void init_cache(void)
 120 {
 121 /* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
 122
 123     /* cache init mode */
 124     CACHE_CTL |= CACHE_CTL_INIT;
 125
 126     /* what's this do? */
 127     CACHE_PRIORITY |= CURRENT_CORE == CPU ? 0x10 : 0x20;
 128
 129     /* Cache if (addr & mask) >> 16 == (mask & match) >> 16:
 130      * yes: 0x00000000 - 0x03ffffff
 131      *  no: 0x04000000 - 0x1fffffff
 132      * yes: 0x20000000 - 0x23ffffff
 133      *  no: 0x24000000 - 0x3fffffff
 134      */
 135     CACHE_MASK = 0x00001c00;
 136     CACHE_OPERATION = 0xfc0;
 137
 138     /* enable cache */
 139     CACHE_CTL |= CACHE_CTL_INIT | CACHE_CTL_ENABLE | CACHE_CTL_RUN;
 140     nop; nop; nop; nop;
 141 }
 142 #endif /* !BOOTLOADER */
 143
 144 /* We need this for Sansas since we boost the cpu in their bootloader */
 145 #if !defined(BOOTLOADER) || defined(SANSA_E200) || defined(SANSA_C200)
 146 void scale_suspend_core(bool suspend) ICODE_ATTR;
 147 void scale_suspend_core(bool suspend)
 148 {
 149     unsigned int core = CURRENT_CORE;
 150     IF_COP( unsigned int othercore = 1 - core; )
 151     static int oldstatus IBSS_ATTR;
 152
 153     if (suspend)
 154     {
 155         oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
 156         IF_COP( PROC_CTL(othercore) = 0x40000000; nop; )
 157         PROC_CTL(core) = 0x48000003; nop;
 158     }
 159     else
 160     {
 161         PROC_CTL(core) = 0x4800001f; nop;
 162         IF_COP( PROC_CTL(othercore) = 0x00000000; nop; )
 163         restore_interrupt(oldstatus);
 164     }
 165 }
 166
 167 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 168 void set_cpu_frequency(long frequency) ICODE_ATTR;
 169 void set_cpu_frequency(long frequency)
 170 #else
 171 static void pp_set_cpu_frequency(long frequency)
 172 #endif
 173 {
 174 #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
 175     spinlock_lock(&boostctrl_spin);
 176 #endif
 177
 178     switch (frequency)
 179     {
 180       /* Note1: The PP5022 PLL must be run at >= 96MHz
 181        * Bits 20..21 select the post divider (1/2/4/8).
 182        * PP5026 is similar to PP5022 except it doesn't
 183        * have this limitation (and the post divider?)
 184        * Note2: CLOCK_SOURCE is set via 0=32kHz, 1=16MHz,
 185        * 2=24MHz, 3=33MHz, 4=48MHz, 5=SLOW, 6=FAST, 7=PLL.
 186        * SLOW = 24MHz / (DIV_SLOW + 1), DIV = Bits 16-19
 187        * FAST = PLL   / (DIV_FAST + 1), DIV = Bits 20-23 */
 188       case CPUFREQ_SLEEP:
 189         cpu_frequency =  CPUFREQ_SLEEP;
 190         PLL_CONTROL  |=  0x0c000000;
 191         scale_suspend_core(true);
 192         CLOCK_SOURCE  =  0x20000000; /* source #1, #2, #3, #4: 32kHz (#2 active) */
 193         scale_suspend_core(false);
 194         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
 195         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
 196         break;
 197
 198       case CPUFREQ_MAX:
 199         cpu_frequency = CPUFREQ_MAX;
 200         DEV_INIT2    |= INIT_PLL;   /* enable PLL power */
 201         PLL_CONTROL  |= 0x88000000; /* enable PLL */
 202         scale_suspend_core(true);
 203         CLOCK_SOURCE  = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 204         DEV_TIMING1   = 0x00000303;
 205         scale_suspend_core(false);
 206 #if   defined(IPOD_MINI2G)
 207         MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
 208 #elif defined(IPOD_NANO)
 209         IDE0_CFG     |= 0x10000000; /* set ">65MHz" bit */
 210 #endif
 211 #if CONFIG_CPU == PP5020
 212         PLL_CONTROL   = 0x8a020a03; /* 80 MHz = 10/3 * 24MHz */
 213         PLL_STATUS    = 0xd19b;     /* unlock frequencies > 66MHz */
 214         PLL_CONTROL   = 0x8a020a03; /* repeat setup */
 215         udelay(500);                /* wait for relock */
 216 #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
 217         PLL_CONTROL   = 0x8a121403; /*  80 MHz = (20/3 * 24MHz) / 2 */
 218         while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
 219 #endif
 220         scale_suspend_core(true);
 221         DEV_TIMING1   = 0x00000808;
 222         CLOCK_SOURCE  = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */
 223         scale_suspend_core(false);
 224         break;
 225 #if 0 /******** CPUFREQ_NORMAL = 24MHz without PLL ********/
 226       case CPUFREQ_NORMAL:
 227         cpu_frequency =  CPUFREQ_NORMAL;
 228         PLL_CONTROL  |=  0x08000000;
 229         scale_suspend_core(true);
 230         CLOCK_SOURCE  =  0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 231         DEV_TIMING1   =  0x00000303;
 232 #if   defined(IPOD_MINI2G)
 233         MLCD_SCLK_DIV =  0x00000000; /* Mono LCD bridge serial clock divider */
 234 #elif defined(IPOD_NANO)
 235         IDE0_CFG     &= ~0x10000000; /* clear ">65MHz" bit */
 236 #endif
 237         scale_suspend_core(false);
 238         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
 239         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
 240         break;
 241 #else /******** CPUFREQ_NORMAL = 30MHz with PLL ********/
 242     case CPUFREQ_NORMAL:
 243         cpu_frequency = CPUFREQ_NORMAL;
 244         DEV_INIT2    |= INIT_PLL;   /* enable PLL power */
 245         PLL_CONTROL  |= 0x88000000; /* enable PLL */
 246         scale_suspend_core(true);
 247         CLOCK_SOURCE  = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 248         DEV_TIMING1   = 0x00000303;
 249         scale_suspend_core(false);
 250 #if   defined(IPOD_MINI2G)
 251         MLCD_SCLK_DIV =  0x00000000; /* Mono LCD bridge serial clock divider */
 252 #elif defined(IPOD_NANO)
 253         IDE0_CFG     &= ~0x10000000; /* clear ">65MHz" bit */
 254 #endif
 255 #if CONFIG_CPU == PP5020
 256         PLL_CONTROL   = 0x8a020504; /* 30 MHz = 5/4 * 24MHz */
 257         udelay(500);                /* wait for relock */
 258 #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
 259         PLL_CONTROL   = 0x8a220501; /* 30 MHz = (5/1 * 24MHz) / 4 */
 260         while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
 261 #endif
 262         scale_suspend_core(true);
 263         DEV_TIMING1   = 0x00000303;
 264         CLOCK_SOURCE  = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */
 265         scale_suspend_core(false);
 266         break;
 267 #endif /******** CPUFREQ_NORMAL end ********/
 268       default:
 269         cpu_frequency =  CPUFREQ_DEFAULT;
 270         PLL_CONTROL  |=  0x08000000;
 271         scale_suspend_core(true);
 272         CLOCK_SOURCE  =  0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 273         DEV_TIMING1   =  0x00000303;
 274 #if   defined(IPOD_MINI2G)
 275         MLCD_SCLK_DIV =  0x00000000; /* Mono LCD bridge serial clock divider */
 276 #elif defined(IPOD_NANO)
 277         IDE0_CFG     &= ~0x10000000; /* clear ">65MHz" bit */
 278 #endif
 279         scale_suspend_core(false);
 280         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
 281         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
 282         break;
 283     }
 284
 285 #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
 286     spinlock_unlock(&boostctrl_spin);
 287 #endif
 288 }
 289 #endif /* !BOOTLOADER || SANSA_E200 || SANSA_C200 */
 290
 291 void system_init(void)
 292 {
 293 #ifndef BOOTLOADER
 294     if (CURRENT_CORE == CPU)
 295     {
 296 #if defined (IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_COLOR)
 297         /* set minimum startup configuration */
 298         DEV_EN         = 0xc2000124;
 299         DEV_EN2        = 0x00002000;
 300         CACHE_PRIORITY = 0x0000003f;
 301         GPO32_VAL      = 0x20000000;
 302         DEV_INIT1      = 0xdc000000;
 303         DEV_INIT2      = 0x40000000;
 304
 305         /* reset all allowed devices */
 306         DEV_RS         = 0x3ffffef8;
 307         DEV_RS2        = 0xffffdfff;
 308         DEV_RS         = 0x00000000;
 309         DEV_RS2        = 0x00000000;
 310 #elif defined (IPOD_VIDEO)
 311         /* set minimum startup configuration */
 312         DEV_EN         = 0xc2000124;
 313         DEV_EN2        = 0x00000000;
 314         CACHE_PRIORITY = 0x0000003f;
 315         GPO32_VAL      = 0x00004000;
 316         DEV_INIT1      = 0x00000000;
 317         DEV_INIT2      = 0x40000000;
 318
 319         /* reset all allowed devices */
 320         DEV_RS         = 0x3ffffef8;
 321         DEV_RS2        = 0xffffffff;
 322         DEV_RS         = 0x00000000;
 323         DEV_RS2        = 0x00000000;
 324 #elif defined (IPOD_NANO)
 325         /* set minimum startup configuration */
 326         DEV_EN         = 0xc2000124;
 327         DEV_EN2        = 0x00002000;
 328         CACHE_PRIORITY = 0x0000003f;
 329         GPO32_VAL      = 0x50000000;
 330         DEV_INIT1      = 0xa8000000;
 331         DEV_INIT2      = 0x40000000;
 332
 333         /* reset all allowed devices */
 334         DEV_RS         = 0x3ffffef8;
 335         DEV_RS2        = 0xffffdfff;
 336         DEV_RS         = 0x00000000;
 337         DEV_RS2        = 0x00000000;
 338 #elif defined(SANSA_C200) || defined (SANSA_E200)
 339         /* set minimum startup configuration */
 340         DEV_EN         = 0xc4000124;
 341         DEV_EN2        = 0x00000000;
 342         CACHE_PRIORITY = 0x0000003f;
 343         GPO32_VAL      = 0x10000000;
 344         DEV_INIT1      = 0x54000000;
 345         DEV_INIT2      = 0x40000000;
 346
 347         /* reset all allowed devices */
 348         DEV_RS         = 0x3bfffef8;
 349         DEV_RS2        = 0xffffffff;
 350         DEV_RS         = 0x00000000;
 351         DEV_RS2        = 0x00000000;
 352 #elif defined(IPOD_4G)
 353         /* set minimum startup configuration */
 354         DEV_EN         = 0xc2020124;
 355         DEV_EN2        = 0x00000000;
 356         CACHE_PRIORITY = 0x0000003f;
 357         GPO32_VAL      = 0x02000000;
 358         DEV_INIT1      = 0x00000000;
 359         DEV_INIT2      = 0x40000000;
 360
 361         /* reset all allowed devices */
 362         DEV_RS         = 0x3ffdfef8;
 363         DEV_RS2        = 0xffffffff;
 364         DEV_RS         = 0x00000000;
 365         DEV_RS2        = 0x00000000;
 366 #elif defined (IPOD_MINI)
 367         /* to be done */
 368 #elif defined (IPOD_MINI2G)
 369         /* to be done */
 370 #elif defined (MROBE_100)
 371         /* to be done */
 372 #elif defined (ELIO_TPJ1022)
 373         /* to be done */
 374 #endif
 375
 376 #if !defined(SANSA_E200) && !defined(SANSA_C200) && !defined(PHILIPS_SA9200)
 377         /* Remap the flash ROM on CPU, keep hidden from COP:
 378          * 0x00000000-0x3fffffff = 0x20000000-0x23ffffff */
 379         MMAP1_LOGICAL  = 0x20003c00;
 380         MMAP1_PHYSICAL = 0x00003084 |
 381             MMAP_PHYS_READ_MASK | MMAP_PHYS_WRITE_MASK |
 382             MMAP_PHYS_DATA_MASK | MMAP_PHYS_CODE_MASK;
 383 #endif
 384
 385         /* disable all irqs */
 386         COP_HI_INT_DIS      = -1;
 387         CPU_HI_INT_DIS      = -1;
 388         HI_INT_FORCED_CLR   = -1;
 389
 390         COP_INT_DIS         = -1;
 391         CPU_INT_DIS         = -1;
 392         INT_FORCED_CLR      = -1;
 393
 394         GPIOA_INT_EN        = 0;
 395         GPIOB_INT_EN        = 0;
 396         GPIOC_INT_EN        = 0;
 397         GPIOD_INT_EN        = 0;
 398         GPIOE_INT_EN        = 0;
 399         GPIOF_INT_EN        = 0;
 400         GPIOG_INT_EN        = 0;
 401         GPIOH_INT_EN        = 0;
 402         GPIOI_INT_EN        = 0;
 403         GPIOJ_INT_EN        = 0;
 404         GPIOK_INT_EN        = 0;
 405         GPIOL_INT_EN        = 0;
 406
 407 #if defined(SANSA_E200) || defined(SANSA_C200) || defined(PHILIPS_SA9200)
 408         /* outl(0x00000000, 0x6000b000); */
 409         outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */
 410 #endif
 411
 412 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 413 #if NUM_CORES > 1
 414         cpu_boost_init();
 415 #endif
 416 #else
 417         pp_set_cpu_frequency(CPUFREQ_MAX);
 418 #endif
 419     }
 420
 421     init_cache();
 422 #else /* BOOTLOADER */
 423     if (CURRENT_CORE == CPU)
 424     {
 425 #if defined(SANSA_C200) || defined (SANSA_E200)
 426         pp_set_cpu_frequency(CPUFREQ_MAX);
 427 #endif
 428     }
 429 #endif /* BOOTLOADER */
 430 }
 431
 432 void system_reboot(void)
 433 {
 434     /* Reboot */
 435 #if defined(SANSA_E200) || defined(SANSA_C200) || defined(PHILIPS_SA9200)
 436     CACHE_CTL &= ~CACHE_CTL_VECT_REMAP;
 437
 438     /* Magic used by the c200 OF: 0x23066000
 439        Magic used by the c200 BL: 0x23066b7b
 440        In both cases, the OF executes these 2 commands from iram. */
 441     STRAP_OPT_A = 0x23066b7b;
 442     DEV_RS = DEV_SYSTEM;
 443 #else
 444     DEV_RS |= DEV_SYSTEM;
 445 #endif
 446     /* wait until reboot kicks in */
 447     while (1);
 448 }
 449
 450 int system_memory_guard(int newmode)
 451 {
 452     (void)newmode;
 453     return 0;
 454 }