firmware/target/arm/system-arm.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Alan Korr
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 #ifndef SYSTEM_ARM_H
  20 #define SYSTEM_ARM_H
  21
  22 #define nop \
  23   asm volatile ("nop")
  24
  25
  26 /* This gets too complicated otherwise with all the ARM variation and would
  27    have conflicts with another system-target.h elsewhere so include a
  28    subheader from here. */
  29
  30 static inline uint16_t swap16(uint16_t value)
  31     /*
  32       result[15..8] = value[ 7..0];
  33       result[ 7..0] = value[15..8];
  34     */
  35 {
  36     return (value >> 8) | (value << 8);
  37 }
  38
  39 static inline uint32_t swap32(uint32_t value)
  40     /*
  41       result[31..24] = value[ 7.. 0];
  42       result[23..16] = value[15.. 8];
  43       result[15.. 8] = value[23..16];
  44       result[ 7.. 0] = value[31..24];
  45     */
  46 {
  47     uint32_t tmp;
  48
  49     asm volatile (
  50         "eor %1, %0, %0, ror #16 \n\t"
  51         "bic %1, %1, #0xff0000   \n\t"
  52         "mov %0, %0, ror #8      \n\t"
  53         "eor %0, %0, %1, lsr #8  \n\t"
  54         : "+r" (value), "=r" (tmp)
  55     );
  56     return value;
  57 }
  58
  59 static inline uint32_t swap_odd_even32(uint32_t value)
  60 {
  61     /*
  62       result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
  63       result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
  64     */
  65     uint32_t tmp;
  66
  67     asm volatile (                    /* ABCD      */
  68         "bic %1, %0, #0x00ff00  \n\t" /* AB.D      */
  69         "bic %0, %0, #0xff0000  \n\t" /* A.CD      */
  70         "mov %0, %0, lsr #8     \n\t" /* .A.C      */
  71         "orr %0, %0, %1, lsl #8 \n\t" /* B.D.|.A.C */
  72         : "+r" (value), "=r" (tmp)    /* BADC      */
  73     );
  74     return value;
  75 }
  76
  77 static inline void enable_fiq(void)
  78 {
  79     /* Clear FIQ disable bit */
  80     asm volatile (
  81         "mrs     r0, cpsr         \n"\
  82         "bic     r0, r0, #0x40    \n"\
  83         "msr     cpsr_c, r0         "
  84         : : : "r0"
  85     );
  86 }
  87
  88 static inline void disable_fiq(void)
  89 {
  90     /* Set FIQ disable bit */
  91     asm volatile (
  92         "mrs     r0, cpsr         \n"\
  93         "orr     r0, r0, #0x40    \n"\
  94         "msr     cpsr_c, r0         "
  95         : : : "r0"
  96     );
  97 }
  98
  99 /* This one returns the old status */
 100 #define IRQ_ENABLED      0x00
 101 #define IRQ_DISABLED     0x80
 102 #define IRQ_STATUS       0x80
 103 #define FIQ_ENABLED      0x00
 104 #define FIQ_DISABLED     0x40
 105 #define FIQ_STATUS       0x40
 106 #define IRQ_FIQ_ENABLED  0x00
 107 #define IRQ_FIQ_DISABLED 0xc0
 108 #define IRQ_FIQ_STATUS   0xc0
 109 #define HIGHEST_IRQ_LEVEL IRQ_DISABLED
 110
 111 #define set_irq_level(status)  set_interrupt_status((status), IRQ_STATUS)
 112 #define set_fiq_status(status) set_interrupt_status((status), FIQ_STATUS)
 113
 114 static inline int set_interrupt_status(int status, int mask)
 115 {
 116     unsigned long cpsr;
 117     int oldstatus;
 118     /* Read the old levels and set the new ones */
 119     asm volatile (
 120         "mrs    %1, cpsr        \n"
 121         "bic    %0, %1, %[mask] \n"
 122         "orr    %0, %0, %2      \n"
 123         "msr    cpsr_c, %0      \n"
 124         : "=&r,r"(cpsr), "=&r,r"(oldstatus)
 125         : "r,i"(status & mask), [mask]"i,i"(mask)
 126     );
 127
 128     return oldstatus;
 129 }
 130
 131 #endif /* SYSTEM_ARM_H */