firmware/target/arm/ata-target.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 by Barry Wardell
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19
  20 #ifdef CPU_PP
  21
  22 /* primary channel */
  23 #define ATA_DATA        (*((volatile unsigned short*)(IDE_BASE + 0x1e0)))
  24 #define ATA_ERROR       (*((volatile unsigned char*)(IDE_BASE + 0x1e4)))
  25 #define ATA_NSECTOR     (*((volatile unsigned char*)(IDE_BASE + 0x1e8)))
  26 #define ATA_SECTOR      (*((volatile unsigned char*)(IDE_BASE + 0x1ec)))
  27 #define ATA_LCYL        (*((volatile unsigned char*)(IDE_BASE + 0x1f0)))
  28 #define ATA_HCYL        (*((volatile unsigned char*)(IDE_BASE + 0x1f4)))
  29 #define ATA_SELECT      (*((volatile unsigned char*)(IDE_BASE + 0x1f8)))
  30 #define ATA_COMMAND     (*((volatile unsigned char*)(IDE_BASE + 0x1fc)))
  31 #define ATA_CONTROL     (*((volatile unsigned char*)(IDE_BASE + 0x3f8)))
  32
  33 #define STATUS_BSY      0x80
  34 #define STATUS_RDY      0x40
  35 #define STATUS_DF       0x20
  36 #define STATUS_DRQ      0x08
  37 #define STATUS_ERR      0x01
  38 #define ERROR_ABRT      0x04
  39
  40 #define WRITE_PATTERN1  0xa5
  41 #define WRITE_PATTERN2  0x5a
  42 #define WRITE_PATTERN3  0xaa
  43 #define WRITE_PATTERN4  0x55
  44
  45 #define READ_PATTERN1   0xa5
  46 #define READ_PATTERN2   0x5a
  47 #define READ_PATTERN3   0xaa
  48 #define READ_PATTERN4   0x55
  49
  50 #define READ_PATTERN1_MASK 0xff
  51 #define READ_PATTERN2_MASK 0xff
  52 #define READ_PATTERN3_MASK 0xff
  53 #define READ_PATTERN4_MASK 0xff
  54
  55 #if (CONFIG_CPU == PP5002)
  56
  57 #define SET_REG(reg,val) do { reg = (val); \
  58                               while (!(IDE_CFG_STATUS & 0x40)); \
  59                          } while (0)
  60 #define SET_16BITREG(reg,val) reg = (val)
  61
  62 /* Plain C reading and writing. See comment in ata-as-arm.S */
  63
  64 #elif defined CPU_PP502x
  65
  66 #define SET_REG(reg,val) reg = (val)
  67 #define SET_16BITREG(reg,val) reg = (val)
  68
  69 /* asm optimized reading and writing */
  70 #define ATA_OPTIMIZED_READING
  71 #define ATA_OPTIMIZED_WRITING
  72 void copy_read_sectors(unsigned char* buf, int wordcount);
  73 void copy_write_sectors(const unsigned char* buf, int wordcount);
  74
  75 #endif /* CONFIG_CPU */
  76
  77 #endif
  78
  79 void ata_reset(void);
  80 void ata_enable(bool on);
  81 bool ata_is_coldstart(void);
  82 void ata_device_init(void);